merge in jb-mr2-release history after reset to jb-mr2-dev

The GNU dynamic linker silently ignores a DT_PREINIT_ARRAY section
in a shared library. We had ineffectual code that tried to report
an error, which I tried to fix but got wrong --- my version still
wouldn't report the error to the caller, but would prevent us from
continuing to call constructors.

Bug: 8825226

(cherry picked from commit 8147d3c284)

Change-Id: Iad8e7e3743d1a5e6bd1d44ef40b1ab3499cb64f2

ABI-bugs.txt

@@ -0,0 +1,15 @@
+KNOWN ABI BUGS
+--------------
+
+  time_t is 32-bit. http://b/5819737
+
+  off_t is 32-bit. There is off64_t, but no _FILE_OFFSET_BITS support.
+
+  sigset_t is too small on ARM and x86 (but correct on MIPS), so support
+  for real-time signals is broken. http://b/5828899
+
+  Too few TLS slots mean we can't allocate 128 pthread_key_t instances,
+  which POSIX says should be the minimum.
+
+  atexit(3) handlers registered by a shared library aren't called on
+  dlclose(3); this only affects ARM. http://b/4998315

Android.mk

@@ -16,9 +16,4 @@
 
 LOCAL_PATH := $(call my-dir)
 
-ifneq ($(TARGET_SIMULATOR),true)
-  include $(call all-subdir-makefiles)
-else
-  # The host dalvikvm needs Android's concatenated & indexed timezone data.
-  include $(LOCAL_PATH)/libc/zoneinfo/Android.mk
-endif
+include $(call all-subdir-makefiles)

MAINTAINERS

@@ -1,6 +0,0 @@
-
-Bionic support for SuperH
--------------------------
-Bionic support for SuperH architecture is written by
-Shin-ichiro KAWASAKI <shinichiro.kawasaki.mg@hitachi.com>
-and Contributed to Android by Hitachi, Ltd. and Renesas Solutions Corp.

ThirdPartyProject.prop

@@ -1,10 +0,0 @@
-# Copyright 2010 Google Inc. All Rights Reserved.
-#Fri Jul 16 10:03:08 PDT 2010
-currentVersion=Unknown
-version=Unknown
-isNative=true
-feedurl=http\://www.openbsd.org/security.html
-name=openbsd
-keywords=openbsd
-onDevice=true
-homepage=http\://openbsd.org

libc/Jamfile

@@ -1,441 +0,0 @@
-# This file is used to build the Bionic library with the Jam build
-# tool. For info, see www.perforce.com/jam/jam.html
-#
-
-BIONIC_TOP ?= $(DOT) ;
-
-DEBUG = 1 ;
-
-# pattern used for automatic heade inclusion detection
-HDRPATTERN = "^[ 	]*#[ 	]*include[ 	]*[<\"]([^\">]*)[\">].*$" ;
-
-
-# debugging support, simply define the DEBUG variable to activate verbose output
-rule Debug
-{
-    if $(DEBUG) {
-        Echo $(1) ;
-    }
-}
-
-# return all elements from $(1) that are not in $(2)
-rule Filter  list : filter
-{
-    local result = ;
-    local item ;
-    for item in $(list) {
-        if ! $(item) in $(filter) {
-            result += $(item) ;
-        }
-    }
-    return $(result) ;
-}
-
-
-# reverse a list of elements
-rule Reverse  list
-{
-    local  result = ;
-    local  item ;
-
-    for item in $(list) {
-        result = $(item) $(result) ;
-    }
-    return $(result) ;
-}
-
-
-# decompose a path into a list of elements
-rule PathDecompose  dir
-{
-    local  result ;
-
-    while $(dir:D)
-    {
-        if ! $(dir:BS) {  # for rooted paths like "/foo"
-            break ;
-        }
-        result = $(dir:BS) $(result) ;
-        dir    = $(dir:D) ;
-    }
-    result = $(dir) $(result) ;
-    return $(result) ;
-}
-
-
-# simply a file path, i.e. get rid of . or .. when possible
-rule _PathSimplify  dir
-{
-    local  result = ;
-    local  dir2 d ;
-
-    dir  = [ PathDecompose $(dir) ] ;
-
-    # get rid of any single dot
-    dir2 = ;
-    for d in $(dir) {
-        if $(d) = "." {
-            continue ;
-        }
-        dir2 += $(d) ;
-    }
-
-    # get rid of .. when possible
-    for d in $(dir2) {
-        if $(d) = ".." && $(result) {
-            result = $(result[2-]) ;
-        }
-        else
-            result = $(d) $(result) ;
-    }
-
-    # now invert the result
-    result = [ Reverse $(result) ] ;
-    if ! $(result) {
-        result = "." ;
-    }
-    return $(result:J="/") ;
-}
-
-
-rule PathSimplify  dirs
-{
-    local result ;
-    local d ;
-    for d in $(dirs) {
-        result += [ _PathSimplify $(d) ] ;
-    }
-    return $(result) ;
-}
-
-
-# retrieve list of subdirectories
-rule ListSubDirs  paths
-{
-    local  result  = ;
-    local  entry ;
-    for entry in [ Glob $(paths) : * ] {
-        if ! $(entry:S) {
-            result += $(entry) ;
-        }
-    }
-    return [ PathSimplify $(result) ] ;
-}
-
-
-# retrieve list of sources in a given directory
-rule ListSources  path
-{
-    return [ Glob $(path) : *.S *.c ] ;
-}
-
-
-# find the prebuilt directory
-#
-if ! $(TOP) {
-    Echo "Please define TOP as the root of your device build tree" ;
-    Exit ;
-}
-
-Debug "OS is" $(OS) ;
-Debug "CPU is" $(CPU) ;
-
-if $(OS) = LINUX
-{
-    PREBUILT = $(TOP)/prebuilt/Linux ;
-}
-else if $(OS) = MACOSX
-{
-    switch $(CPU) {
-        case i386 : PREBUILT = $(TOP)/prebuilt/darwin-x86 ; break ;
-        case ppc  : PREBUILT = $(TOP)/prebuilt/darwin-ppc ; break ;
-        case *    : Echo "unsupported CPU" "$(CPU) !!" ;
-                    Echo "Please contact digit@google.com for help" ;
-                    Exit ;
-    }
-}
-else
-{
-    Echo "Unsupported operating system" $(OS) ;
-    Echo "Please contact digit@google.com for help" ;
-    Exit ;
-}
-
-Debug "TOP is" $(TOP) ;
-Debug "PREBUILT is" $(PREBUILT) ;
-
-
-# check architectures and setup toolchain variables
-#
-SUPPORTED_ARCHS = x86 arm ;
-
-ARCH ?= $(SUPPORTED_ARCHS) ;
-
-if ! $(ARCH) in $(SUPPORTED_ARCHS) {
-    Echo "The variable ARCH contains an unsupported value, use one or more of these instead" ;
-    Echo "separated by spaces:" $(SUPPORTED_ARCHS) ;
-    Exit ;
-}
-
-x86_TOOLSET_PREFIX ?= "" ;
-arm_TOOLSET_PREFIX ?= $(TOP)/prebuilt/Linux/toolchain-4.1.1/bin/arm-elf- ;
-
-for arch in $(ARCH) {
-    CC_$(arch)  = $($(arch)_TOOLSET_PREFIX)gcc ;
-    C++_$(arch) = $($(arch)_TOOLSET_PREFIX)g++ ;
-    AR_$(arch)  = $($(arch)_TOOLSET_PREFIX)ar ;
-}
-
-
-# the list of arch-independent source subdirectories
-BIONIC_SRC_SUBDIRS = string ;
-BIONIC_x86_SUBDIRS = ;
-BIONIC_arm_SUBDIRS = ;
-
-CFLAGS   = -O0 -g -W ;
-
-
-
-# find sources in a given list of subdirectories
-rule FindSources  dirs
-{
-    local dir ;
-
-    for dir in $(dirs)
-    {
-        local LOCAL_SRC NO_LOCAL_SRC ;
-
-        if [ Glob $(dir) : rules.jam ] {
-            include $(dir)/rules.jam ;
-            if $(LOCAL_SRC) {
-                _sources = $(LOCAL_SRC) ;
-            }
-            else {
-                _sources = [ Glob $(dir) : *.S *.c ] ;
-                _sources = $(_sources:BS) ;
-            }
-            if $(NO_LOCAL_SRC) {
-                _sources = [ Filter $(_sources) : $(NO_LOCAL_SRC) ] ;
-            }
-            sources += $(dir)/$(_sources) ;
-        }
-        else
-            sources += [ ListSources $(dir) ] ;
-    }
-}
-
-# Compile a given object file from a source
-rule Compile  object : source
-{
-    Depends $(object) : $(source) ;
-    Depends bionic : $(object) ;
-    Clean clean : $(object) ;
-
-    MakeLocate $(object) : $(OUT) ;
-
-
-    CC on $(object)       = $(CC_$(arch)) ;
-    CFLAGS on $(object)   = $(CFLAGS) ;
-    INCLUDES on $(object) = $(INCLUDES) ;
-    DEFINES on $(object)  = $(DEFINES) ;
-
-    HDRRULE on $(>) = HdrRule ;
-    HDRSCAN on $(>) = $(HDRPATTERN) ;
-    HDRSEARCH on $(>) = $(INCLUDES) ;
-    HDRGRIST on $(>) = $(HDRGRIST) ;
-}
-
-
-actions Compile
-{
-    $(CC) -c -o $(1) $(CFLAGS) -I$(INCLUDES) -D$(DEFINES) $(2)
-}
-
-
-rule RmTemps
-{
-    Temporary $(2) ;
-}
-
-actions quietly updated piecemeal together RmTemps
-{
-    rm -f $(2)
-}
-
-actions Archive
-{
-    $(AR) ru $(1) $(2)
-}
-
-rule Library  library : objects
-{
-    local  obj ;
-
-    if ! $(library:S) {
-        library = $(library:S=.a) ;
-    }
-    library = $(library:G=<$(arch)>) ;
-
-    Depends all : $(library) ;
-
-    if ! $(library:D) {
-        MakeLocate $(library) $(library)($(objects:BS)) : $(OUT) ;
-    }
-
-    Depends $(library) : $(library)($(objects:BS)) ;
-    for obj in $(objects) {
-        Depends $(library)($(obj:BS)) : $(obj) ;
-    }
-
-    Clean clean : $(library) ;
-
-    AR on $(library) = $(AR_$(arch)) ;
-    Archive $(library) : $(objects) ;
-
-    RmTemps $(library) : $(objects) ;
-}
-
-
-rule  ProcessDir
-{
-    local CFLAGS   = $(CFLAGS) ;
-    local DEFINES  = $(DEFINES) ;
-    local INCLUDES = $(INCLUDES) ;
-    local local_rules = [ Glob $(1) : rules.jam ] ;
-    local source sources ;
-
-    if $(local_rules) {
-        local LOCAL_CFLAGS LOCAL_DEFINES LOCAL_INCLUDES LOCAL_SRC NO_LOCAL_SRC ;
-
-        include $(local_rules) ;
-        CFLAGS   += $(LOCAL_CFLAGS) ;
-        DEFINES  += $(LOCAL_DEFINES) ;
-        INCLUDES += $(LOCAL_INCLUDES) ;
-
-        if $(LOCAL_SRC) {
-            sources = $(LOCAL_SRC) ;
-        }
-        else {
-            sources = [ Glob $(1) : *.S *.c ] ;
-            sources = $(sources:BS) ;
-        }
-
-        if $(NO_LOCAL_SRC) {
-            sources = [ Filter $(sources) : $(NO_LOCAL_SRC) ] ;
-        }
-
-        sources = $(1)/$(sources) ;
-    }
-    else
-        sources = [ Glob $(1) : *.S *.c ] ;
-
-    for source in $(sources) {
-        local name = $(source:B) ;
-
-        if $(source:S) = ".S" {
-            # record the list of assembler sources
-            ASSEMBLER_SOURCES += $(name) ;
-        }
-        else if $(source:S) = ".c" && $(name) in $(ASSEMBLER_SOURCES) {
-            # skip C source file if corresponding assembler exists
-            continue ;
-        }
-
-        objname = <$(arch)>$(name).o  ;
-
-        Compile $(objname) : $(source) ;
-        ALL_OBJECTS += $(objname) ;
-    }
-}
-
-rule ProcessDirs
-{
-    local  dir ;
-    for dir in $(1) {
-        ProcessDir $(dir) ;
-    }
-}
-
-INCLUDES_x86 = /usr/src/linux/include ;
-
-INCLUDES_arm = ../kernel_headers
-               include/arch/arm
-               include/bits32
-               ;
-
-INCLUDES = include stdio string stdlib .
-           ../msun/include
-           ;
-
-DEFINES  = ANDROID_CHANGES
-           USE_LOCKS
-           REALLOC_ZERO_BYTES_FREES
-           _LIBC=1
-           SOFTFLOAT
-           FLOATING_POINT
-           NEED_PSELECT=1
-           ANDROID
-           ;
-
-CFLAGS_x86 = ;
-
-
-for arch in $(ARCH)
-{
-    local ARCH_DIR = $(BIONIC_TOP)/arch-$(arch) ;
-    local INCLUDES = $(INCLUDES_$(arch)) $(ARCH_DIR)/include $(INCLUDES) ;
-    local DEFINES  = $(DEFINES_$(arch)) $(DEFINES) ARCH=$(arch)  ;
-    local CFLAGS   = $(CFLAGS) $(CFLAGS_$(arch)) ;
-    local OUT      = out/$(arch) ;
-    local ASSEMBLER_SOURCES ALL_OBJECTS ;
-
-    ProcessDirs [ ListSubDirs $(ARCH_DIR) ] ;
-    ProcessDirs stdlib stdio unistd string tzcode inet ;
-    ProcessDirs [ ListSubDirs netbsd ] ;
-    ProcessDirs bionic ;
-
-    Library bionic : $(ALL_OBJECTS) ;
-}
-
-BIONIC_SEARCH = $(BIONIC_TOP)/include ;
-
-
-
-# /HdrRule source : headers ;
-#
-# Arranges the proper dependencies when the file _source_ includes the files
-# _headers_ through the #include C preprocessor directive
-#
-# this rule is not intendend to be called explicitely. It is called
-# automatically during header scanning on sources handled by the @Object
-# rule (e.g. sources in @Main or @Library rules)
-#
-rule HdrRule
-{
-    # HdrRule source : headers ;
-
-    # N.B.  This rule is called during binding, potentially after
-    # the fate of many targets has been determined, and must be
-    # used with caution: don't add dependencies to unrelated
-    # targets, and don't set variables on $(<).
-
-    # Tell Jam that anything depending on $(<) also depends on $(>),
-    # set SEARCH so Jam can find the headers, but then say we don't
-    # care if we can't actually find the headers (they may have been
-    # within ifdefs),
-
-    local s = $(>:G=$(HDRGRIST:E)) ;
-
-    Includes $(<) : $(s) ;
-    SEARCH on $(s) = $(HDRSEARCH) ;
-    NoCare $(s) ;
-
-    # Propagate on $(<) to $(>)
-
-    HDRSEARCH on $(s) = $(HDRSEARCH) ;
-    HDRSCAN on $(s) = $(HDRSCAN) ;
-    HDRRULE on $(s) = $(HDRRULE) ;
-    HDRGRIST on $(s) = $(HDRGRIST) ;
-}
-
-

libc/README

@@ -1,54 +0,0 @@
-Welcome to Bionic, Android's small and custom C library for the Android
-platform.
-
-Bionic is mainly a port of the BSD C library to our Linux kernel with the
-following additions/changes:
-
-- no support for locales
-- no support for wide chars (i.e. multi-byte characters)
-- its own smallish implementation of pthreads based on Linux futexes
-- support for x86, ARM and ARM thumb CPU instruction sets and kernel interfaces
-
-Bionic is released under the standard 3-clause BSD License
-
-Bionic doesn't want to implement all features of a traditional C library, we only
-add features to it as we need them, and we try to keep things as simple and small
-as possible. Our goal is not to support scaling to thousands of concurrent threads
-on multi-processors machines; we're running this on cell-phones, damnit !!
-
-Note that Bionic doesn't provide a libthread_db or a libm implementation.
-
-
-Adding new syscalls:
-====================
-
-Bionic provides the gensyscalls.py Python script to automatically generate syscall
-stubs from the list defined in the file SYSCALLS.TXT. You can thus add a new syscall
-by doing the following:
-
-- edit SYSCALLS.TXT
-- add a new line describing your syscall, it should look like:
-
-   return_type  syscall_name(parameters)    syscall_number
-
-- in the event where you want to differentiate the syscall function from its entry name,
-  use the alternate:
-
-   return_type  funcname:syscall_name(parameters)  syscall_number
-
-- additionally, if the syscall number is different between ARM and x86, use:
-
-   return_type  funcname[:syscall_name](parameters)   arm_number,x86_number
-
-- a syscall number can be -1 to indicate that the syscall is not implemented on
-  a given platform, for example:
-
-   void   __set_tls(void*)   arm_number,-1
-
-
-the comments in SYSCALLS.TXT contain more information about the line format
-
-You can also use the 'checksyscalls.py' script to check that all the syscall
-numbers you entered are correct. It does so by looking at the values defined in
-your Linux kernel headers. The script indicates where the values are incorrect
-and what is expected instead.

libc/SYSCALLS.TXT

@@ -1,13 +1,11 @@
-# this file is used to list all the syscalls that will be supported by
-# the Bionic C library. It is used to automatically generate the syscall
-# stubs, the list of syscall constants (__NR_xxxx) and the content of <linux/_unitsd.h>
+# This file is used to automatically generate bionic's the system calls stubs.
 #
-# each non comment line has the following format:
+# Each non comment line has the following format:
 #
-# return_type    func_name[:syscall_name[:call_id]]([parameter_list])  (#syscall_number|stub)
+# return_type    func_name[:syscall_name[:call_id]]([parameter_list])  (1|-1|"stub")
 #
-# note that:
-#      - syscall_name correspond to the name of the syscall, which may differ from
+# Note that:
+#      - syscall_name corresponds to the name of the syscall, which may differ from
 #        the exported function name (example: the exit syscall is implemented by the _exit()
 #        function, which is not the same as the standard C exit() function which calls it)
 #        The call_id parameter, given that func_name and syscall_name have
@@ -18,249 +16,306 @@
 #      - each parameter type is assumed to be stored on 32 bits, there is no plan to support
 #        64-bit architectures at the moment
 #
-#      - it there is "stub" instead of a syscall number, the tool will not generate any
-#        assembler template for the syscall; it's up to the bionic implementation to provide
-#        a relevant C stub
+#      - the final field can be "1", meaning: generate a stub for each architecture,
+#        taking the constants from the kernel header files.
 #
-#      - additionally, if the syscall number is different amoung ARM, x86 and SuperH, use:
-#        return_type funcname[:syscall_name](parameters) arm_number,x86_number,superh_number
+#      - the final field can be "stub" meaning: do not generate any stubs ---
+#        in this case, a hand-written custom stub must be provided.
+#        TODO: replace this with something like "custom" or "none", or remove
+#        it entirely.
 #
-# the file is processed by a python script named gensyscalls.py
+#      - the final field can be a three-element list of 1s and -1 meaning:
+#        this system call is only available on some of the architectures (1),
+#        and no stub should be generated for those architectures marked with -1.
+#        the order is arm,x86,mips.
+#        TODO: replace this with something more readable like "-arm,-mips" (meaning x86 only).
+#
+# This file is processed by a python script named gensyscalls.py.
 #
 
 # process management
-void    _exit:exit_group (int)      248,252
-void    _exit_thread:exit (int)	    1
-pid_t   __fork:fork (void)           2
-pid_t   _waitpid:waitpid (pid_t, int*, int, struct rusage*)   -1,7
-int     __waitid:waitid(int, pid_t, struct siginfo_t*, int,void*)          280,284
+void    _exit:exit_group (int)      1
+void    _exit_thread:exit (int)     1
+pid_t   __fork:fork (void)           1
+pid_t   _waitpid:waitpid (pid_t, int*, int, struct rusage*)   -1,1,1
+int     __waitid:waitid(int, pid_t, struct siginfo_t*, int,void*)          1
+pid_t   wait4(pid_t pid, int *status, int options, struct rusage *rusage)   1
 
 # NOTE: this system call is never called directly, but we list it there
 #       to have __NR_clone properly defined.
 #
-pid_t   __sys_clone:clone (int, void*, int*, void*, int*) 120
+pid_t   __sys_clone:clone (int, void*, int*, void*, int*) 1
 
-int     execve (const char*, char* const*, char* const*)  11
+int     execve (const char*, char* const*, char* const*)  1
 
-int     __setuid:setuid32 (uid_t)    213
-uid_t   getuid:getuid32 ()         199
-gid_t   getgid:getgid32 ()         200
-uid_t   geteuid:geteuid32 ()       201
-gid_t   getegid:getegid32 ()       202
-uid_t   getresuid:getresuid32 ()   209
-gid_t   getresgid:getresgid32 ()   211
-pid_t   gettid()                   224
-int     getgroups:getgroups32(int, gid_t *)    205
-pid_t   getpgid(pid_t)             132
-pid_t   getppid()		   64
-pid_t   setsid()                   66
-int     setgid:setgid32(gid_t)     214
+int     __setuid:setuid32 (uid_t)    1,1,-1
+int     __setuid:setuid (uid_t)   -1,-1,1
+uid_t   getuid:getuid32 ()         1,1,-1
+uid_t   getuid:getuid ()           -1,-1,1
+gid_t   getgid:getgid32 ()         1,1,-1
+gid_t   getgid:getgid ()           -1,-1,1
+uid_t   geteuid:geteuid32 ()       1,1,-1
+uid_t   geteuid:geteuid ()         -1,-1,1
+gid_t   getegid:getegid32 ()       1,1,-1
+gid_t   getegid:getegid ()         -1,-1,1
+uid_t   getresuid:getresuid32 (uid_t *ruid, uid_t *euid, uid_t *suid)   1,1,-1
+uid_t   getresuid:getresuid (uid_t *ruid, uid_t *euid, uid_t *suid)     -1,-1,1
+gid_t   getresgid:getresgid32 (gid_t *rgid, gid_t *egid, gid_t *sgid)   1,1,-1
+gid_t   getresgid:getresgid (gid_t *rgid, gid_t *egid, gid_t *sgid)     -1,-1,1
+pid_t   gettid()                   1
+ssize_t readahead(int, off64_t, size_t)     1
+int     getgroups:getgroups32(int, gid_t *)    1,1,-1
+int     getgroups:getgroups(int, gid_t *)      -1,-1,1
+pid_t   getpgid(pid_t)             1
+pid_t   getppid()                  1
+pid_t   getsid(pid_t)              1
+pid_t   setsid()                   1
+int     setgid:setgid32(gid_t)     1,1,-1
+int     setgid:setgid(gid_t)       -1,-1,1
 int     seteuid:seteuid32(uid_t)   stub
-int     __setreuid:setreuid32(uid_t, uid_t)   203
-int     __setresuid:setresuid32(uid_t, uid_t, uid_t)   208
-int     setresgid:setresgid32(gid_t, gid_t, gid_t)   210
-void*   __brk:brk(void*)           45
+int     __setreuid:setreuid32(uid_t, uid_t)   1,1,-1
+int     __setreuid:setreuid(uid_t, uid_t)     -1,-1,1
+int     __setresuid:setresuid32(uid_t, uid_t, uid_t)   1,1,-1
+int     __setresuid:setresuid(uid_t, uid_t, uid_t)     -1,-1,1
+int     setresgid:setresgid32(gid_t, gid_t, gid_t)   1,1,-1
+int     setresgid:setresgid(gid_t, gid_t, gid_t)     -1,-1,1
+void*   __brk:brk(void*)           1
 # see comments in arch-arm/bionic/kill.S to understand why we don't generate an ARM stub for kill/tkill
-int     kill(pid_t, int)           -1,37
-int     tkill(pid_t tid, int sig)  -1,238
-int     __ptrace:ptrace(int request, int pid, void* addr, void* data)  26
-int     __set_thread_area:set_thread_area(void*  user_desc)  -1,243
-int     __getpriority:getpriority(int, int)  96
-int     setpriority(int, int, int)   97
-int     setrlimit(int resource, const struct rlimit *rlp)  75
-int     getrlimit:ugetrlimit(int resource, struct rlimit *rlp)  191
-int     getrusage(int who, struct rusage*  r_usage)  77
-int     setgroups:setgroups32(int, const gid_t *)   206
+int     kill(pid_t, int)           -1,1,1
+int     tkill(pid_t tid, int sig)  -1,1,1
+int     tgkill(pid_t tgid, pid_t tid, int sig)  -1,1,1
+int     __ptrace:ptrace(int request, int pid, void* addr, void* data)  1
+int     __set_thread_area:set_thread_area(void*  user_desc)  -1,1,1
+int     __getpriority:getpriority(int, int)  1
+int     setpriority(int, int, int)   1
+int     setrlimit(int resource, const struct rlimit *rlp)  1
+int     getrlimit:ugetrlimit(int resource, struct rlimit *rlp)  1,1,-1
+int     getrlimit:getrlimit(int resource, struct rlimit *rlp)  -1,-1,1
+int     getrusage(int who, struct rusage*  r_usage)  1
+int     setgroups:setgroups32(int, const gid_t *)   1,1,-1
+int     setgroups:setgroups(int, const gid_t *)     -1,-1,1
 pid_t   getpgrp(void)  stub
-int     setpgid(pid_t, pid_t)  57
-pid_t   vfork(void)  190,-1,190
-int     setregid:setregid32(gid_t, gid_t)  204
-int     chroot(const char *)  61
-int     prctl(int option, unsigned int arg2, unsigned int arg3, unsigned int arg4, unsigned int arg5)  172
-int     capget(cap_user_header_t header, cap_user_data_t data) 184
-int     capset(cap_user_header_t header, const cap_user_data_t data) 185
-int     sigaltstack(const stack_t*, stack_t*) 186
-int     acct(const char*  filepath)  51
+int     setpgid(pid_t, pid_t)  1
+pid_t   vfork(void)  1,-1,-1
+int     setregid:setregid32(gid_t, gid_t)  1,1,-1
+int     setregid:setregid(gid_t, gid_t)    -1,-1,1
+int     chroot(const char *)  1
+# IMPORTANT: Even though <sys/prctl.h> declares prctl(int,...), the syscall stub must take 6 arguments
+#            to match the kernel implementation.
+int     prctl(int option, unsigned int arg2, unsigned int arg3, unsigned int arg4, unsigned int arg5) 1
+int     capget(cap_user_header_t header, cap_user_data_t data) 1
+int     capset(cap_user_header_t header, const cap_user_data_t data) 1
+int     sigaltstack(const stack_t*, stack_t*) 1
+int     acct(const char*  filepath)  1
 
 # file descriptors
-ssize_t     read (int, void*, size_t)        3
-ssize_t     write (int, const void*, size_t)       4
-ssize_t     __pread64:pread64 (int, void *, size_t, off_t, off_t) 180
-ssize_t     __pwrite64:pwrite64 (int, void *, size_t, off_t, off_t) 181
-int         __open:open (const char*, int, mode_t)  5
-int         __openat:openat (int, const char*, int, mode_t)  322,295
-int         close (int)                      6
+ssize_t     read (int, void*, size_t)        1
+ssize_t     write (int, const void*, size_t)       1
+ssize_t     pread64 (int, void *, size_t, off64_t) 1
+ssize_t     pwrite64 (int, void *, size_t, off64_t) 1
+int         __open:open (const char*, int, mode_t)  1
+int         __openat:openat (int, const char*, int, mode_t) 1
+int         close (int)                      1
 int         creat(const char*, mode_t)       stub
-off_t       lseek(int, off_t, int)           19
-int         __llseek:_llseek (int, unsigned long, unsigned long, loff_t*, int)  140
-pid_t       getpid ()    20
+off_t       lseek(int, off_t, int)           1
+int         __llseek:_llseek (int, unsigned long, unsigned long, loff_t*, int)  1
+pid_t       getpid ()    1
 void *      mmap(void *, size_t, int, int, int, long)  stub
-void *      __mmap2:mmap2(void*, size_t, int, int, int, long)   192
-int         munmap(void *, size_t)  91
-void *      mremap(void *, size_t, size_t, unsigned long)  163
-int         msync(const void *, size_t, int)    144
-int         mprotect(const void *, size_t, int)  125
-int         madvise(const void *, size_t, int)  220,219
-int         mlock(const void *addr, size_t len)    150
-int         munlock(const void *addr, size_t len)   151
-int         mincore(void*  start, size_t  length, unsigned char*  vec)   219,218
-int         __ioctl:ioctl(int, int, void *)  54
-int         readv(int, const struct iovec *, int)   145
-int         writev(int, const struct iovec *, int)  146
-int         __fcntl:fcntl(int, int, void*)  55
-int         flock(int, int)   143
-int         fchmod(int, mode_t)  94
-int         dup(int)  41
-int         pipe(int *)  42,42,-1
-int         pipe2(int *, int) 359,331
-int         dup2(int, int)   63
-int         select:_newselect(int, struct fd_set *, struct fd_set *, struct fd_set *, struct timeval *)  142
-int         ftruncate(int, off_t)  93
-int         getdents:getdents64(unsigned int, struct dirent *, unsigned int)   217,220
-int         fsync(int)  118
-int         fdatasync(int) 148
-int         fchown:fchown32(int, uid_t, gid_t)  207
-void        sync(void)  36
-int         __fcntl64:fcntl64(int, int, void *)  221
-int         __fstatfs64:fstatfs64(int, size_t, struct statfs *)  267,269
-ssize_t     sendfile(int out_fd, int in_fd, off_t *offset, size_t count)  187
-int         fstatat:fstatat64(int dirfd, const char *path, struct stat *buf, int flags)   327,300
-int         mkdirat(int dirfd, const char *pathname, mode_t mode)  323,296
-int         fchownat(int dirfd, const char *path, uid_t owner, gid_t group, int flags)  325,298
-int         fchmodat(int dirfd, const char *path, mode_t mode, int flags)  333,306
-int         renameat(int olddirfd, const char *oldpath, int newdirfd, const char *newpath)  329,302
+void *      __mmap2:mmap2(void*, size_t, int, int, int, long)   1
+int         munmap(void *, size_t)  1
+void *      mremap(void *, size_t, size_t, unsigned long)  1
+int         msync(const void *, size_t, int)    1
+int         mprotect(const void *, size_t, int)  1
+int         madvise(const void *, size_t, int)  1
+int         mlock(const void *addr, size_t len)    1
+int         munlock(const void *addr, size_t len)   1
+int         mlockall(int flags)   1
+int         munlockall()   1
+int         mincore(void*  start, size_t  length, unsigned char*  vec)   1
+int         __ioctl:ioctl(int, int, void *)  1
+int         readv(int, const struct iovec *, int)   1
+int         writev(int, const struct iovec *, int)  1
+int         __fcntl:fcntl(int, int, void*)  1
+int         flock(int, int)   1
+int         fchmod(int, mode_t)  1
+int         dup(int)  1
+int         pipe(int *)  1,1,-1
+int         pipe2(int *, int) 1
+int         dup2(int, int)   1
+int         select:_newselect(int, struct fd_set *, struct fd_set *, struct fd_set *, struct timeval *)  1
+int         ftruncate(int, off_t)  1
+int         ftruncate64(int, off64_t) 1
+int         getdents:getdents64(unsigned int, struct dirent *, unsigned int)   1
+int         fsync(int)  1
+int         fdatasync(int) 1
+int         fchown:fchown32(int, uid_t, gid_t)  1,1,-1
+int         fchown:fchown(int, uid_t, gid_t)    -1,-1,1
+void        sync(void)  1
+int         __fcntl64:fcntl64(int, int, void *)  1
+int         __fstatfs64:fstatfs64(int, size_t, struct statfs *)  1
+ssize_t     sendfile(int out_fd, int in_fd, off_t *offset, size_t count)  1
+int         fstatat:fstatat64(int dirfd, const char *path, struct stat *buf, int flags)   1
+int         mkdirat(int dirfd, const char *pathname, mode_t mode)  1
+int         fchownat(int dirfd, const char *path, uid_t owner, gid_t group, int flags)  1
+int         fchmodat(int dirfd, const char *path, mode_t mode, int flags)  1
+int         renameat(int olddirfd, const char *oldpath, int newdirfd, const char *newpath)  1
+int         fsetxattr(int, const char *, const void *, size_t, int) 1
+ssize_t     fgetxattr(int, const char *, void *, size_t) 1
+ssize_t     flistxattr(int, char *, size_t) 1
+int         fremovexattr(int, const char *) 1
 
 # file system
-int     link (const char*, const char*)  9
-int     unlink (const char*)             10
-int     unlinkat (int, const char *, int)   328,301
-int     chdir (const char*)              12
-int     mknod (const char*, mode_t, dev_t)  14
-int     chmod (const char*,mode_t)          15
-int     chown:chown32(const char *, uid_t, gid_t)  212
-int     lchown:lchown32 (const char*, uid_t, gid_t)  198
-int     mount (const char*, const char*, const char*, unsigned long, const void*)  21
+int     link (const char*, const char*)  1
+int     unlink (const char*)             1
+int     unlinkat (int, const char *, int)   1
+int     chdir (const char*)              1
+int     mknod (const char*, mode_t, dev_t)  1
+int     chmod (const char*,mode_t)          1
+int     chown:chown32(const char *, uid_t, gid_t)  1,1,-1
+int     chown:chown(const char *, uid_t, gid_t)    -1,-1,1
+int     lchown:lchown32 (const char*, uid_t, gid_t)  1,1,-1
+int     lchown:lchown (const char*, uid_t, gid_t)  -1,-1,1
+int     mount (const char*, const char*, const char*, unsigned long, const void*)  1
 int     umount(const char*)  stub
-int     umount2 (const char*, int)  52
-int     fstat:fstat64(int, struct stat*)    197
-int     stat:stat64(const char *, struct stat *)  195
-int     lstat:lstat64(const char *, struct stat *)  196
-int     mkdir(const char *, mode_t) 39
-int     readlink(const char *, char *, size_t)  85
-int     rmdir(const char *)  40
-int     rename(const char *, const char *)  38
-int     __getcwd:getcwd(char * buf, size_t size)  183
-int     access(const char *, int)  33
-int     symlink(const char *, const char *)  83
-int     fchdir(int)    133
-int     truncate(const char*, off_t)    92
-int     __statfs64:statfs64(const char *, size_t, struct statfs *)  266,268
+int     umount2 (const char*, int)  1
+int     fstat:fstat64(int, struct stat*)    1
+int     stat:stat64(const char *, struct stat *)  1
+int     lstat:lstat64(const char *, struct stat *)  1
+int     mkdir(const char *, mode_t) 1
+int     readlink(const char *, char *, size_t)  1
+int     rmdir(const char *)  1
+int     rename(const char *, const char *)  1
+int     __getcwd:getcwd(char * buf, size_t size)  1
+int     access(const char *, int)  1
+int     faccessat(int, const char *, int, int)  1
+int     symlink(const char *, const char *)  1
+int     fchdir(int)    1
+int     truncate(const char*, off_t)    1
+int     setxattr(const char *, const char *, const void *, size_t, int) 1
+int     lsetxattr(const char *, const char *, const void *, size_t, int) 1
+ssize_t getxattr(const char *, const char *, void *, size_t) 1
+ssize_t lgetxattr(const char *, const char *, void *, size_t) 1
+ssize_t listxattr(const char *, char *, size_t) 1
+ssize_t llistxattr(const char *, char *, size_t) 1
+int     removexattr(const char *, const char *) 1
+int     lremovexattr(const char *, const char *) 1
+int     __statfs64:statfs64(const char *, size_t, struct statfs *)  1
+long    unshare(unsigned long)  1
+
 # time
-int           pause ()                       29
-int           gettimeofday(struct timeval*, struct timezone*)       78
-int           settimeofday(const struct timeval*, const struct timezone*)   79
-clock_t       times(struct tms *)       43
-int           nanosleep(const struct timespec *, struct timespec *)   162
-int           clock_gettime(clockid_t clk_id, struct timespec *tp)    263,265
-int           clock_settime(clockid_t clk_id, const struct timespec *tp)  262,264
-int           clock_getres(clockid_t clk_id, struct timespec *res)   264,266
-int           clock_nanosleep(const struct timespec *req, struct timespec *rem)  265,267
-int           getitimer(int, const struct itimerval *)   105
-int           setitimer(int, const struct itimerval *, struct itimerval *)  104
-int           __timer_create:timer_create(clockid_t clockid, struct sigevent *evp, timer_t *timerid)    257,259
-int           __timer_settime:timer_settime(timer_t, int, const struct itimerspec*, struct itimerspec*) 258,260
-int           __timer_gettime:timer_gettime(timer_t, struct itimerspec*)                                259,261
-int           __timer_getoverrun:timer_getoverrun(timer_t)                                              260,262
-int           __timer_delete:timer_delete(timer_t)                                                      261,263
-int           utimes(const char*, const struct timeval tvp[2])                          269, 271
+int           pause ()                       1
+int           gettimeofday(struct timeval*, struct timezone*)       1
+int           settimeofday(const struct timeval*, const struct timezone*)   1
+clock_t       times(struct tms *)       1
+int           nanosleep(const struct timespec *, struct timespec *)   1
+int           clock_gettime(clockid_t clk_id, struct timespec *tp)    1
+int           clock_settime(clockid_t clk_id, const struct timespec *tp)  1
+int           clock_getres(clockid_t clk_id, struct timespec *res)   1
+int           clock_nanosleep(clockid_t clock_id, int flags, const struct timespec *req, struct timespec *rem)  1
+int           getitimer(int, const struct itimerval *)   1
+int           setitimer(int, const struct itimerval *, struct itimerval *)  1
+int           __timer_create:timer_create(clockid_t clockid, struct sigevent *evp, timer_t *timerid)    1
+int           __timer_settime:timer_settime(timer_t, int, const struct itimerspec*, struct itimerspec*) 1
+int           __timer_gettime:timer_gettime(timer_t, struct itimerspec*)                                1
+int           __timer_getoverrun:timer_getoverrun(timer_t)                                              1
+int           __timer_delete:timer_delete(timer_t)                                                      1
+int           utimes(const char*, const struct timeval tvp[2])                          1
+int           utimensat(int, const char *, const struct timespec times[2], int)         1
 
 # signals
-int     sigaction(int, const struct sigaction *, struct sigaction *)  67
-int     sigprocmask(int, const sigset_t *, sigset_t *)  126
-int     __sigsuspend:sigsuspend(int unused1, int unused2, unsigned mask)  72
-int     __rt_sigaction:rt_sigaction (int sig, const struct sigaction *act, struct sigaction *oact, size_t sigsetsize)  174
-int     __rt_sigprocmask:rt_sigprocmask (int  how, const sigset_t *set, sigset_t *oset, size_t sigsetsize)  175
-int     __rt_sigtimedwait:rt_sigtimedwait(const sigset_t *set, struct siginfo_t  *info, struct timespec_t  *timeout, size_t  sigset_size)  177
-int     sigpending(sigset_t *)  73
+int     sigaction(int, const struct sigaction *, struct sigaction *)  1
+int     sigprocmask(int, const sigset_t *, sigset_t *)  1
+int     __sigsuspend:sigsuspend(int unused1, int unused2, unsigned mask)  1,1,-1
+int     __sigsuspend:sigsuspend(const sigset_t *mask)  -1,-1,1
+int     __rt_sigaction:rt_sigaction (int sig, const struct sigaction *act, struct sigaction *oact, size_t sigsetsize)  1
+int     __rt_sigprocmask:rt_sigprocmask (int  how, const sigset_t *set, sigset_t *oset, size_t sigsetsize)  1
+int     __rt_sigtimedwait:rt_sigtimedwait(const sigset_t *set, struct siginfo_t  *info, struct timespec_t  *timeout, size_t  sigset_size)  1
+int     sigpending(sigset_t *)  1
+int     signalfd4(int fd, const sigset_t *mask, size_t sizemask, int flags)  1
 
 # sockets
-int           socket(int, int, int)              281,-1
-int           socketpair(int, int, int, int*)    288,-1
-int           bind(int, struct sockaddr *, int)  282,-1
-int           connect(int, struct sockaddr *, socklen_t)   283,-1
-int           listen(int, int)                   284,-1
-int           accept(int, struct sockaddr *, socklen_t *)  285,-1
-int           getsockname(int, struct sockaddr *, socklen_t *)  286,-1
-int           getpeername(int, struct sockaddr *, socklen_t *)  287,-1
-int           sendto(int, const void *, size_t, int, const struct sockaddr *, socklen_t)  290,-1
-int           recvfrom(int, void *, size_t, unsigned int, struct sockaddr *, socklen_t *)  292,-1
-int           shutdown(int, int)  293,-1
-int           setsockopt(int, int, int, const void *, socklen_t)  294,-1
-int           getsockopt(int, int, int, void *, socklen_t *)    295,-1
-int           sendmsg(int, const struct msghdr *, unsigned int)  296,-1
-int           recvmsg(int, struct msghdr *, unsigned int)   297,-1
+int           socket(int, int, int)              1,-1,1
+int           socketpair(int, int, int, int*)    1,-1,1
+int           bind(int, struct sockaddr *, int)  1,-1,1
+int           connect(int, struct sockaddr *, socklen_t)   1,-1,1
+int           listen(int, int)                   1,-1,1
+int           accept(int, struct sockaddr *, socklen_t *)  1,-1,1
+int           getsockname(int, struct sockaddr *, socklen_t *)  1,-1,1
+int           getpeername(int, struct sockaddr *, socklen_t *)  1,-1,1
+int           sendto(int, const void *, size_t, int, const struct sockaddr *, socklen_t)  1,-1,1
+int           recvfrom(int, void *, size_t, unsigned int, struct sockaddr *, socklen_t *)  1,-1,1
+int           shutdown(int, int)  1,-1,1
+int           setsockopt(int, int, int, const void *, socklen_t)  1,-1,1
+int           getsockopt(int, int, int, void *, socklen_t *)    1,-1,1
+int           sendmsg(int, const struct msghdr *, unsigned int)  1,-1,1
+int           recvmsg(int, struct msghdr *, unsigned int)   1,-1,1
 
 # sockets for x86. These are done as an "indexed" call to socketcall syscall.
-int           socket:socketcall:1 (int, int, int) -1,102,-1
-int           bind:socketcall:2 (int, struct sockaddr *, int)  -1,102,-1
-int           connect:socketcall:3(int, struct sockaddr *, socklen_t)   -1,102,-1
-int           listen:socketcall:4(int, int)                   -1,102,-1
-int           accept:socketcall:5(int, struct sockaddr *, socklen_t *)  -1,102,-1
-int           getsockname:socketcall:6(int, struct sockaddr *, socklen_t *)  -1,102,-1
-int           getpeername:socketcall:7(int, struct sockaddr *, socklen_t *)  -1,102,-1
-int           socketpair:socketcall:8(int, int, int, int*)    -1,102,-1
-int           sendto:socketcall:11(int, const void *, size_t, int, const struct sockaddr *, socklen_t)  -1,102,-1
-int           recvfrom:socketcall:12(int, void *, size_t, unsigned int, struct sockaddr *, socklen_t *)  -1,102,-1
-int           shutdown:socketcall:13(int, int)  -1,102,-1
-int           setsockopt:socketcall:14(int, int, int, const void *, socklen_t)  -1,102,-1
-int           getsockopt:socketcall:15(int, int, int, void *, socklen_t *)    -1,102,-1
-int           sendmsg:socketcall:16(int, const struct msghdr *, unsigned int)  -1,102,-1
-int           recvmsg:socketcall:17(int, struct msghdr *, unsigned int)   -1,102,-1
-
-# sockets for sh.
-int           __socketcall:__socketcall(int, unsigned long*) -1,-1,102
+int           socket:socketcall:1 (int, int, int) -1,1,-1
+int           bind:socketcall:2 (int, struct sockaddr *, int)  -1,1,-1
+int           connect:socketcall:3(int, struct sockaddr *, socklen_t)   -1,1,-1
+int           listen:socketcall:4(int, int)                   -1,1,-1
+int           accept:socketcall:5(int, struct sockaddr *, socklen_t *)  -1,1,-1
+int           getsockname:socketcall:6(int, struct sockaddr *, socklen_t *)  -1,1,-1
+int           getpeername:socketcall:7(int, struct sockaddr *, socklen_t *)  -1,1,-1
+int           socketpair:socketcall:8(int, int, int, int*)    -1,1,-1
+int           sendto:socketcall:11(int, const void *, size_t, int, const struct sockaddr *, socklen_t)  -1,1,-1
+int           recvfrom:socketcall:12(int, void *, size_t, unsigned int, struct sockaddr *, socklen_t *)  -1,1,-1
+int           shutdown:socketcall:13(int, int)  -1,1,-1
+int           setsockopt:socketcall:14(int, int, int, const void *, socklen_t)  -1,1,-1
+int           getsockopt:socketcall:15(int, int, int, void *, socklen_t *)    -1,1,-1
+int           sendmsg:socketcall:16(int, const struct msghdr *, unsigned int)  -1,1,-1
+int           recvmsg:socketcall:17(int, struct msghdr *, unsigned int)   -1,1,-1
 
 # scheduler & real-time
-int sched_setscheduler(pid_t pid, int policy, const struct sched_param *param)  156
-int sched_getscheduler(pid_t pid)  157
-int sched_yield(void)  158
-int sched_setparam(pid_t pid, const struct sched_param *param)  154
-int sched_getparam(pid_t pid, struct sched_param *param)  155
-int sched_get_priority_max(int policy)  159
-int sched_get_priority_min(int policy)  160
-int sched_rr_get_interval(pid_t pid, struct timespec *interval)  161
+int sched_setscheduler(pid_t pid, int policy, const struct sched_param *param)  1
+int sched_getscheduler(pid_t pid)  1
+int sched_yield(void)  1
+int sched_setparam(pid_t pid, const struct sched_param *param)  1
+int sched_getparam(pid_t pid, struct sched_param *param)  1
+int sched_get_priority_max(int policy)  1
+int sched_get_priority_min(int policy)  1
+int sched_rr_get_interval(pid_t pid, struct timespec *interval)  1
+int sched_setaffinity(pid_t pid, size_t setsize, const cpu_set_t* set) 1
+int __sched_getaffinity:sched_getaffinity(pid_t pid, size_t setsize, cpu_set_t* set)  1
+int __getcpu:getcpu(unsigned *cpu, unsigned *node, void *unused) 1
 
 # io priorities
-int ioprio_set(int which, int who, int ioprio) 314,289,288
-int ioprio_get(int which, int who) 315,290,289
+int ioprio_set(int which, int who, int ioprio) 1
+int ioprio_get(int which, int who) 1
 
 # other
-int     uname(struct utsname *)  122
-pid_t   __wait4:wait4(pid_t pid, int *status, int options, struct rusage *rusage)   114
-mode_t  umask(mode_t)  60
-int      __reboot:reboot(int, int, int, void *)  88
-int     __syslog:syslog(int, char *, int)  103
-int     init_module(void *, unsigned long, const char *)  128
-int     delete_module(const char*, unsigned int)   129
-int     klogctl:syslog(int, char *, int)   103
-int     sysinfo(struct sysinfo *)  116
+int     uname(struct utsname *)  1
+mode_t  umask(mode_t)  1
+int      __reboot:reboot(int, int, int, void *)  1
+int     __syslog:syslog(int, char *, int)  1
+int     init_module(void *, unsigned long, const char *)  1
+int     delete_module(const char*, unsigned int)   1
+int     klogctl:syslog(int, char *, int)   1
+int     sysinfo(struct sysinfo *)  1
+int     personality(unsigned long)  1
+long    perf_event_open(struct perf_event_attr *attr_uptr, pid_t pid, int cpu, int group_fd, unsigned long flags) 1
 
 # futex
-int	futex(void *, int, int, void *, void *, int) 240
+int	futex(void *, int, int, void *, void *, int) 1
 
 # epoll
-int     epoll_create(int size)     250,254
-int     epoll_ctl(int epfd, int op, int fd, struct epoll_event *event)    251,255
-int     epoll_wait(int epfd, struct epoll_event *events, int max, int timeout)   252,256
+int     epoll_create(int size)     1
+int     epoll_ctl(int epfd, int op, int fd, struct epoll_event *event)    1
+int     epoll_wait(int epfd, struct epoll_event *events, int max, int timeout)   1
 
-int     inotify_init(void)      316,291,290
-int     inotify_add_watch(int, const char *, unsigned int)  317,292,291
-int     inotify_rm_watch(int, unsigned int)  318,293,292
+int     inotify_init(void)      1
+int     inotify_add_watch(int, const char *, unsigned int)  1
+int     inotify_rm_watch(int, unsigned int)  1
 
-int     poll(struct pollfd *, unsigned int, long)  168
+int     poll(struct pollfd *, unsigned int, long)  1
 
-int     eventfd:eventfd2(unsigned int, int)  356,328
+int     eventfd:eventfd2(unsigned int, int)  1
 
 # ARM-specific ARM_NR_BASE == 0x0f0000 == 983040
-int     __set_tls:ARM_set_tls(void*)                                 983045,-1
-int     cacheflush:ARM_cacheflush(long start, long end, long flags)  983042,-1
+int     __set_tls:__ARM_NR_set_tls(void*)                                 1,-1,-1
+int     cacheflush:__ARM_NR_cacheflush(long start, long end, long flags)  1,-1,-1
+
+# MIPS-specific
+int     _flush_cache:cacheflush(char *addr, const int nbytes, const int op) -1,-1,1
+int     syscall(int number,...) -1,-1,1

libc/arch-arm/arm.mk

@@ -0,0 +1,35 @@
+_LIBC_ARCH_COMMON_SRC_FILES := \
+    arch-arm/bionic/abort_arm.S \
+    arch-arm/bionic/atomics_arm.c \
+    arch-arm/bionic/clone.S \
+    arch-arm/bionic/eabi.c \
+    arch-arm/bionic/_exit_with_stack_teardown.S \
+    arch-arm/bionic/ffs.S \
+    arch-arm/bionic/futex_arm.S \
+    arch-arm/bionic/__get_sp.S \
+    arch-arm/bionic/kill.S \
+    arch-arm/bionic/libgcc_compat.c \
+    arch-arm/bionic/memcmp16.S \
+    arch-arm/bionic/memcmp.S \
+    arch-arm/bionic/_setjmp.S \
+    arch-arm/bionic/setjmp.S \
+    arch-arm/bionic/sigsetjmp.S \
+    arch-arm/bionic/strcpy.S \
+    arch-arm/bionic/strlen.c.arm \
+    arch-arm/bionic/syscall.S \
+    arch-arm/bionic/tgkill.S \
+    arch-arm/bionic/tkill.S \
+
+# These are used by the static and dynamic versions of the libc
+# respectively.
+_LIBC_ARCH_STATIC_SRC_FILES := \
+    arch-arm/bionic/exidx_static.c
+
+_LIBC_ARCH_DYNAMIC_SRC_FILES := \
+    arch-arm/bionic/exidx_dynamic.c
+
+ifeq ($(strip $(wildcard bionic/libc/arch-arm/$(TARGET_CPU_VARIANT)/$(TARGET_CPU_VARIANT).mk)),)
+$(error "TARGET_CPU_VARIANT not set or set to an unknown value. Possible values are cortex-a9, cortex-a15, krait. Use generic for devices that do not have a CPU similar to any of the supported cpu variants.")
+endif
+
+include bionic/libc/arch-arm/$(TARGET_CPU_VARIANT)/$(TARGET_CPU_VARIANT).mk

libc/arch-arm/bionic/__get_sp.S

@@ -25,10 +25,10 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
-.global __get_sp
-.type __get_sp, %function
 
-__get_sp:
-	mov r0, sp
-	bx lr
+#include <machine/asm.h>
 
+ENTRY(__get_sp)
+  mov r0, sp
+  bx lr
+END(__get_sp)

libc/arch-arm/bionic/_exit_with_stack_teardown.S

@@ -25,31 +25,20 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
+
+#include <machine/asm.h>
 #include <asm/unistd.h>
 
-.text
-.type _exit_with_stack_teardown, #function
-.globl _exit_with_stack_teardown
-.align 4
-
-@ void _exit_with_stack_teardown(void * stackBase, int stackSize, int retCode)
-
-_exit_with_stack_teardown:
-
-#if __ARM_EABI__
+// void _exit_with_stack_teardown(void* stackBase, int stackSize, int retCode)
+ENTRY(_exit_with_stack_teardown)
     mov     lr, r2
     ldr     r7, =__NR_munmap
-    swi     #0              @ the stack is destroyed by this call
+    swi     #0              // the stack is destroyed by this call
     mov     r0, lr
     ldr     r7, =__NR_exit
     swi     #0
-#else
-    mov     lr, r2
-    swi     # __NR_munmap   @ the stack is destroyed by this call
-    mov     r0, lr
-    swi     # __NR_exit
-#endif
 
-    @ exit() should never return, cause a crash if it does
-    mov		r0, #0
-    ldr		r0, [r0]
+    // exit() should never return, cause a crash if it does
+    mov     r0, #0
+    ldr     r0, [r0]
+END(_exit_with_stack_teardown)

libc/arch-arm/bionic/_setjmp.S

@@ -70,6 +70,7 @@ ENTRY(_setjmp)
 
         mov	r0, #0x00000000
         bx      lr
+END(_setjmp)
 
 .L_setjmp_magic:
 	.word	_JB_MAGIC__SETJMP
@@ -109,3 +110,4 @@ botch:
 	bl	PIC_SYM(_C_LABEL(longjmperror), PLT)
 	bl	PIC_SYM(_C_LABEL(abort), PLT)
 	b	. - 8		/* Cannot get here */
+END(_longjmp)

libc/arch-arm/bionic/abort_arm.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011 The Android Open Source Project
+ * Copyright (C) 2012 The Android Open Source Project
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,24 +25,18 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
+
+#include <machine/asm.h>
+
 /*
- * Contributed by: Intel Corporation
+ * Coding the abort function in assembly so that registers are guaranteed to
+ * be preserved properly regardless of GCC's assumption on the "noreturn"
+ * attribute. When the registers are not properly preserved we won't be able
+ * to unwind the stack all the way to the bottom to fully reveal the call
+ * sequence when the crash happens.
  */
-
-	.text
-	.p2align 4,,15
-	.globl	__stack_chk_fail_local
-	.hidden	__stack_chk_fail_local
-	.type	__stack_chk_fail_local, @function
-
-__stack_chk_fail_local:
-#ifdef __PIC__
-	pushl	%ebx
-	call	__x86.get_pc_thunk.bx
-	addl	$_GLOBAL_OFFSET_TABLE_, %ebx
-	call	__stack_chk_fail@PLT
-#else /* PIC */
-	jmp   __stack_chk_fail
-#endif /* not PIC */
-
-	.size	__stack_chk_fail_local, .-__stack_chk_fail_local
+ENTRY(abort)
+    .save   {r3, r14}
+    stmfd   sp!, {r3, r14}
+    blx     PIC_SYM(_C_LABEL(__libc_android_abort), PLT)
+END(abort)

libc/arch-arm/bionic/atexit.S

@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2011 The Android Open Source Project
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#ifndef CRT_LEGACY_WORKAROUND
-	.arch armv5te
-	.fpu softvfp
-	.eabi_attribute 20, 1
-	.eabi_attribute 21, 1
-	.eabi_attribute 23, 3
-	.eabi_attribute 24, 1
-	.eabi_attribute 25, 1
-	.eabi_attribute 26, 2
-	.eabi_attribute 30, 4
-	.eabi_attribute 18, 4
-	.code	16
-	.section	.text.atexit,"ax",%progbits
-	.align	2
-	.global	atexit
-	.hidden	atexit
-	.code	16
-	.thumb_func
-	.type	atexit, %function
-atexit:
-	.fnstart
-.LFB0:
-	.save	{r4, lr}
-	push	{r4, lr}
-.LCFI0:
-	ldr	r3, .L3
-	mov	r1, #0
-	@ sp needed for prologue
-.LPIC0:
-	add	r3, pc
-	ldr	r2, [r3]
-	bl	__cxa_atexit
-	pop	{r4, pc}
-.L4:
-	.align	2
-.L3:
-	.word	__dso_handle-(.LPIC0+4)
-.LFE0:
-	.fnend
-	.size	atexit, .-atexit
-#endif

libc/arch-arm/bionic/atexit.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2008 The Android Open Source Project
+ * Copyright (C) 2012 The Android Open Source Project
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,11 +25,11 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
-#include <sys/resource.h>
 
-int nice(int increment)
+extern void *__dso_handle;
+
+__attribute__ ((visibility ("hidden")))
+int atexit(void (*func)(void))
 {
-    int  priority = getpriority(PRIO_PROCESS, 0);
-
-    return setpriority( PRIO_PROCESS, 0, priority+increment);
+  return (__cxa_atexit((void (*)(void *))func, (void *)0, &__dso_handle));
 }

libc/arch-arm/bionic/atexit_legacy.c

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2012 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <private/libc_logging.h>
+#include <stdio.h>
+
+/*
+ * This source file should only be included by libc.so, its purpose is
+ * to support legacy ARM binaries by exporting a publicly visible
+ * implementation of atexit().
+ */
+
+extern int __cxa_atexit(void (*func)(void *), void *arg, void *dso);
+
+/*
+ * Register a function to be performed at exit.
+ */
+int
+atexit(void (*func)(void))
+{
+    /*
+     * Exit functions queued by this version of atexit will not be called
+     * on dlclose(), and when they are called (at program exit), the
+     * calling library may have been dlclose()'d, causing the program to
+     * crash.
+     */
+    static char const warning[] = "WARNING: generic atexit() called from legacy shared library\n";
+
+    __libc_format_log(ANDROID_LOG_WARN, "libc", warning);
+    fprintf(stderr, warning);
+
+    return (__cxa_atexit((void (*)(void *))func, NULL, NULL));
+}

libc/arch-arm/bionic/atomics_arm.S

@@ -1,251 +0,0 @@
-/*
- * Copyright (C) 2008 The Android Open Source Project
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
- * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-#include <sys/linux-syscalls.h>
-#include <machine/cpu-features.h>
-
-.global __atomic_cmpxchg
-.type __atomic_cmpxchg, %function
-.global __atomic_swap
-.type __atomic_swap, %function
-.global __atomic_dec
-.type __atomic_dec, %function
-.global __atomic_inc
-.type __atomic_inc, %function
-
-#define FUTEX_WAIT 0
-#define FUTEX_WAKE 1
-
-#if defined(__ARM_HAVE_LDREX_STREX)
-/*
- * ===========================================================================
- *      ARMv6+ implementation
- * ===========================================================================
- */
-
-/* r0(addr) -> r0(old) */
-__atomic_dec:
-    .fnstart
-    mov     r1, r0                      @ copy addr so we don't clobber it
-1:  ldrex   r0, [r1]                    @ load current value into r0
-    sub     r2, r0, #1                  @ generate new value into r2
-    strex   r3, r2, [r1]                @ try to store new value; result in r3
-    cmp     r3, #0                      @ success?
-    bxeq    lr                          @ yes, return
-    b       1b                          @ no, retry
-    .fnend
-
-/* r0(addr) -> r0(old) */
-__atomic_inc:
-    .fnstart
-    mov     r1, r0
-1:  ldrex   r0, [r1]
-    add     r2, r0, #1
-    strex   r3, r2, [r1]
-    cmp     r3, #0
-    bxeq    lr
-    b       1b
-    .fnend
-
-/* r0(old) r1(new) r2(addr) -> r0(zero_if_succeeded) */
-__atomic_cmpxchg:
-    .fnstart
-1:  mov     ip, #2                      @ ip=2 means "new != old"
-    ldrex   r3, [r2]                    @ load current value into r3
-    teq     r0, r3                      @ new == old?
-    strexeq ip, r1, [r2]                @ yes, try store, set ip to 0 or 1
-    teq     ip, #1                      @ strex failure?
-    beq     1b                          @ yes, retry
-    mov     r0, ip                      @ return 0 on success, 2 on failure
-    bx      lr
-    .fnend
-
-/* r0(new) r1(addr) -> r0(old) */
-__atomic_swap:
-    .fnstart
-1:  ldrex   r2, [r1]
-    strex   r3, r0, [r1]
-    teq     r3, #0
-    bne     1b
-    mov     r0, r2
-    bx      lr
-    .fnend
-
-#else /*not defined __ARM_HAVE_LDREX_STREX*/
-/*
- * ===========================================================================
- *      Pre-ARMv6 implementation
- * ===========================================================================
- */
-
-    /* int __kernel_cmpxchg(int oldval, int newval, int* ptr) */
-    .equ    kernel_cmpxchg, 0xFFFF0FC0
-    .equ    kernel_atomic_base, 0xFFFF0FFF
-
-/* r0(addr) -> r0(old) */
-__atomic_dec:
-    .fnstart
-    .save {r4, lr}
-    stmdb   sp!, {r4, lr}
-    mov     r2, r0
-1: @ atomic_dec
-    ldr     r0, [r2]
-    mov     r3, #kernel_atomic_base
-    add     lr, pc, #4
-    sub     r1, r0, #1
-    add     pc, r3, #(kernel_cmpxchg - kernel_atomic_base)
-    bcc     1b
-    add     r0, r1, #1
-    ldmia   sp!, {r4, lr}
-    bx      lr
-    .fnend
-
-/* r0(addr) -> r0(old) */
-__atomic_inc:
-    .fnstart
-    .save {r4, lr}
-    stmdb   sp!, {r4, lr}
-    mov     r2, r0
-1: @ atomic_inc
-    ldr     r0, [r2]
-    mov     r3, #kernel_atomic_base
-    add     lr, pc, #4
-    add     r1, r0, #1
-    add     pc, r3, #(kernel_cmpxchg - kernel_atomic_base)
-    bcc     1b
-    sub     r0, r1, #1
-    ldmia   sp!, {r4, lr}
-    bx      lr
-    .fnend
-
-/* r0(old) r1(new) r2(addr) -> r0(zero_if_succeeded) */
-__atomic_cmpxchg:
-    .fnstart
-    .save {r4, lr}
-    stmdb   sp!, {r4, lr}
-    mov     r4, r0          /* r4 = save oldvalue */
-1: @ atomic_cmpxchg
-    mov     r3, #kernel_atomic_base
-    add     lr, pc, #4
-    mov     r0, r4          /* r0 = oldvalue */
-    add     pc, r3, #(kernel_cmpxchg - kernel_atomic_base)
-    bcs     2f              /* swap was made. we're good, return. */
-    ldr     r3, [r2]        /* swap not made, see if it's because *ptr!=oldvalue */
-    cmp     r3, r4
-    beq     1b
-2: @ atomic_cmpxchg
-    ldmia   sp!, {r4, lr}
-    bx      lr
-    .fnend
-
-/* r0(new) r1(addr) -> r0(old) */
-__atomic_swap:
-    .fnstart
-    swp     r0, r0, [r1]
-    bx      lr
-    .fnend
-
-#endif /*not defined __ARM_HAVE_LDREX_STREX*/
-
-
-/* __futex_wait(*ftx, val, *timespec) */
-/* __futex_wake(*ftx, counter) */
-/* __futex_syscall3(*ftx, op, val) */
-/* __futex_syscall4(*ftx, op, val, *timespec) */
-
-.global __futex_wait
-.type __futex_wait, %function
-
-.global __futex_wake
-.type __futex_wake, %function
-
-.global __futex_syscall3
-.type __futex_syscall3, %function
-
-.global __futex_syscall4
-.type __futex_syscall4, %function
-
-#if __ARM_EABI__
-
-__futex_syscall3:
-    .fnstart
-    stmdb   sp!, {r4, r7}
-    .save   {r4, r7}
-    ldr     r7, =__NR_futex
-    swi     #0
-    ldmia   sp!, {r4, r7}
-    bx      lr
-    .fnend
-
-__futex_wait:
-    .fnstart
-    stmdb   sp!, {r4, r7}
-    .save   {r4, r7}
-    mov     r3, r2
-    mov     r2, r1
-    mov     r1, #FUTEX_WAIT
-    ldr     r7, =__NR_futex
-    swi     #0
-    ldmia   sp!, {r4, r7}
-    bx      lr
-    .fnend
-
-__futex_wake:
-    .fnstart
-    .save   {r4, r7}
-    stmdb   sp!, {r4, r7}
-    mov     r2, r1
-    mov     r1, #FUTEX_WAKE
-    ldr     r7, =__NR_futex
-    swi     #0
-    ldmia   sp!, {r4, r7}
-    bx      lr
-    .fnend
-
-#else
-
-__futex_syscall3:
-    swi     #__NR_futex
-    bx      lr
-
-__futex_wait:
-    mov     r3, r2
-    mov     r2, r1
-    mov     r1, #FUTEX_WAIT
-    swi     #__NR_futex
-    bx      lr
-
-__futex_wake:
-    mov     r2, r1
-    mov     r1, #FUTEX_WAKE
-    swi     #__NR_futex
-    bx      lr
-
-#endif
-
-__futex_syscall4:
-    b __futex_syscall3

libc/arch-arm/bionic/atomics_arm.c

@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2011 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+
+/* The purpose of this file is to export a small set of atomic-related
+ * functions from the C library, to ensure binary ABI compatibility for
+ * the NDK.
+ *
+ * These functions were initially exposed by the NDK through <sys/atomics.h>,
+ * which was unfortunate because their implementation didn't provide any
+ * memory barriers at all.
+ *
+ * This wasn't a problem for the platform code that used them, because it
+ * used explicit barrier instructions around them. On the other hand, it means
+ * that any NDK-generated machine code that linked against them would not
+ * perform correctly when running on multi-core devices.
+ *
+ * To fix this, the platform code was first modified to not use any of these
+ * functions (everything is now inlined through assembly statements, see
+ * libc/private/bionic_arm_inline.h and the headers it includes.
+ *
+ * The functions here are thus only for the benefit of NDK applications,
+ * and now includes full memory barriers to prevent any random memory ordering
+ * issue from cropping.
+ *
+ * Note that we also provide an updated <sys/atomics.h> header that defines
+ * always_inlined versions of the functions that use the GCC builtin
+ * intrinsics to perform the same thing.
+ *
+ * NOTE: There is no need for a similar file for non-ARM platforms.
+ */
+
+/* DO NOT INCLUDE <sys/atomics.h> HERE ! */
+
+int
+__atomic_cmpxchg(int old, int _new, volatile int *ptr)
+{
+    /* We must return 0 on success */
+    return __sync_val_compare_and_swap(ptr, old, _new) != old;
+}
+
+int
+__atomic_swap(int _new, volatile int *ptr)
+{
+    int prev;
+    do {
+        prev = *ptr;
+    } while (__sync_val_compare_and_swap(ptr, prev, _new) != prev);
+    return prev;
+}
+
+int
+__atomic_dec(volatile int *ptr)
+{
+  return __sync_fetch_and_sub (ptr, 1);
+}
+
+int
+__atomic_inc(volatile int *ptr)
+{
+  return __sync_fetch_and_add (ptr, 1);
+}

libc/arch-arm/bionic/clone.S

@@ -25,55 +25,43 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
-#include <sys/linux-syscalls.h>
 
-    .text
-    .type __pthread_clone, #function
-    .global __pthread_clone
-    .align 4
-    .fnstart
+#include <linux/err.h>
+#include <machine/asm.h>
+#include <asm/unistd.h>
 
-__pthread_clone:
-    @ insert the args onto the new stack
-    str     r0, [r1, #-4]
-    str     r3, [r1, #-8]
-
-    @ do the system call
-    @ get flags
+// int  __pthread_clone(void* (*fn)(void*), void* child_stack, int flags, void* arg);
+ENTRY(__pthread_clone)
+    # Copy the args onto the new stack.
+    stmdb   r1!, {r0, r3}
 
+    # The sys_clone system call only takes two arguments: 'flags' and 'child_stack'.
+    # 'child_stack' is already in r1, but we need to move 'flags' into position.
     mov     r0, r2
-
-    @ new sp is already in r1
-
-#if __ARM_EABI__
     stmfd   sp!, {r4, r7}
+
+    # System call.
     ldr     r7, =__NR_clone
     swi     #0
-#else
-    swi     #__NR_clone
-#endif
-
     movs    r0, r0
-#if __ARM_EABI__
-    ldmnefd sp!, {r4, r7}
-#endif
-    blt     __error
-    bxne    lr
+    beq     1f
 
+    # In parent, reload saved registers then either return or set errno.
+    ldmfd   sp!, {r4, r7}
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
 
-    @ pick the function arg and call address off the stack and jump
-    @ to the C __thread_entry function which does some setup and then
-    @ calls the thread's start function
-
-    ldr     r0, [sp, #-4]
-    ldr     r1, [sp, #-8]
-    mov     r2, sp			@ __thread_entry needs the TLS pointer
+1:  # The child.
+    # pick the function arg and call address off the stack and jump
+    # to the C __thread_entry function which does some setup and then
+    # calls the thread's start function
+    pop     {r0, r1}
+    # __thread_entry needs the TLS pointer
+    mov     r2, sp
     b       __thread_entry
-
-__error:
-    mov     r0, #-1
-    bx      lr
-    .fnend
+END(__pthread_clone)
 
 
     #
@@ -83,17 +71,13 @@ __error:
     #                          pid_t *pid, void *tls, pid_t *ctid,
     #                          int  (*fn)(void *), void* arg );
     #
-    # NOTE: This is not the same signature than the GLibc
-    #       __clone function here !! Placing 'fn' and 'arg'
+    # NOTE: This is not the same signature as the glibc
+    #       __clone function. Placing 'fn' and 'arg'
     #       at the end of the parameter list makes the
     #       implementation much simpler.
     #
-    .type __bionic_clone, #function
-    .globl __bionic_clone
-    .align 4
-    .fnstart
 
-__bionic_clone:
+ENTRY(__bionic_clone)
     mov     ip, sp
     .save   {r4, r5, r6, r7}
 
@@ -107,22 +91,21 @@ __bionic_clone:
     str     r5, [r1, #-4]
     str     r6, [r1, #-8]
 
-    # system call
+    # System call
     ldr     r7, =__NR_clone
     swi     #0
     movs    r0, r0
     beq     1f
 
-    # in parent, reload saved registers
-    # then either exit or error
-    #
+    # In the parent, reload saved registers then either return or set errno.
     ldmfd   sp!, {r4, r5, r6, r7}
-    bxne    lr
-    b       __set_syscall_errno
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
 
-1:  # in the child - pick arguments
+1:  # The child.
     ldr    r0, [sp, #-4]
     ldr    r1, [sp, #-8]
     b      __bionic_clone_entry
-
-    .fnend
+END(__bionic_clone)

libc/arch-arm/bionic/crtbegin.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "../../bionic/libc_init_common.h"
+#include <stddef.h>
+#include <stdint.h>
+
+__attribute__ ((section (".preinit_array")))
+void (*__PREINIT_ARRAY__)(void) = (void (*)(void)) -1;
+
+__attribute__ ((section (".init_array")))
+void (*__INIT_ARRAY__)(void) = (void (*)(void)) -1;
+
+__attribute__ ((section (".fini_array")))
+void (*__FINI_ARRAY__)(void) = (void (*)(void)) -1;
+
+__LIBC_HIDDEN__ void _start() {
+  structors_array_t array;
+  array.preinit_array = &__PREINIT_ARRAY__;
+  array.init_array = &__INIT_ARRAY__;
+  array.fini_array = &__FINI_ARRAY__;
+
+  void* raw_args = (void*) ((uintptr_t) __builtin_frame_address(0) + sizeof(void*));
+  __libc_init(raw_args, NULL, &main, &array);
+}
+
+#include "__dso_handle.h"
+#include "atexit.h"

libc/arch-arm/bionic/crtbegin_so.c

@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2012 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+extern void __cxa_finalize(void *);
+extern void *__dso_handle;
+
+__attribute__((visibility("hidden"),destructor))
+void __on_dlclose() {
+  __cxa_finalize(&__dso_handle);
+}
+
+/* CRT_LEGACY_WORKAROUND should only be defined when building
+ * this file as part of the platform's C library.
+ *
+ * The C library already defines a function named 'atexit()'
+ * for backwards compatibility with older NDK-generated binaries.
+ *
+ * For newer ones, 'atexit' is actually embedded in the C
+ * runtime objects that are linked into the final ELF
+ * binary (shared library or executable), and will call
+ * __cxa_atexit() in order to un-register any atexit()
+ * handler when a library is unloaded.
+ *
+ * This function must be global *and* hidden. Only the
+ * code inside the same ELF binary should be able to access it.
+ */
+
+#ifdef CRT_LEGACY_WORKAROUND
+#include "__dso_handle.h"
+#else
+#include "__dso_handle_so.h"
+#include "atexit.h"
+#endif

libc/arch-arm/bionic/crtend.S

@@ -35,6 +35,6 @@
 	.section .fini_array, "aw"
 	.long 0
 
-	.section .ctors, "aw"
-	.long 0
-
+#if defined(__linux__) && defined(__ELF__)
+	.section .note.GNU-stack,"",%progbits
+#endif

libc/arch-arm/bionic/crtend_so.S

@@ -26,13 +26,6 @@
  * SUCH DAMAGE.
  */
 
-/* This is the same than crtend.S except that a shared library
- * cannot have a .preinit_array
- */
-	
-	.section .init_array, "aw"
-	.long 0
-
-	.section .fini_array, "aw"
-	.long 0
-
+#if defined(__linux__) && defined(__ELF__)
+	.section .note.GNU-stack,"",%progbits
+#endif

libc/arch-arm/bionic/eabi.c

@@ -30,22 +30,6 @@
 
 extern int  __cxa_atexit(void (*)(void*), void*, void* );
 
-/* Temporary hack: this variable should not be part of the C library
- * itself, but placed in the .bss section of each executable or
- * shared library instead.
- *
- * We keep it here temporarily until the build system has been
- * modified properly to use crtbegin_so.S and crtend_so.S when
- * generating shared libraries.
- *
- * It must be a 'weak' symbol to avoid conflicts with the definitions
- * that have been moved to crtbegin_static.S and crtbegin_dynamic.S
- *
- * For the record, it is used for static C++ object construction
- * and destruction. See http://www.codesourcery.com/public/cxx-abi/abi.html#dso-dtor
- */
-void* __attribute__((weak)) __dso_handle;
-
 /* The "C++ ABI for ARM" document states that static C++ constructors,
  * which are called from the .init_array, should manually call
  * __aeabi_atexit() to register static destructors explicitely.

libc/arch-arm/bionic/exidx_dynamic.c

@@ -25,12 +25,8 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
-typedef long unsigned int *_Unwind_Ptr;
 
-/* Stubbed out in libdl and defined in the dynamic linker.
- * Same semantics as __gnu_Unwind_Find_exidx().
- */
-extern _Unwind_Ptr dl_unwind_find_exidx(_Unwind_Ptr pc, int *pcount);
+#include <link.h>
 
 /* For a given PC, find the .so that it belongs to.
  * Returns the base address of the .ARM.exidx section

libc/arch-arm/bionic/exidx_static.c

@@ -25,7 +25,8 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
-typedef long unsigned int *_Unwind_Ptr;
+
+#include <link.h>
 
 /* Find the .ARM.exidx section (which in the case of a static executable
  * can be identified through its start and end symbols), and return its

libc/arch-arm/bionic/ffs.S

@@ -29,54 +29,13 @@
  */
 
 #include <machine/asm.h>
-
-/*
- * ffs - find first set bit, this algorithm isolates the first set
- * bit, then multiplies the number by 0x0450fbaf which leaves the top
- * 6 bits as an index into the table.  This algorithm should be a win
- * over the checking each bit in turn as per the C compiled version.
- *
- * under ARMv5 there's an instruction called CLZ (count leading Zero's) that
- * could be used
- *
- * This is the ffs algorithm devised by d.seal and posted to comp.sys.arm on
- * 16 Feb 1994.
- */
+#include <machine/cpu-features.h>
 
 ENTRY(ffs)
 	/* Standard trick to isolate bottom bit in r0 or 0 if r0 = 0 on entry */
  	rsb     r1, r0, #0
  	ands    r0, r0, r1
-#ifndef __ARM_ARCH_5__
-	/*
-	 * now r0 has at most one set bit, call this X
-	 * if X = 0, all further instructions are skipped
-	 */
-	adrne   r2, .L_ffs_table
-	orrne   r0, r0, r0, lsl #4  /* r0 = X * 0x11 */ 
-	orrne   r0, r0, r0, lsl #6  /* r0 = X * 0x451 */
-	rsbne   r0, r0, r0, lsl #16 /* r0 = X * 0x0450fbaf */
-              
-	/* now lookup in table indexed on top 6 bits of r0 */
-	ldrneb  r0, [ r2, r0, lsr #26 ]
-
-	bx		lr
-
-.text;
-.type .L_ffs_table, _ASM_TYPE_OBJECT;
-.L_ffs_table:
-/*               0   1   2   3   4   5   6   7           */
-	.byte	 0,  1,  2, 13,  3,  7,  0, 14  /*  0- 7 */
-	.byte	 4,  0,  8,  0,  0,  0,  0, 15  /*  8-15 */
-	.byte	11,  5,  0,  0,  9,  0,  0, 26  /* 16-23 */
-	.byte	 0,  0,  0,  0,  0, 22, 28, 16  /* 24-31 */
-	.byte	32, 12,  6,  0,  0,  0,  0,  0	/* 32-39 */
-	.byte	10,  0,  0, 25,  0,  0, 21, 27  /* 40-47 */
-	.byte	31,  0,  0,  0,  0, 24,  0, 20  /* 48-55 */
-	.byte   30,  0, 23, 19, 29, 18, 17,  0  /* 56-63 */
-#else
 	clzne	r0, r0
 	rsbne	r0, r0, #32
 	bx		lr
-#endif
-
+END(ffs)

libc/arch-arm/bionic/futex_arm.S

@@ -26,36 +26,48 @@
  * SUCH DAMAGE.
  */
 
-# Implement static C++ destructors when the shared
-# library is unloaded through dlclose().
-#
-# A call to this function must be the first entry
-# in the .fini_array. See 3.3.5.3.C of C++ ABI
-# standard.
-#
-__on_dlclose:
-        adr     r0, 0f
-        ldr     r0, [r0]
-        b       __cxa_finalize
+#include <asm/unistd.h>
+#include <machine/asm.h>
 
-0:
-        .long   __dso_handle
+#define FUTEX_WAIT 0
+#define FUTEX_WAKE 1
 
-	.section .init_array, "aw"
-	.globl __INIT_ARRAY__
-__INIT_ARRAY__:
-	.long -1
+// __futex_syscall3(*ftx, op, val)
+ENTRY(__futex_syscall3)
+    stmdb   sp!, {r4, r7}
+    .save   {r4, r7}
+    ldr     r7, =__NR_futex
+    swi     #0
+    ldmia   sp!, {r4, r7}
+    bx      lr
+END(__futex_syscall3)
 
-        .section .fini_array, "aw"
-        .globl __FINI_ARRAY__
-__FINI_ARRAY__:
-        .long -1
-        .long __on_dlclose
+// __futex_syscall4(*ftx, op, val, *timespec)
+ENTRY(__futex_syscall4)
+    b __futex_syscall3
+END(__futex_syscall4)
 
-#ifdef CRT_LEGACY_WORKAROUND
-#include "__dso_handle.S"
-#else
-#include "__dso_handle_so.S"
-#endif
+// __futex_wait(*ftx, val, *timespec)
+ENTRY(__futex_wait)
+    stmdb   sp!, {r4, r7}
+    .save   {r4, r7}
+    mov     r3, r2
+    mov     r2, r1
+    mov     r1, #FUTEX_WAIT
+    ldr     r7, =__NR_futex
+    swi     #0
+    ldmia   sp!, {r4, r7}
+    bx      lr
+END(__futex_wait)
 
-#include "atexit.S"
+// __futex_wake(*ftx, counter)
+ENTRY(__futex_wake)
+    .save   {r4, r7}
+    stmdb   sp!, {r4, r7}
+    mov     r2, r1
+    mov     r1, #FUTEX_WAKE
+    ldr     r7, =__NR_futex
+    swi     #0
+    ldmia   sp!, {r4, r7}
+    bx      lr
+END(__futex_wake)

libc/arch-arm/bionic/kill.S

@@ -25,6 +25,11 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
+
+#include <linux/err.h>
+#include <asm/unistd.h>
+#include <machine/asm.h>
+
 /* unlike our auto-generated syscall stubs, this code saves lr
    on the stack, as well as a few other registers. this makes
    our stack unwinder happy, when we generate debug stack
@@ -32,22 +37,14 @@
    abort due to a fatal runtime error (e.g. detection
    of a corrupted malloc heap).
 */
-#include <sys/linux-syscalls.h>
 
-#ifndef __NR_kill
-#define __NR_kill   37
-#endif
-
-    .text
-    .type kill, #function
-    .globl kill
-    .align 4
-
-kill:
+ENTRY(kill)
     stmfd   sp!, {r4-r7, ip, lr}
     ldr     r7, =__NR_kill
     swi     #0
     ldmfd   sp!, {r4-r7, ip, lr}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(kill)

libc/arch-arm/bionic/libgcc_compat.c

@@ -30,7 +30,7 @@
  * dynamic linker to copy their definition into the final libc.so binary.
  *
  * They are required to ensure backwards binary compatibility with
- * Android 1.5 and Android 1.6 system images. Some applications built
+ * Android 1.5, 1.6 and even 3.0  system images. Some applications built
  * using the NDK require them to be here.
  *
  * Now, for a more elaborate description of the issue:
@@ -66,7 +66,12 @@
  * any native shared library generated with it should now be safe from that
  * problem. On the other hand, existing shared libraries distributed with
  * applications that were generated with a previous version of the NDK
- * still need all 1.5/1.6 helper functions in libc.so and libn.so
+ * still need all 1.5/1.6 helper functions in libc.so and libm.so
+ *
+ * After 3.2, the toolchain was updated again, adding __aeabi_f2uiz to the
+ * list of requirements. Technically, this is due to mis-linked NDK libraries
+ * but it is easier to add a single function here than asking several app
+ * developers to fix their build.
  *
  * Final note: some of the functions below should really be in libm.so to
  *             completely reflect the state of 1.5/1.6 system images. However,
@@ -96,6 +101,7 @@
     XX(__aeabi_dsub)         \
     XX(__aeabi_f2d)          \
     XX(__aeabi_f2iz)         \
+    XX(__aeabi_f2uiz)        \
     XX(__aeabi_fadd)         \
     XX(__aeabi_fcmpun)       \
     XX(__aeabi_fdiv)         \
@@ -104,9 +110,12 @@
     XX(__aeabi_fsub)         \
     XX(__aeabi_i2d)          \
     XX(__aeabi_i2f)          \
+    XX(__aeabi_idiv)         \
     XX(__aeabi_l2d)          \
     XX(__aeabi_l2f)          \
     XX(__aeabi_lmul)         \
+    XX(__aeabi_llsl)         \
+    XX(__aeabi_llsr)         \
     XX(__aeabi_ui2d)         \
     XX(__aeabi_ui2f)         \
     XX(__aeabi_ul2d)         \

libc/arch-arm/bionic/memcmp.S

@@ -27,52 +27,95 @@
  */
 
 #include <machine/cpu-features.h>
+#include <machine/asm.h>
 
-    .text
 
-    .global memcmp
-    .type memcmp, %function
-    .align 4
+#ifdef HAVE_32_BYTE_CACHE_LINE
+#define CACHE_LINE_SIZE     32
+#else
+#define CACHE_LINE_SIZE     64
+#endif
 
 /*
- * Optimized memcmp() for ARM9.
- * This would not be optimal on XScale or ARM11, where more prefetching
- * and use of PLD will be needed.
- * The 2 major optimzations here are
- * (1) The main loop compares 16 bytes at a time
- * (2) The loads are scheduled in a way they won't stall
+ * Optimized memcmp() for Cortex-A9.
  */
 
-memcmp:
-        .fnstart
-        PLD         (r0, #0)
-        PLD         (r1, #0)
+ENTRY(memcmp)
+        pld         [r0, #(CACHE_LINE_SIZE * 0)]
+        pld         [r0, #(CACHE_LINE_SIZE * 1)]
 
         /* take of the case where length is 0 or the buffers are the same */
         cmp         r0, r1
-        cmpne       r2, #0
         moveq       r0, #0
         bxeq        lr
 
+        pld         [r1, #(CACHE_LINE_SIZE * 0)]
+        pld         [r1, #(CACHE_LINE_SIZE * 1)]
+
+        /* make sure we have at least 8+4 bytes, this simplify things below
+         * and avoid some overhead for small blocks
+         */
+        cmp        r2, #(8+4)
+        bmi        10f
+/*
+ * Neon optimization
+ * Comparing 32 bytes at a time
+ */
+#if defined(__ARM_NEON__) && defined(NEON_UNALIGNED_ACCESS)
+        subs        r2, r2, #32
+        blo         3f
+
+        /* preload all the cache lines we need. */
+        pld         [r0, #(CACHE_LINE_SIZE * 2)]
+        pld         [r1, #(CACHE_LINE_SIZE * 2)]
+
+1:      /* The main loop compares 32 bytes at a time */
+        vld1.8      {d0 - d3}, [r0]!
+        pld         [r0, #(CACHE_LINE_SIZE * 2)]
+        vld1.8      {d4 - d7}, [r1]!
+        pld         [r1, #(CACHE_LINE_SIZE * 2)]
+
+        /* Start subtracting the values and merge results */
+        vsub.i8     q0, q2
+        vsub.i8     q1, q3
+        vorr        q2, q0, q1
+        vorr        d4, d5
+        vmov        r3, ip, d4
+        /* Check if there are any differences among the 32 bytes */
+        orrs        r3, ip
+        bne         2f
+        subs        r2, r2, #32
+        bhs         1b
+        b           3f
+2:
+        /* Check if the difference was in the first or last 16 bytes */
+        sub         r0, #32
+        vorr        d0, d1
+        sub         r1, #32
+        vmov        r3, ip, d0
+        orrs        r3, ip
+        /* if the first 16 bytes are equal, we only have to rewind 16 bytes */
+        ittt        eq
+        subeq       r2, #16
+        addeq       r0, #16
+        addeq       r1, #16
+
+3:      /* fix-up the remaining count */
+        add         r2, r2, #32
+
+        cmp        r2, #(8+4)
+        bmi        10f
+#endif
+
         .save {r4, lr}
         /* save registers */
         stmfd       sp!, {r4, lr}
-        
-        PLD         (r0, #32)
-        PLD         (r1, #32)
 
         /* since r0 hold the result, move the first source
          * pointer somewhere else
          */
-         
          mov        r4, r0
-         
-         /* make sure we have at least 8+4 bytes, this simplify things below
-          * and avoid some overhead for small blocks
-          */
-         cmp        r2, #(8+4)
-         bmi        8f
-        
+
         /* align first pointer to word boundary
          * offset = -src & 3
          */
@@ -108,9 +151,9 @@ memcmp:
         ldr         ip, [r1]
         subs        r2, r2, #(32 + 4)
         bmi         1f
-        
-0:      PLD         (r4, #64)
-        PLD         (r1, #64)
+
+0:      pld         [r4, #(CACHE_LINE_SIZE * 2)]
+        pld         [r1, #(CACHE_LINE_SIZE * 2)]
         ldr         r0, [r4], #4
         ldr         lr, [r1, #4]!
         eors        r0, r0, ip
@@ -135,14 +178,14 @@ memcmp:
         ldreq       r0, [r4], #4
         ldreq       ip, [r1, #4]!
         eoreqs      r0, r0, lr
-        bne         2f        
+        bne         2f
         subs        r2, r2, #32
         bhs         0b
 
         /* do we have at least 4 bytes left? */
 1:      adds        r2, r2, #(32 - 4 + 4)
         bmi         4f
-        
+
         /* finish off 4 bytes at a time */
 3:      ldr         r0, [r4], #4
         ldr         ip, [r1], #4
@@ -176,19 +219,28 @@ memcmp:
 9:      /* restore registers and return */
         ldmfd       sp!, {r4, lr}
         bx          lr
-        .fnend
-
-
-
 
+10:     /* process less than 12 bytes */
+        cmp         r2, #0
+        moveq       r0, #0
+        bxeq        lr
+        mov         r3, r0
+11:
+        ldrb        r0, [r3], #1
+        ldrb        ip, [r1], #1
+        subs        r0, ip
+        bxne        lr
+        subs        r2, r2, #1
+        bne         11b
+        bx          lr
 
 5:      /*************** non-congruent case ***************/
-        and         r0, r1, #3      
+        and         r0, r1, #3
         cmp         r0, #2
         bne         4f
 
         /* here, offset is 2 (16-bits aligned, special cased) */
-        
+
         /* make sure we have at least 16 bytes to process */
         subs        r2, r2, #16
         addmi       r2, r2, #16
@@ -198,8 +250,8 @@ memcmp:
         bic         r1, r1, #3
         ldr         lr, [r1], #4
 
-6:      PLD         (r1, #64)
-        PLD         (r4, #64)
+6:      pld         [r1, #(CACHE_LINE_SIZE * 2)]
+        pld         [r4, #(CACHE_LINE_SIZE * 2)]
         mov         ip, lr, lsr #16
         ldr         lr, [r1], #4
         ldr         r0, [r4], #4
@@ -286,3 +338,4 @@ memcmp:
         mov         r2, #4
 		ldmfd		sp!, {r5, r6, r7}
         b           8b
+END(memcmp)

libc/arch-arm/bionic/memcmp16.S

@@ -27,12 +27,7 @@
  */
 
 #include <machine/cpu-features.h>
-
-    .text
-
-    .global __memcmp16
-    .type __memcmp16, %function
-    .align 4
+#include <machine/asm.h>
 
 /*
  * Optimized memcmp16() for ARM9.
@@ -43,8 +38,7 @@
  * (2) The loads are scheduled in a way they won't stall
  */
 
-__memcmp16:
-        .fnstart
+ENTRY(__memcmp16)
         PLD         (r0, #0)
         PLD         (r1, #0)
 
@@ -95,8 +89,6 @@ __memcmp16:
         /* restore registers and return */
         ldmnefd     sp!, {r4, lr}
         bxne        lr
-        .fnend
-
 
 
 0:      /* here the first pointer is aligned, and we have at least 3 words
@@ -237,3 +229,4 @@ __memcmp16:
 7:      /* fix up the 2 pointers and fallthrough... */
         sub         r1, r1, #2
         b           2b
+END(__memcmp16)

libc/arch-arm/bionic/memcpy.S

@@ -27,37 +27,45 @@
  */
 
 #include <machine/cpu-features.h>
+#include <machine/asm.h>
 
-#if defined(__ARM_NEON__)
+#if defined(__ARM_NEON__) && !defined(ARCH_ARM_USE_NON_NEON_MEMCPY)
 
         .text
         .fpu    neon
 
-        .global memcpy
-        .type memcpy, %function
-        .align 4
-
+#ifdef HAVE_32_BYTE_CACHE_LINE
+/* a prefetch distance of 2 cache-lines */
+#define CACHE_LINE_SIZE     32
+#else
 /* a prefetch distance of 4 cache-lines works best experimentally */
 #define CACHE_LINE_SIZE     64
-#define PREFETCH_DISTANCE   (CACHE_LINE_SIZE*4)
+#endif
 
-memcpy:
-        .fnstart
+ENTRY(memcpy)
         .save       {r0, lr}
-        stmfd       sp!, {r0, lr}
-
         /* start preloading as early as possible */
-        pld         [r1, #(CACHE_LINE_SIZE*0)]
-        pld         [r1, #(CACHE_LINE_SIZE*1)]
+        pld         [r1, #(CACHE_LINE_SIZE * 0)]
+        stmfd       sp!, {r0, lr}
+        pld         [r1, #(CACHE_LINE_SIZE * 1)]
 
+/* If Neon supports unaligned access then remove the align code,
+ * unless a size limit has been specified.
+ */
+#ifndef NEON_UNALIGNED_ACCESS
         /* do we have at least 16-bytes to copy (needed for alignment below) */
         cmp         r2, #16
         blo         5f
 
-        /* align destination to half cache-line for the write-buffer */
+        /* check if buffers are aligned. If so, run arm-only version */
+        eor         r3, r0, r1
+        ands        r3, r3, #0x3
+        beq         11f
+
+        /* align destination to cache-line for the write-buffer */
         rsb         r3, r0, #0
         ands        r3, r3, #0xF
-        beq         0f
+        beq         2f
 
         /* copy up to 15-bytes (count in r3) */
         sub         r2, r2, r3
@@ -78,14 +86,14 @@ memcpy:
         vld1.8      {d0}, [r1]!
         vst1.8      {d0}, [r0, :64]!
 2:
+        /* preload immediately the next cache line, which we may need */
+        pld         [r1, #(CACHE_LINE_SIZE * 0)]
+        pld         [r1, #(CACHE_LINE_SIZE * 1)]
 
-0:      /* preload immediately the next cache line, which we may need */
-        pld         [r1, #(CACHE_LINE_SIZE*0)]
-        pld         [r1, #(CACHE_LINE_SIZE*1)]
-
-        /* make sure we have at least 64 bytes to copy */
-        subs        r2, r2, #64
-        blo         2f
+#ifdef HAVE_32_BYTE_CACHE_LINE
+        /* make sure we have at least 32 bytes to copy */
+        subs        r2, r2, #32
+        blo         4f
 
         /* preload all the cache lines we need.
          * NOTE: the number of pld below depends on PREFETCH_DISTANCE,
@@ -93,17 +101,35 @@ memcpy:
          * avoid the goofy code below. In practice this doesn't seem to make
          * a big difference.
          */
-        pld         [r1, #(CACHE_LINE_SIZE*2)]
-        pld         [r1, #(CACHE_LINE_SIZE*3)]
         pld         [r1, #(PREFETCH_DISTANCE)]
 
-1:      /* The main loop copies 64 bytes at a time */
+1:      /* The main loop copies 32 bytes at a time */
         vld1.8      {d0  - d3},   [r1]!
-        vld1.8      {d4  - d7},   [r1]!
         pld         [r1, #(PREFETCH_DISTANCE)]
-        subs        r2, r2, #64
+        subs        r2, r2, #32
         vst1.8      {d0  - d3},   [r0, :128]!
-        vst1.8      {d4  - d7},   [r0, :128]!
+        bhs         1b
+#else
+        /* make sure we have at least 64 bytes to copy */
+        subs        r2, r2, #64
+        blo         2f
+
+        /* preload all the cache lines we need. */
+        pld         [r1, #(CACHE_LINE_SIZE * 2)]
+        pld         [r1, #(CACHE_LINE_SIZE * 3)]
+
+1:      /* The main loop copies 64 bytes at a time */
+        vld1.8      {d0 - d3}, [r1]!
+        vld1.8      {d4 - d7}, [r1]!
+#ifdef  HAVE_32_BYTE_CACHE_LINE
+        pld         [r1, #(CACHE_LINE_SIZE * 2)]
+        pld         [r1, #(CACHE_LINE_SIZE * 3)]
+#else
+        pld         [r1, #(CACHE_LINE_SIZE * 3)]
+#endif
+        subs        r2, r2, #64
+        vst1.8      {d0 - d3}, [r0, :128]!
+        vst1.8      {d4 - d7}, [r0, :128]!
         bhs         1b
 
 2:      /* fix-up the remaining count and make sure we have >= 32 bytes left */
@@ -112,11 +138,11 @@ memcpy:
         blo         4f
 
 3:      /* 32 bytes at a time. These cache lines were already preloaded */
-        vld1.8      {d0 - d3},  [r1]!
+        vld1.8      {d0 - d3}, [r1]!
         subs        r2, r2, #32
-        vst1.8      {d0 - d3},  [r0, :128]!
+        vst1.8      {d0 - d3}, [r0, :128]!
         bhs         3b
-
+#endif
 4:      /* less than 32 left */
         add         r2, r2, #32
         tst         r2, #0x10
@@ -124,7 +150,6 @@ memcpy:
         // copies 16 bytes, 128-bits aligned
         vld1.8      {d0, d1}, [r1]!
         vst1.8      {d0, d1}, [r0, :128]!
-
 5:      /* copy up to 15-bytes (count in r2) */
         movs        ip, r2, lsl #29
         bcc         1f
@@ -143,18 +168,170 @@ memcpy:
 
         ldmfd       sp!, {r0, lr}
         bx          lr
-        .fnend
+
+#else   /* NEON_UNALIGNED_ACCESS */
+
+        // Check so divider is at least 16 bytes, needed for alignment code.
+        cmp         r2, #16
+        blo         5f
+
+#ifdef NEON_MEMCPY_ALIGNMENT_DIVIDER
+        /* Check the upper size limit for Neon unaligned memory access in memcpy */
+#if NEON_MEMCPY_ALIGNMENT_DIVIDER >= 16
+        cmp         r2, #NEON_MEMCPY_ALIGNMENT_DIVIDER
+        blo         3f
+#endif
+        /* check if buffers are aligned. If so, run arm-only version */
+        eor         r3, r0, r1
+        ands        r3, r3, #0x3
+        beq         11f
+
+        /* align destination to 16 bytes for the write-buffer */
+        rsb         r3, r0, #0
+        ands        r3, r3, #0xF
+        beq         3f
+
+        /* copy up to 15-bytes (count in r3) */
+        sub         r2, r2, r3
+        movs        ip, r3, lsl #31
+        ldrmib      lr, [r1], #1
+        strmib      lr, [r0], #1
+        ldrcsb      ip, [r1], #1
+        ldrcsb      lr, [r1], #1
+        strcsb      ip, [r0], #1
+        strcsb      lr, [r0], #1
+        movs        ip, r3, lsl #29
+        bge         1f
+        // copies 4 bytes, destination 32-bits aligned
+        vld1.32     {d0[0]}, [r1]!
+        vst1.32     {d0[0]}, [r0, :32]!
+1:      bcc         2f
+        // copies 8 bytes, destination 64-bits aligned
+        vld1.8      {d0}, [r1]!
+        vst1.8      {d0}, [r0, :64]!
+2:
+        /* preload immediately the next cache line, which we may need */
+        pld         [r1, #(CACHE_LINE_SIZE * 0)]
+        pld         [r1, #(CACHE_LINE_SIZE * 1)]
+3:
+#endif
+        /* make sure we have at least 64 bytes to copy */
+        subs        r2, r2, #64
+        blo         2f
+
+        /* preload all the cache lines we need */
+        pld         [r1, #(CACHE_LINE_SIZE * 2)]
+        pld         [r1, #(CACHE_LINE_SIZE * 3)]
+
+1:      /* The main loop copies 64 bytes at a time */
+        vld1.8      {d0 - d3}, [r1]!
+        vld1.8      {d4 - d7}, [r1]!
+#ifdef  HAVE_32_BYTE_CACHE_LINE
+        pld         [r1, #(CACHE_LINE_SIZE * 2)]
+        pld         [r1, #(CACHE_LINE_SIZE * 3)]
+#else
+        pld         [r1, #(CACHE_LINE_SIZE * 3)]
+#endif
+        subs        r2, r2, #64
+        vst1.8      {d0 - d3}, [r0]!
+        vst1.8      {d4 - d7}, [r0]!
+        bhs         1b
+
+2:      /* fix-up the remaining count and make sure we have >= 32 bytes left */
+        add         r2, r2, #64
+        subs        r2, r2, #32
+        blo         4f
+
+3:      /* 32 bytes at a time. These cache lines were already preloaded */
+        vld1.8      {d0 - d3}, [r1]!
+        subs        r2, r2, #32
+        vst1.8      {d0 - d3}, [r0]!
+        bhs         3b
+
+4:      /* less than 32 left */
+        add         r2, r2, #32
+        tst         r2, #0x10
+        beq         5f
+        // copies 16 bytes, 128-bits aligned
+        vld1.8      {d0, d1}, [r1]!
+        vst1.8      {d0, d1}, [r0]!
+5:      /* copy up to 15-bytes (count in r2) */
+        movs        ip, r2, lsl #29
+        bcc         1f
+        vld1.8      {d0}, [r1]!
+        vst1.8      {d0}, [r0]!
+1:      bge         2f
+        vld1.32     {d0[0]}, [r1]!
+        vst1.32     {d0[0]}, [r0]!
+2:      movs        ip, r2, lsl #31
+        ldrmib      r3, [r1], #1
+        ldrcsb      ip, [r1], #1
+        ldrcsb      lr, [r1], #1
+        strmib      r3, [r0], #1
+        strcsb      ip, [r0], #1
+        strcsb      lr, [r0], #1
+
+        ldmfd       sp!, {r0, lr}
+        bx          lr
+#endif  /* NEON_UNALIGNED_ACCESS */
+11:
+        /* Simple arm-only copy loop to handle aligned copy operations */
+        stmfd       sp!, {r4, r5, r6, r7, r8}
+        pld         [r1, #(CACHE_LINE_SIZE * 2)]
+
+        /* Check alignment */
+        rsb         r3, r1, #0
+        ands        r3, #3
+        beq         2f
+
+        /* align source to 32 bits. We need to insert 2 instructions between
+         * a ldr[b|h] and str[b|h] because byte and half-word instructions
+         * stall 2 cycles.
+         */
+        movs        r12, r3, lsl #31
+        sub         r2, r2, r3      /* we know that r3 <= r2 because r2 >= 4 */
+        ldrmib      r3, [r1], #1
+        ldrcsb      r4, [r1], #1
+        ldrcsb      r5, [r1], #1
+        strmib      r3, [r0], #1
+        strcsb      r4, [r0], #1
+        strcsb      r5, [r0], #1
+2:
+        subs        r2, #32
+        blt         5f
+        pld         [r1, #(CACHE_LINE_SIZE * 3)]
+3:      /* Main copy loop, copying 32 bytes at a time */
+        pld         [r1, #(CACHE_LINE_SIZE * 4)]
+        ldmia       r1!, {r3, r4, r5, r6, r7, r8, r12, lr}
+        subs        r2, r2, #32
+        stmia       r0!, {r3, r4, r5, r6, r7, r8, r12, lr}
+        bge         3b
+5:      /* Handle any remaining bytes */
+        adds        r2, #32
+        beq         6f
+
+        movs        r12, r2, lsl #28
+        ldmcsia     r1!, {r3, r4, r5, r6}   /* 16 bytes */
+        ldmmiia     r1!, {r7, r8}           /*  8 bytes */
+        stmcsia     r0!, {r3, r4, r5, r6}
+        stmmiia     r0!, {r7, r8}
+        movs        r12, r2, lsl #30
+        ldrcs       r3, [r1], #4            /*  4 bytes */
+        ldrmih      r4, [r1], #2            /*  2 bytes */
+        strcs       r3, [r0], #4
+        strmih      r4, [r0], #2
+        tst         r2, #0x1
+        ldrneb      r3, [r1]                /*  last byte  */
+        strneb      r3, [r0]
+6:
+        ldmfd       sp!, {r4, r5, r6, r7, r8}
+        ldmfd       sp!, {r0, pc}
+END(memcpy)
 
 
 #else   /* __ARM_ARCH__ < 7 */
 
 
-	.text
-
-    .global memcpy
-    .type memcpy, %function
-    .align 4
-
 		/*
 		 * Optimized memcpy() for ARM.
          *
@@ -162,12 +339,11 @@ memcpy:
 		 * so we have to preserve R0.
 		 */
 
-memcpy:
+ENTRY(memcpy)
 		/* The stack must always be 64-bits aligned to be compliant with the
 		 * ARM ABI. Since we have to save R0, we might as well save R4
 		 * which we can use for better pipelining of the reads below
 		 */
-        .fnstart
         .save       {r0, r4, lr}
         stmfd       sp!, {r0, r4, lr}
         /* Making room for r5-r11 which will be spilled later */
@@ -504,7 +680,7 @@ copy_last_3_and_return:
         add         sp,  sp, #28
 		ldmfd		sp!, {r0, r4, lr}
 		bx			lr
-        .fnend
+END(memcpy)
 
 
 #endif    /* __ARM_ARCH__ < 7 */

libc/arch-arm/bionic/memcpy.a15.S

@@ -0,0 +1,406 @@
+/*
+ * Copyright (c) 2013 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+    /* Prototype: void *memcpy (void *dst, const void *src, size_t count).  */
+
+        /* Use the version of memcpy implemented using LDRD and STRD.
+           This version is tuned for Cortex-A15.
+           This might not be the best for other ARMv7-A CPUs,
+           but there is no predefine to distinguish between
+           different CPUs in the same architecture,
+           and this version is better than the plain memcpy provided in newlib.
+
+           Therefore, we use this version for all ARMv7-A CPUS.  */
+
+        /* To make the same code compile for both ARM and Thumb instruction
+       sets, switch to unified syntax at the beginning of this function.
+           However, by using the same code, we may be missing optimization
+       opportunities.  For instance, in LDRD/STRD instructions, the first
+       destination register must be even and the second consecutive in
+       ARM state, but not in Thumb state.  */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+        .syntax         unified
+
+ENTRY(memcpy)
+
+       /* Assumes that n >= 0, and dst, src are valid pointers.
+          If there is at least 8 bytes to copy, use LDRD/STRD.
+          If src and dst are misaligned with different offsets,
+          first copy byte by byte until dst is aligned,
+          and then copy using LDRD/STRD and shift if needed.
+          When less than 8 left, copy a word and then byte by byte.  */
+
+       /* Save registers (r0 holds the return value):
+          optimized push {r0, r4, r5, r6, r7, lr}.
+          To try and improve performance, stack layout changed,
+          i.e., not keeping the stack looking like users expect
+          (highest numbered register at highest address).  */
+        .save   {r0, lr}
+        push    {r0, lr}
+        .save   {r4, r5}
+        strd    r4, r5, [sp, #-8]!
+        .save   {r6, r7}
+        strd    r6, r7, [sp, #-8]!
+
+       /* TODO: Add debug frame directives.
+          We don't need exception unwind directives, because the code below
+      does not throw any exceptions and does not call any other functions.
+          Generally, newlib functions like this lack debug information for
+      assembler source.  */
+
+        /* Get copying of tiny blocks out of the way first.  */
+        /* Is there at least 4 bytes to copy?  */
+        subs    r2, r2, #4
+        blt     copy_less_than_4                 /* If n < 4.  */
+
+        /* Check word alignment.  */
+        ands    ip, r0, #3                       /* ip = last 2 bits of dst.  */
+        bne     dst_not_word_aligned             /* If dst is not word-aligned.  */
+
+        /* Get here if dst is word-aligned.  */
+        ands    ip, r1, #3                      /* ip = last 2 bits of src.  */
+        bne     src_not_word_aligned            /* If src is not word-aligned.  */
+word_aligned:
+        /* Get here if source and dst both are word-aligned.
+           The number of bytes remaining to copy is r2+4.  */
+
+        /* Is there is at least 64 bytes to copy?  */
+        subs    r2, r2, #60
+        blt     copy_less_than_64                /* If r2 + 4 < 64.  */
+
+        /* First, align the destination buffer to 8-bytes,
+           to make sure double loads and stores don't cross cache line boundary,
+           as they are then more expensive even if the data is in the cache
+           (require two load/store issue cycles instead of one).
+           If only one of the buffers is not 8-bytes aligned,
+           then it's more important to align dst than src,
+           because there is more penalty for stores
+           than loads that cross cacheline boundary.
+           This check and realignment are only worth doing
+           if there is a lot to copy.  */
+
+        /* Get here if dst is word aligned,
+           i.e., the 2 least significant bits are 0.
+           If dst is not 2w aligned (i.e., the 3rd bit is not set in dst),
+           then copy 1 word (4 bytes).  */
+        ands    r3, r0, #4
+        beq     11f                  /* If dst already two-word aligned.  */
+        ldr     r3, [r1], #4
+        str     r3, [r0], #4
+        subs    r2, r2, #4
+        blt     copy_less_than_64
+
+11:
+        /* TODO: Align to cacheline (useful for PLD optimization).  */
+
+        /* Every loop iteration copies 64 bytes.  */
+1:
+        .irp    offset, #0, #8, #16, #24, #32, #40, #48, #56
+        ldrd    r4, r5, [r1, \offset]
+        strd    r4, r5, [r0, \offset]
+        .endr
+
+        add     r0, r0, #64
+        add     r1, r1, #64
+        subs    r2, r2, #64
+        bge     1b                            /* If there is more to copy.  */
+
+copy_less_than_64:
+
+        /* Get here if less than 64 bytes to copy, -64 <= r2 < 0.
+           Restore the count if there is more than 7 bytes to copy.  */
+        adds    r2, r2, #56
+        blt     copy_less_than_8
+
+        /* Copy 8 bytes at a time.  */
+2:
+        ldrd    r4, r5, [r1], #8
+        strd    r4, r5, [r0], #8
+        subs    r2, r2, #8
+        bge     2b                            /* If there is more to copy.  */
+
+copy_less_than_8:
+
+        /* Get here if less than 8 bytes to copy, -8 <= r2 < 0.
+           Check if there is more to copy.  */
+        cmn     r2, #8
+        beq     return                          /* If r2 + 8 == 0.  */
+
+        /* Restore the count if there is more than 3 bytes to copy.  */
+        adds    r2, r2, #4
+        blt     copy_less_than_4
+
+        /* Copy 4 bytes.  */
+        ldr     r3, [r1], #4
+        str     r3, [r0], #4
+
+copy_less_than_4:
+        /* Get here if less than 4 bytes to copy, -4 <= r2 < 0.  */
+
+        /* Restore the count, check if there is more to copy.  */
+        adds    r2, r2, #4
+        beq     return                          /* If r2 == 0.  */
+
+        /* Get here with r2 is in {1,2,3}={01,10,11}.  */
+        /* Logical shift left r2, insert 0s, update flags.  */
+        lsls    r2, r2, #31
+
+        /* Copy byte by byte.
+           Condition ne means the last bit of r2 is 0.
+           Condition cs means the second to last bit of r2 is set,
+           i.e., r2 is 1 or 3.  */
+        itt     ne
+        ldrbne  r3, [r1], #1
+        strbne  r3, [r0], #1
+
+        itttt   cs
+        ldrbcs  r4, [r1], #1
+        ldrbcs  r5, [r1]
+        strbcs  r4, [r0], #1
+        strbcs  r5, [r0]
+
+return:
+        /* Restore registers: optimized pop {r0, r4, r5, r6, r7, pc}   */
+        /* This is the only return point of memcpy.  */
+        ldrd r6, r7, [sp], #8
+        ldrd r4, r5, [sp], #8
+        pop {r0, pc}
+
+#ifndef __ARM_FEATURE_UNALIGNED
+
+       /* The following assembly macro implements misaligned copy in software.
+          Assumes that dst is word aligned, src is at offset "pull" bits from
+      word, push = 32 - pull, and the number of bytes that remain to copy
+      is r2 + 4, r2 >= 0.  */
+
+       /* In the code below, r2 is the number of bytes that remain to be
+      written.  The number of bytes read is always larger, because we have
+      partial words in the shift queue.  */
+
+        .macro  miscopy pull push shiftleft shiftright
+
+        /* Align src to the previous word boundary.  */
+        bic     r1, r1, #3
+
+        /* Initialize the shift queue.  */
+        ldr     r5, [r1], #4                   /* Load a word from source.  */
+
+        subs    r2, r2, #4
+        blt     6f          /* Go to misaligned copy of less than 8 bytes.  */
+
+       /* Get here if there is more than 8 bytes to copy.
+          The number of bytes to copy is r2+8, r2 >= 0.  */
+
+       subs     r2, r2, #56
+       blt      4f         /* Go to misaligned copy of less than 64 bytes.  */
+
+3:
+       /* Get here if there is more than 64 bytes to copy.
+          The number of bytes to copy is r2+64, r2 >= 0.  */
+
+       /* Copy 64 bytes in every iteration.
+          Use a partial word from the shift queue.  */
+        .irp    offset, #0, #8, #16, #24, #32, #40, #48, #56
+        mov     r6, r5, \shiftleft #\pull
+        ldrd    r4, r5, [r1, \offset]
+        orr     r6, r6, r4, \shiftright #\push
+        mov     r7, r4, \shiftleft #\pull
+        orr     r7, r7, r5, \shiftright #\push
+        strd    r6, r7, [r0, \offset]
+        .endr
+
+        add     r1, r1, #64
+        add     r0, r0, #64
+        subs    r2, r2, #64
+        bge     3b
+
+4:
+       /* Get here if there is less than 64 bytes to copy (-64 <= r2 < 0)
+      and they are misaligned.  */
+
+       /* Restore the count if there is more than 7 bytes to copy.  */
+        adds    r2, r2, #56
+
+        blt     6f          /* Go to misaligned copy of less than 8 bytes.  */
+
+5:
+        /* Copy 8 bytes at a time.
+           Use a partial word from the shift queue.  */
+        mov     r6, r5, \shiftleft #\pull
+        ldrd    r4, r5, [r1], #8
+        orr     r6, r6, r4, \shiftright #\push
+        mov     r7, r4, \shiftleft #\pull
+        orr     r7, r7, r5, \shiftright #\push
+        strd    r6, r7, [r0], #8
+
+        subs    r2, r2, #8
+        bge     5b                        /* If there is more to copy.  */
+
+6:
+        /* Get here if there less than 8 bytes to copy (-8 <= r2 < 0)
+           and they are misaligned.  */
+
+        /* Check if there is more to copy.  */
+        cmn     r2, #8
+        beq     return
+
+        /* Check if there is less than 4 bytes to copy.  */
+        cmn     r2, #4
+
+        itt     lt
+        /* Restore src offset from word-align.  */
+        sublt   r1, r1, #(\push / 8)
+        blt     copy_less_than_4
+
+        /* Use a partial word from the shift queue.  */
+        mov     r3, r5, \shiftleft #\pull
+        /* Load a word from src, but without writeback
+           (this word is not fully written to dst).  */
+        ldr     r5, [r1]
+
+        /* Restore src offset from word-align.  */
+        add     r1, r1, #(\pull / 8)
+
+        /* Shift bytes to create one dst word and store it.  */
+        orr     r3, r3, r5, \shiftright #\push
+        str     r3, [r0], #4
+
+        /* Use single byte copying of the remaining bytes.  */
+        b       copy_less_than_4
+
+        .endm
+
+#endif /* not __ARM_FEATURE_UNALIGNED  */
+
+dst_not_word_aligned:
+
+       /* Get here when dst is not aligned and ip has the last 2 bits of dst,
+          i.e., ip is the offset of dst from word.
+          The number of bytes that remains to copy is r2 + 4,
+          i.e., there are at least 4 bytes to copy.
+          Write a partial word (0 to 3 bytes), such that dst becomes
+      word-aligned.  */
+
+       /* If dst is at ip bytes offset from a word (with 0 < ip < 4),
+          then there are (4 - ip) bytes to fill up to align dst to the next
+      word.  */
+        rsb     ip, ip, #4                        /* ip = #4 - ip.  */
+        cmp     ip, #2
+
+       /* Copy byte by byte with conditionals.  */
+        itt     gt
+        ldrbgt  r3, [r1], #1
+        strbgt  r3, [r0], #1
+
+        itt     ge
+        ldrbge  r4, [r1], #1
+        strbge  r4, [r0], #1
+
+        ldrb    lr, [r1], #1
+        strb    lr, [r0], #1
+
+       /* Update the count.
+          ip holds the number of bytes we have just copied.  */
+        subs    r2, r2, ip                        /* r2 = r2 - ip.  */
+        blt     copy_less_than_4                  /* If r2 < ip.  */
+
+       /* Get here if there are more than 4 bytes to copy.
+          Check if src is aligned.  If beforehand src and dst were not word
+      aligned but congruent (same offset), then now they are both
+      word-aligned, and we can copy the rest efficiently (without
+      shifting).  */
+        ands    ip, r1, #3                    /* ip = last 2 bits of src.  */
+        beq     word_aligned                  /* If r1 is word-aligned.  */
+
+src_not_word_aligned:
+       /* Get here when src is not word-aligned, but dst is word-aligned.
+          The number of bytes that remains to copy is r2+4.  */
+
+#ifdef __ARM_FEATURE_UNALIGNED
+       /* Copy word by word using LDR when alignment can be done in hardware,
+          i.e., SCTLR.A is set, supporting unaligned access in LDR and STR.  */
+        subs    r2, r2, #60
+        blt     8f
+
+7:
+        /* Copy 64 bytes in every loop iteration.  */
+        .irp    offset, #0, #4, #8, #12, #16, #20, #24, #28, #32, #36, #40, #44, #48, #52, #56, #60
+        ldr     r3, [r1, \offset]
+        str     r3, [r0, \offset]
+        .endr
+
+        add     r0, r0, #64
+        add     r1, r1, #64
+        subs    r2, r2, #64
+        bge     7b
+
+8:
+        /* Get here if less than 64 bytes to copy, -64 <= r2 < 0.
+           Check if there is more than 3 bytes to copy.  */
+        adds    r2, r2, #60
+        blt     copy_less_than_4
+
+9:
+       /* Get here if there is less than 64 but at least 4 bytes to copy,
+          where the number of bytes to copy is r2+4.  */
+        ldr     r3, [r1], #4
+        str     r3, [r0], #4
+        subs    r2, r2, #4
+        bge     9b
+
+        b       copy_less_than_4
+
+#else /* not __ARM_FEATURE_UNALIGNED  */
+
+       /* ip has last 2 bits of src,
+          i.e., ip is the offset of src from word, and ip > 0.
+          Compute shifts needed to copy from src to dst.  */
+        cmp     ip, #2
+        beq     miscopy_16_16             /* If ip == 2.  */
+        bge     miscopy_24_8              /* If ip == 3.  */
+
+        /* Get here if ip == 1.  */
+
+        /* Endian independent macros for shifting bytes within registers.  */
+
+#ifndef __ARMEB__
+miscopy_8_24:   miscopy pull=8 push=24 shiftleft=lsr shiftright=lsl
+miscopy_16_16:  miscopy pull=16 push=16 shiftleft=lsr shiftright=lsl
+miscopy_24_8:   miscopy pull=24 push=8 shiftleft=lsr shiftright=lsl
+#else  /* not __ARMEB__ */
+miscopy_8_24:   miscopy pull=8 push=24 shiftleft=lsl shiftright=lsr
+miscopy_16_16:  miscopy pull=16 push=16 shiftleft=lsl shiftright=lsr
+miscopy_24_8:   miscopy pull=24 push=8 shiftleft=lsl shiftright=lsr
+#endif  /* not __ARMEB__ */
+
+#endif  /* not __ARM_FEATURE_UNALIGNED  */
+
+END(memcpy)

libc/arch-arm/bionic/memset.S

@@ -25,31 +25,115 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
-	.text
 
-    .global memset
-    .type memset, %function
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
 
-    .global bzero
-    .type bzero, %function
-
-    .align
-	
 		/*
 		 * Optimized memset() for ARM.
          *
          * memset() returns its first argument.
 		 */
-	
-bzero:
+
+#if defined(__ARM_NEON__)
+    .fpu    neon
+#endif
+
+ENTRY(bzero)
         mov     r2, r1
         mov     r1, #0
+        // Fall through to memset...
+END(bzero)
+
+ENTRY(memset)
+#if defined(__ARM_NEON__)
+
+#ifdef  NEON_MEMSET_DIVIDER
+        cmp         r2, #NEON_MEMSET_DIVIDER
+        bhi         11f
+#endif
+        .save       {r0}
+        stmfd       sp!, {r0}
+
+        vdup.8      q0, r1
+
+#ifndef NEON_UNALIGNED_ACCESS
+        /* do we have at least 16-bytes to write (needed for alignment below) */
+        cmp         r2, #16
+        blo         3f
+
+        /* align destination to 16 bytes for the write-buffer */
+        rsb         r3, r0, #0
+        ands        r3, r3, #0xF
+        beq         2f
+
+        /* write up to 15-bytes (count in r3) */
+        sub         r2, r2, r3
+        movs        ip, r3, lsl #31
+        strmib      r1, [r0], #1
+        strcsb      r1, [r0], #1
+        strcsb      r1, [r0], #1
+        movs        ip, r3, lsl #29
+        bge         1f
+
+        // writes 4 bytes, 32-bits aligned
+        vst1.32     {d0[0]}, [r0, :32]!
+1:      bcc         2f
+
+        // writes 8 bytes, 64-bits aligned
+        vst1.8      {d0}, [r0, :64]!
+2:
+#endif
+        /* make sure we have at least 32 bytes to write */
+        subs        r2, r2, #32
+        blo         2f
+        vmov        q1, q0
+
+1:      /* The main loop writes 32 bytes at a time */
+        subs        r2, r2, #32
+#ifndef NEON_UNALIGNED_ACCESS
+        vst1.8      {d0 - d3}, [r0, :128]!
+#else
+        vst1.8      {d0 - d3}, [r0]!
+#endif
+        bhs         1b
+
+2:      /* less than 32 left */
+        add         r2, r2, #32
+        tst         r2, #0x10
+        beq         3f
+
+        // writes 16 bytes, 128-bits aligned
+#ifndef NEON_UNALIGNED_ACCESS
+        vst1.8      {d0, d1}, [r0, :128]!
+#else
+        vst1.8      {d0, d1}, [r0]!
+#endif
+3:      /* write up to 15-bytes (count in r2) */
+        movs        ip, r2, lsl #29
+        bcc         1f
+        vst1.8      {d0}, [r0]!
+1:      bge         2f
+        vst1.32     {d0[0]}, [r0]!
+2:      movs        ip, r2, lsl #31
+        strmib      r1, [r0], #1
+        strcsb      r1, [r0], #1
+        strcsb      r1, [r0], #1
+        ldmfd       sp!, {r0}
+        bx          lr
+11:
+#endif
+
+        /*
+         * Optimized memset() for ARM.
+         *
+         * memset() returns its first argument.
+         */
 
-memset:	
 		/* compute the offset to align the destination
 		 * offset = (4-(src&3))&3 = -src & 3
 		 */
-        .fnstart
+
         .save       {r0, r4-r7, lr}
 		stmfd		sp!, {r0, r4-r7, lr}
 		rsb			r3, r0, #0
@@ -77,7 +161,7 @@ memset:
         mov         r5, r1
         mov         r6, r1
         mov         r7, r1
-        
+
 		rsb         r3, r0, #0
 		ands		r3, r3, #0x1C
 		beq         3f
@@ -85,7 +169,7 @@ memset:
 		andhi		r3, r2, #0x1C
 		sub         r2, r2, r3
 
-		/* conditionnaly writes 0 to 7 words (length in r3) */
+		/* conditionally writes 0 to 7 words (length in r3) */
 		movs		r3, r3, lsl #28
 		stmcsia		r0!, {r1, lr}
 		stmcsia		r0!, {r1, lr}
@@ -102,7 +186,7 @@ memset:
         bhs         1b
 2:      add         r2, r2, #32
 
-		/* conditionnaly stores 0 to 31 bytes */
+		/* conditionally stores 0 to 31 bytes */
 		movs		r2, r2, lsl #28
 		stmcsia		r0!, {r1,r3,r12,lr}
 		stmmiia		r0!, {r1, lr}
@@ -113,5 +197,4 @@ memset:
 		strcsb		r1, [r0]
         ldmfd		sp!, {r0, r4-r7, lr}
         bx          lr
-        .fnend
-    
+END(memset)

libc/arch-arm/bionic/setjmp.S

@@ -79,6 +79,7 @@ ENTRY(setjmp)
 
 	mov	r0, #0x00000000
 	bx      lr
+END(setjmp)
 
 .Lsetjmp_magic:
 	.word	_JB_MAGIC_SETJMP
@@ -138,3 +139,4 @@ botch:
 	bl	PIC_SYM(_C_LABEL(longjmperror), PLT)
 	bl	PIC_SYM(_C_LABEL(abort), PLT)
 	b	. - 8		/* Cannot get here */
+END(longjmp)

libc/arch-arm/bionic/sigsetjmp.S

@@ -33,6 +33,8 @@
  * SUCH DAMAGE.
  */
 
+#define _ALIGN_TEXT .align 0
+
 #include <machine/asm.h>
 #include <machine/setjmp.h>
 
@@ -50,6 +52,7 @@ ENTRY(sigsetjmp)
 	teq	r1, #0
 	beq	PIC_SYM(_C_LABEL(_setjmp), PLT)
 	b	PIC_SYM(_C_LABEL(setjmp), PLT)
+END(sigsetjmp)
 
 .L_setjmp_magic:
 	.word	_JB_MAGIC__SETJMP
@@ -60,3 +63,4 @@ ENTRY(siglongjmp)
 	teq	r2, r3
 	beq	PIC_SYM(_C_LABEL(_longjmp), PLT)
 	b	PIC_SYM(_C_LABEL(longjmp), PLT)
+END(siglongjmp)

libc/arch-arm/bionic/strcmp.S

@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2011 The Android Open Source Project
+ * Copyright (c) 2008 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+	.text
+
+#ifdef __ARMEB__
+#define SHFT2LSB lsl
+#define SHFT2LSBEQ lsleq
+#define SHFT2MSB lsr
+#define SHFT2MSBEQ lsreq
+#define MSB 0x000000ff
+#define LSB 0xff000000
+#else
+#define SHFT2LSB lsr
+#define SHFT2LSBEQ lsreq
+#define SHFT2MSB lsl
+#define SHFT2MSBEQ lsleq
+#define MSB 0xff000000
+#define LSB 0x000000ff
+#endif
+
+#define magic1(REG) REG
+#define magic2(REG) REG, lsl #7
+
+ENTRY(strcmp)
+	PLD(r0, #0)
+	PLD(r1, #0)
+	eor	r2, r0, r1
+	tst	r2, #3
+
+	/* Strings not at same byte offset from a word boundary.  */
+	bne	.Lstrcmp_unaligned
+	ands	r2, r0, #3
+	bic	r0, r0, #3
+	bic	r1, r1, #3
+	ldr	ip, [r0], #4
+	it	eq
+	ldreq	r3, [r1], #4
+	beq	1f
+
+	/* Although s1 and s2 have identical initial alignment, they are
+	 * not currently word aligned.  Rather than comparing bytes,
+	 * make sure that any bytes fetched from before the addressed
+	 * bytes are forced to 0xff.  Then they will always compare
+	 * equal.
+	 */
+	eor	r2, r2, #3
+	lsl	r2, r2, #3
+	mvn	r3, #MSB
+	SHFT2LSB	r2, r3, r2
+	ldr	r3, [r1], #4
+	orr	ip, ip, r2
+	orr	r3, r3, r2
+1:
+	/* Load the 'magic' constant 0x01010101. */
+	str	r4, [sp, #-4]!
+	mov	r4, #1
+	orr	r4, r4, r4, lsl #8
+	orr	r4, r4, r4, lsl #16
+	.p2align	2
+4:
+	PLD(r0, #8)
+	PLD(r1, #8)
+	sub	r2, ip, magic1(r4)
+	cmp	ip, r3
+	itttt	eq
+
+	/* check for any zero bytes in first word */
+	biceq	r2, r2, ip
+	tsteq	r2, magic2(r4)
+	ldreq	ip, [r0], #4
+	ldreq	r3, [r1], #4
+	beq	4b
+2:
+	/* There's a zero or a different byte in the word */
+	SHFT2MSB	r0, ip, #24
+	SHFT2LSB	ip, ip, #8
+	cmp	r0, #1
+	it	cs
+	cmpcs	r0, r3, SHFT2MSB #24
+	it	eq
+	SHFT2LSBEQ r3, r3, #8
+	beq	2b
+	/* On a big-endian machine, r0 contains the desired byte in bits
+	 * 0-7; on a little-endian machine they are in bits 24-31.  In
+	 * both cases the other bits in r0 are all zero.  For r3 the
+	 * interesting byte is at the other end of the word, but the
+	 * other bits are not necessarily zero.  We need a signed result
+	 * representing the differnece in the unsigned bytes, so for the
+	 * little-endian case we can't just shift the interesting bits up.
+	 */
+#ifdef __ARMEB__
+	sub	r0, r0, r3, lsr #24
+#else
+	and	r3, r3, #255
+	/* No RSB instruction in Thumb2 */
+#ifdef __thumb2__
+	lsr	r0, r0, #24
+	sub	r0, r0, r3
+#else
+	rsb	r0, r3, r0, lsr #24
+#endif
+#endif
+	ldr	r4, [sp], #4
+	bx	lr
+
+.Lstrcmp_unaligned:
+	wp1 .req r0
+	wp2 .req r1
+	b1  .req r2
+	w1  .req r4
+	w2  .req r5
+	t1  .req ip
+	@ r3 is scratch
+
+	/* First of all, compare bytes until wp1(sp1) is word-aligned. */
+1:
+	tst	wp1, #3
+	beq	2f
+	ldrb	r2, [wp1], #1
+	ldrb	r3, [wp2], #1
+	cmp	r2, #1
+	it	cs
+	cmpcs	r2, r3
+	beq	1b
+	sub	r0, r2, r3
+	bx	lr
+
+2:
+	str	r5, [sp, #-4]!
+	str	r4, [sp, #-4]!
+	mov	b1, #1
+	orr	b1, b1, b1, lsl #8
+	orr	b1, b1, b1, lsl #16
+
+	and	t1, wp2, #3
+	bic	wp2, wp2, #3
+	ldr	w1, [wp1], #4
+	ldr	w2, [wp2], #4
+	cmp	t1, #2
+	beq	2f
+	bhi	3f
+
+	/* Critical inner Loop: Block with 3 bytes initial overlap */
+	.p2align	2
+1:
+	bic	t1, w1, #MSB
+	cmp	t1, w2, SHFT2LSB #8
+	sub	r3, w1, b1
+	bic	r3, r3, w1
+	bne	4f
+	ands	r3, r3, b1, lsl #7
+	it	eq
+	ldreq	w2, [wp2], #4
+	bne	5f
+	eor	t1, t1, w1
+	cmp	t1, w2, SHFT2MSB #24
+	bne	6f
+	ldr	w1, [wp1], #4
+	b	1b
+4:
+	SHFT2LSB	w2, w2, #8
+	b	8f
+
+5:
+#ifdef __ARMEB__
+	/* The syndrome value may contain false ones if the string ends
+	 * with the bytes 0x01 0x00
+	 */
+	tst	w1, #0xff000000
+	itt	ne
+	tstne	w1, #0x00ff0000
+	tstne	w1, #0x0000ff00
+	beq	7f
+#else
+	bics	r3, r3, #0xff000000
+	bne	7f
+#endif
+	ldrb	w2, [wp2]
+	SHFT2LSB	t1, w1, #24
+#ifdef __ARMEB__
+	lsl	w2, w2, #24
+#endif
+	b	8f
+
+6:
+	SHFT2LSB	t1, w1, #24
+	and	w2, w2, #LSB
+	b	8f
+
+	/* Critical inner Loop: Block with 2 bytes initial overlap */
+	.p2align	2
+2:
+	SHFT2MSB	t1, w1, #16
+	sub	r3, w1, b1
+	SHFT2LSB	t1, t1, #16
+	bic	r3, r3, w1
+	cmp	t1, w2, SHFT2LSB #16
+	bne	4f
+	ands	r3, r3, b1, lsl #7
+	it	eq
+	ldreq	w2, [wp2], #4
+	bne	5f
+	eor	t1, t1, w1
+	cmp	t1, w2, SHFT2MSB #16
+	bne	6f
+	ldr	w1, [wp1], #4
+	b	2b
+
+5:
+#ifdef __ARMEB__
+	/* The syndrome value may contain false ones if the string ends
+	 * with the bytes 0x01 0x00
+	 */
+	tst	w1, #0xff000000
+	it	ne
+	tstne	w1, #0x00ff0000
+	beq	7f
+#else
+	lsls	r3, r3, #16
+	bne	7f
+#endif
+	ldrh	w2, [wp2]
+	SHFT2LSB	t1, w1, #16
+#ifdef __ARMEB__
+	lsl	w2, w2, #16
+#endif
+	b	8f
+
+6:
+	SHFT2MSB	w2, w2, #16
+	SHFT2LSB	t1, w1, #16
+4:
+	SHFT2LSB	w2, w2, #16
+	b	8f
+
+	/* Critical inner Loop: Block with 1 byte initial overlap */
+	.p2align	2
+3:
+	and	t1, w1, #LSB
+	cmp	t1, w2, SHFT2LSB #24
+	sub	r3, w1, b1
+	bic	r3, r3, w1
+	bne	4f
+	ands	r3, r3, b1, lsl #7
+	it	eq
+	ldreq	w2, [wp2], #4
+	bne	5f
+	eor	t1, t1, w1
+	cmp	t1, w2, SHFT2MSB #8
+	bne	6f
+	ldr	w1, [wp1], #4
+	b	3b
+4:
+	SHFT2LSB	w2, w2, #24
+	b	8f
+5:
+	/* The syndrome value may contain false ones if the string ends
+	 * with the bytes 0x01 0x00
+	 */
+	tst	w1, #LSB
+	beq	7f
+	ldr	w2, [wp2], #4
+6:
+	SHFT2LSB	t1, w1, #8
+	bic	w2, w2, #MSB
+	b	8f
+7:
+	mov	r0, #0
+	ldr	r4, [sp], #4
+	ldr	r5, [sp], #4
+	bx	lr
+
+8:
+	and	r2, t1, #LSB
+	and	r0, w2, #LSB
+	cmp	r0, #1
+	it	cs
+	cmpcs	r0, r2
+	itt	eq
+	SHFT2LSBEQ	t1, t1, #8
+	SHFT2LSBEQ	w2, w2, #8
+	beq	8b
+	sub	r0, r2, r0
+	ldr	r4, [sp], #4
+	ldr	r5, [sp], #4
+	bx	lr
+END(strcmp)

libc/arch-arm/bionic/strcmp.a15.S

@@ -0,0 +1,787 @@
+/*
+ * Copyright (c) 2013 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arm_asm.h"
+
+#ifdef __ARMEB__
+#define S2LOMEM lsl
+#define S2LOMEMEQ lsleq
+#define S2HIMEM lsr
+#define MSB 0x000000ff
+#define LSB 0xff000000
+#define BYTE0_OFFSET 24
+#define BYTE1_OFFSET 16
+#define BYTE2_OFFSET 8
+#define BYTE3_OFFSET 0
+#else /* not  __ARMEB__ */
+#define S2LOMEM lsr
+#define S2LOMEMEQ lsreq
+#define S2HIMEM lsl
+#define BYTE0_OFFSET 0
+#define BYTE1_OFFSET 8
+#define BYTE2_OFFSET 16
+#define BYTE3_OFFSET 24
+#define MSB 0xff000000
+#define LSB 0x000000ff
+#endif /* not  __ARMEB__ */
+
+.syntax         unified
+
+#if defined (__thumb__)
+        .thumb
+        .thumb_func
+#endif
+        .global strcmp
+        .type   strcmp, %function
+strcmp:
+
+#if (defined (__thumb__) && !defined (__thumb2__))
+1:
+        ldrb    r2, [r0]
+        ldrb    r3, [r1]
+        adds    r0, r0, #1
+        adds    r1, r1, #1
+        cmp     r2, #0
+        beq     2f
+        cmp     r2, r3
+        beq     1b
+2:
+        subs    r0, r2, r3
+        bx      lr
+#elif (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
+1:
+        ldrb    r2, [r0], #1
+        ldrb    r3, [r1], #1
+        cmp     r2, #1
+        it      cs
+        cmpcs   r2, r3
+        beq     1b
+        subs    r0, r2, r3
+        RETURN
+
+
+#elif (defined (_ISA_THUMB_2) || defined (_ISA_ARM_6))
+      /* Use LDRD whenever possible.  */
+
+/* The main thing to look out for when comparing large blocks is that
+   the loads do not cross a page boundary when loading past the index
+   of the byte with the first difference or the first string-terminator.
+
+   For example, if the strings are identical and the string-terminator
+   is at index k, byte by byte comparison will not load beyond address
+   s1+k and s2+k; word by word comparison may load up to 3 bytes beyond
+   k; double word - up to 7 bytes.  If the load of these bytes crosses
+   a page boundary, it might cause a memory fault (if the page is not mapped)
+   that would not have happened in byte by byte comparison.
+
+   If an address is (double) word aligned, then a load of a (double) word
+   from that address will not cross a page boundary.
+   Therefore, the algorithm below considers word and double-word alignment
+   of strings separately.  */
+
+/* High-level description of the algorithm.
+
+   * The fast path: if both strings are double-word aligned,
+     use LDRD to load two words from each string in every loop iteration.
+   * If the strings have the same offset from a word boundary,
+     use LDRB to load and compare byte by byte until
+     the first string is aligned to a word boundary (at most 3 bytes).
+     This is optimized for quick return on short unaligned strings.
+   * If the strings have the same offset from a double-word boundary,
+     use LDRD to load two words from each string in every loop iteration, as in the fast path.
+   * If the strings do not have the same offset from a double-word boundary,
+     load a word from the second string before the loop to initialize the queue.
+     Use LDRD to load two words from every string in every loop iteration.
+     Inside the loop, load the second word from the second string only after comparing
+     the first word, using the queued value, to guarantee safety across page boundaries.
+   * If the strings do not have the same offset from a word boundary,
+     use LDR and a shift queue. Order of loads and comparisons matters,
+     similarly to the previous case.
+
+   * Use UADD8 and SEL to compare words, and use REV and CLZ to compute the return value.
+   * The only difference between ARM and Thumb modes is the use of CBZ instruction.
+   * The only difference between big and little endian is the use of REV in little endian
+     to compute the return value, instead of MOV.
+   * No preload. [TODO.]
+*/
+
+        .macro m_cbz reg label
+#ifdef __thumb2__
+        cbz     \reg, \label
+#else   /* not defined __thumb2__ */
+        cmp     \reg, #0
+        beq     \label
+#endif /* not defined __thumb2__ */
+        .endm /* m_cbz */
+
+        .macro m_cbnz reg label
+#ifdef __thumb2__
+        cbnz    \reg, \label
+#else   /* not defined __thumb2__ */
+        cmp     \reg, #0
+        bne     \label
+#endif /* not defined __thumb2__ */
+        .endm /* m_cbnz */
+
+        .macro  init
+        /* Macro to save temporary registers and prepare magic values.  */
+        subs    sp, sp, #16
+        strd    r4, r5, [sp, #8]
+        strd    r6, r7, [sp]
+        mvn     r6, #0  /* all F */
+        mov     r7, #0  /* all 0 */
+        .endm   /* init */
+
+        .macro  magic_compare_and_branch w1 w2 label
+        /* Macro to compare registers w1 and w2 and conditionally branch to label.  */
+        cmp     \w1, \w2        /* Are w1 and w2 the same?  */
+        magic_find_zero_bytes \w1
+        it      eq
+        cmpeq   ip, #0          /* Is there a zero byte in w1?  */
+        bne     \label
+        .endm /* magic_compare_and_branch */
+
+        .macro  magic_find_zero_bytes w1
+        /* Macro to find all-zero bytes in w1, result is in ip.  */
+#if (defined (__ARM_FEATURE_DSP))
+        uadd8   ip, \w1, r6
+        sel     ip, r7, r6
+#else /* not defined (__ARM_FEATURE_DSP) */
+        /* __ARM_FEATURE_DSP is not defined for some Cortex-M processors.
+        Coincidently, these processors only have Thumb-2 mode, where we can use the
+        the (large) magic constant available directly as an immediate in instructions.
+        Note that we cannot use the magic constant in ARM mode, where we need
+        to create the constant in a register.  */
+        sub     ip, \w1, #0x01010101
+        bic     ip, ip, \w1
+        and     ip, ip, #0x80808080
+#endif /* not defined (__ARM_FEATURE_DSP) */
+        .endm /* magic_find_zero_bytes */
+
+        .macro  setup_return w1 w2
+#ifdef __ARMEB__
+        mov     r1, \w1
+        mov     r2, \w2
+#else /* not  __ARMEB__ */
+        rev     r1, \w1
+        rev     r2, \w2
+#endif /* not  __ARMEB__ */
+        .endm /* setup_return */
+
+        /*
+        optpld r0, #0
+        optpld r1, #0
+        */
+
+        /* Are both strings double-word aligned?  */
+        orr     ip, r0, r1
+        tst     ip, #7
+        bne     do_align
+
+        /* Fast path.  */
+        init
+
+doubleword_aligned:
+
+        /* Get here when the strings to compare are double-word aligned.  */
+        /* Compare two words in every iteration.  */
+        .p2align        2
+2:
+        /*
+        optpld r0, #16
+        optpld r1, #16
+        */
+
+        /* Load the next double-word from each string.  */
+        ldrd    r2, r3, [r0], #8
+        ldrd    r4, r5, [r1], #8
+
+        magic_compare_and_branch w1=r2, w2=r4, label=return_24
+        magic_compare_and_branch w1=r3, w2=r5, label=return_35
+        b       2b
+
+do_align:
+        /* Is the first string word-aligned?  */
+        ands    ip, r0, #3
+        beq     word_aligned_r0
+
+        /* Fast compare byte by byte until the first string is word-aligned.  */
+        /* The offset of r0 from a word boundary is in ip. Thus, the number of bytes
+        to read until the next word boudnary is 4-ip.  */
+        bic     r0, r0, #3
+        ldr     r2, [r0], #4
+        lsls    ip, ip, #31
+        beq     byte2
+        bcs     byte3
+
+byte1:
+        ldrb    ip, [r1], #1
+        uxtb    r3, r2, ror #BYTE1_OFFSET
+        subs    ip, r3, ip
+        bne     fast_return
+        m_cbz   reg=r3, label=fast_return
+
+byte2:
+        ldrb    ip, [r1], #1
+        uxtb    r3, r2, ror #BYTE2_OFFSET
+        subs    ip, r3, ip
+        bne     fast_return
+        m_cbz   reg=r3, label=fast_return
+
+byte3:
+        ldrb    ip, [r1], #1
+        uxtb    r3, r2, ror #BYTE3_OFFSET
+        subs    ip, r3, ip
+        bne     fast_return
+        m_cbnz  reg=r3, label=word_aligned_r0
+
+fast_return:
+        mov     r0, ip
+        bx      lr
+
+word_aligned_r0:
+        init
+        /* The first string is word-aligned.  */
+        /* Is the second string word-aligned?  */
+        ands    ip, r1, #3
+        bne     strcmp_unaligned
+
+word_aligned:
+        /* The strings are word-aligned. */
+        /* Is the first string double-word aligned?  */
+        tst     r0, #4
+        beq     doubleword_aligned_r0
+
+        /* If r0 is not double-word aligned yet, align it by loading
+        and comparing the next word from each string.  */
+        ldr     r2, [r0], #4
+        ldr     r4, [r1], #4
+        magic_compare_and_branch w1=r2 w2=r4 label=return_24
+
+doubleword_aligned_r0:
+        /* Get here when r0 is double-word aligned.  */
+        /* Is r1 doubleword_aligned?  */
+        tst     r1, #4
+        beq     doubleword_aligned
+
+        /* Get here when the strings to compare are word-aligned,
+        r0 is double-word aligned, but r1 is not double-word aligned.  */
+
+        /* Initialize the queue.  */
+        ldr     r5, [r1], #4
+
+        /* Compare two words in every iteration.  */
+        .p2align        2
+3:
+        /*
+        optpld r0, #16
+        optpld r1, #16
+        */
+
+        /* Load the next double-word from each string and compare.  */
+        ldrd    r2, r3, [r0], #8
+        magic_compare_and_branch w1=r2 w2=r5 label=return_25
+        ldrd    r4, r5, [r1], #8
+        magic_compare_and_branch w1=r3 w2=r4 label=return_34
+        b       3b
+
+        .macro miscmp_word offsetlo offsethi
+        /* Macro to compare misaligned strings.  */
+        /* r0, r1 are word-aligned, and at least one of the strings
+        is not double-word aligned.  */
+        /* Compare one word in every loop iteration.  */
+        /* OFFSETLO is the original bit-offset of r1 from a word-boundary,
+        OFFSETHI is 32 - OFFSETLO (i.e., offset from the next word).  */
+
+        /* Initialize the shift queue.  */
+        ldr     r5, [r1], #4
+
+        /* Compare one word from each string in every loop iteration.  */
+        .p2align        2
+7:
+        ldr     r3, [r0], #4
+        S2LOMEM r5, r5, #\offsetlo
+        magic_find_zero_bytes w1=r3
+        cmp     r7, ip, S2HIMEM #\offsetlo
+        and     r2, r3, r6, S2LOMEM #\offsetlo
+        it      eq
+        cmpeq   r2, r5
+        bne     return_25
+        ldr     r5, [r1], #4
+        cmp     ip, #0
+        eor r3, r2, r3
+        S2HIMEM r2, r5, #\offsethi
+        it      eq
+        cmpeq   r3, r2
+        bne     return_32
+        b       7b
+        .endm /* miscmp_word */
+
+strcmp_unaligned:
+        /* r0 is word-aligned, r1 is at offset ip from a word.  */
+        /* Align r1 to the (previous) word-boundary.  */
+        bic     r1, r1, #3
+
+        /* Unaligned comparison word by word using LDRs. */
+        cmp     ip, #2
+        beq     miscmp_word_16                    /* If ip == 2.  */
+        bge     miscmp_word_24                    /* If ip == 3.  */
+        miscmp_word offsetlo=8 offsethi=24        /* If ip == 1.  */
+miscmp_word_16:  miscmp_word offsetlo=16 offsethi=16
+miscmp_word_24:  miscmp_word offsetlo=24 offsethi=8
+
+
+return_32:
+        setup_return w1=r3, w2=r2
+        b       do_return
+return_34:
+        setup_return w1=r3, w2=r4
+        b       do_return
+return_25:
+        setup_return w1=r2, w2=r5
+        b       do_return
+return_35:
+        setup_return w1=r3, w2=r5
+        b       do_return
+return_24:
+        setup_return w1=r2, w2=r4
+
+do_return:
+
+#ifdef __ARMEB__
+        mov     r0, ip
+#else /* not  __ARMEB__ */
+        rev     r0, ip
+#endif /* not  __ARMEB__ */
+
+        /* Restore temporaries early, before computing the return value.  */
+        ldrd    r6, r7, [sp]
+        ldrd    r4, r5, [sp, #8]
+        adds    sp, sp, #16
+
+        /* There is a zero or a different byte between r1 and r2.  */
+        /* r0 contains a mask of all-zero bytes in r1.  */
+        /* Using r0 and not ip here because cbz requires low register.  */
+        m_cbz   reg=r0, label=compute_return_value
+        clz     r0, r0
+        /* r0 contains the number of bits on the left of the first all-zero byte in r1.  */
+        rsb     r0, r0, #24
+        /* Here, r0 contains the number of bits on the right of the first all-zero byte in r1.  */
+        lsr     r1, r1, r0
+        lsr     r2, r2, r0
+
+compute_return_value:
+        movs    r0, #1
+        cmp     r1, r2
+        /* The return value is computed as follows.
+        If r1>r2 then (C==1 and Z==0) and LS doesn't hold and r0 is #1 at return.
+        If r1<r2 then (C==0 and Z==0) and we execute SBC with carry_in=0,
+        which means r0:=r0-r0-1 and r0 is #-1 at return.
+        If r1=r2 then (C==1 and Z==1) and we execute SBC with carry_in=1,
+        which means r0:=r0-r0 and r0 is #0 at return.
+        (C==0 and Z==1) cannot happen because the carry bit is "not borrow".  */
+        it      ls
+        sbcls   r0, r0, r0
+        bx      lr
+
+
+#else   /* !(defined (_ISA_THUMB_2) || defined (_ISA_ARM_6)
+             defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) ||
+             (defined (__thumb__) && !defined (__thumb2__))) */
+
+        /* Use LDR whenever possible. */
+
+#ifdef __thumb2__
+#define magic1(REG) 0x01010101
+#define magic2(REG) 0x80808080
+#else
+#define magic1(REG) REG
+#define magic2(REG) REG, lsl #7
+#endif
+
+        optpld  r0
+        optpld  r1
+        eor     r2, r0, r1
+        tst     r2, #3
+        /* Strings not at same byte offset from a word boundary.  */
+        bne     strcmp_unaligned
+        ands    r2, r0, #3
+        bic     r0, r0, #3
+        bic     r1, r1, #3
+        ldr     ip, [r0], #4
+        it      eq
+        ldreq   r3, [r1], #4
+        beq     1f
+        /* Although s1 and s2 have identical initial alignment, they are
+        not currently word aligned.  Rather than comparing bytes,
+    make sure that any bytes fetched from before the addressed
+    bytes are forced to 0xff.  Then they will always compare
+    equal.  */
+        eor     r2, r2, #3
+        lsl     r2, r2, #3
+        mvn     r3, MSB
+        S2LOMEM        r2, r3, r2
+        ldr     r3, [r1], #4
+        orr     ip, ip, r2
+        orr     r3, r3, r2
+1:
+#ifndef __thumb2__
+              /* Load the 'magic' constant 0x01010101.  */
+        str     r4, [sp, #-4]!
+        mov     r4, #1
+        orr     r4, r4, r4, lsl #8
+        orr     r4, r4, r4, lsl #16
+#endif
+        .p2align        2
+4:
+        optpld  r0, #8
+        optpld  r1, #8
+        sub     r2, ip, magic1(r4)
+        cmp     ip, r3
+        itttt   eq
+        /* check for any zero bytes in first word */
+        biceq   r2, r2, ip
+        tsteq   r2, magic2(r4)
+        ldreq   ip, [r0], #4
+        ldreq   r3, [r1], #4
+        beq     4b
+2:
+        /* There's a zero or a different byte in the word */
+        S2HIMEM  r0, ip, #24
+        S2LOMEM  ip, ip, #8
+        cmp     r0, #1
+        it      cs
+        cmpcs   r0, r3, S2HIMEM #24
+        it      eq
+        S2LOMEMEQ r3, r3, #8
+        beq     2b
+        /* On a big-endian machine, r0 contains the desired byte in bits
+        0-7; on a little-endian machine they are in bits 24-31.  In
+        both cases the other bits in r0 are all zero.  For r3 the
+        interesting byte is at the other end of the word, but the
+        other bits are not necessarily zero.  We need a signed result
+        representing the differnece in the unsigned bytes, so for the
+        little-endian case we can't just shift the interesting bits
+        up.  */
+#ifdef __ARMEB__
+        sub     r0, r0, r3, lsr #24
+#else
+        and     r3, r3, #255
+#ifdef __thumb2__
+        /* No RSB instruction in Thumb2 */
+        lsr     r0, r0, #24
+        sub     r0, r0, r3
+#else
+        rsb     r0, r3, r0, lsr #24
+#endif
+#endif
+#ifndef __thumb2__
+        ldr     r4, [sp], #4
+#endif
+        RETURN
+
+
+strcmp_unaligned:
+
+#if 0
+        /* The assembly code below is based on the following alogrithm.  */
+#ifdef __ARMEB__
+#define RSHIFT <<
+#define LSHIFT >>
+#else
+#define RSHIFT >>
+#define LSHIFT <<
+#endif
+
+#define body(shift)                         \
+  mask = 0xffffffffU RSHIFT shift;                  \
+  w1 = *wp1++;                              \
+  w2 = *wp2++;                              \
+  do                                    \
+    {                                   \
+      t1 = w1 & mask;                           \
+      if (__builtin_expect(t1 != w2 RSHIFT shift, 0))           \
+    {                               \
+      w2 RSHIFT= shift;                     \
+      break;                            \
+    }                               \
+      if (__builtin_expect(((w1 - b1) & ~w1) & (b1 << 7), 0))       \
+    {                               \
+      /* See comment in assembler below re syndrome on big-endian */\
+      if ((((w1 - b1) & ~w1) & (b1 << 7)) & mask)           \
+        w2 RSHIFT= shift;                       \
+      else                              \
+        {                               \
+          w2 = *wp2;                        \
+          t1 = w1 RSHIFT (32 - shift);              \
+          w2 = (w2 LSHIFT (32 - shift)) RSHIFT (32 - shift);    \
+        }                               \
+      break;                            \
+    }                               \
+      w2 = *wp2++;                          \
+      t1 ^= w1;                             \
+      if (__builtin_expect(t1 != w2 LSHIFT (32 - shift), 0))        \
+    {                               \
+      t1 = w1 >> (32 - shift);                  \
+      w2 = (w2 << (32 - shift)) RSHIFT (32 - shift);        \
+      break;                            \
+    }                               \
+      w1 = *wp1++;                          \
+    } while (1)
+
+  const unsigned* wp1;
+  const unsigned* wp2;
+  unsigned w1, w2;
+  unsigned mask;
+  unsigned shift;
+  unsigned b1 = 0x01010101;
+  char c1, c2;
+  unsigned t1;
+
+  while (((unsigned) s1) & 3)
+    {
+      c1 = *s1++;
+      c2 = *s2++;
+      if (c1 == 0 || c1 != c2)
+    return c1 - (int)c2;
+    }
+  wp1 = (unsigned*) (((unsigned)s1) & ~3);
+  wp2 = (unsigned*) (((unsigned)s2) & ~3);
+  t1 = ((unsigned) s2) & 3;
+  if (t1 == 1)
+    {
+      body(8);
+    }
+  else if (t1 == 2)
+    {
+      body(16);
+    }
+  else
+    {
+      body (24);
+    }
+
+  do
+    {
+#ifdef __ARMEB__
+      c1 = (char) t1 >> 24;
+      c2 = (char) w2 >> 24;
+#else /* not  __ARMEB__ */
+      c1 = (char) t1;
+      c2 = (char) w2;
+#endif /* not  __ARMEB__ */
+      t1 RSHIFT= 8;
+      w2 RSHIFT= 8;
+    } while (c1 != 0 && c1 == c2);
+  return c1 - c2;
+#endif /* 0 */
+
+
+        wp1 .req r0
+        wp2 .req r1
+        b1  .req r2
+        w1  .req r4
+        w2  .req r5
+        t1  .req ip
+        @ r3 is scratch
+
+        /* First of all, compare bytes until wp1(sp1) is word-aligned. */
+1:
+        tst     wp1, #3
+        beq     2f
+        ldrb    r2, [wp1], #1
+        ldrb    r3, [wp2], #1
+        cmp     r2, #1
+        it      cs
+        cmpcs   r2, r3
+        beq     1b
+        sub     r0, r2, r3
+        RETURN
+
+2:
+        str     r5, [sp, #-4]!
+        str     r4, [sp, #-4]!
+        //stmfd   sp!, {r4, r5}
+        mov     b1, #1
+        orr     b1, b1, b1, lsl #8
+        orr     b1, b1, b1, lsl #16
+
+        and     t1, wp2, #3
+        bic     wp2, wp2, #3
+        ldr     w1, [wp1], #4
+        ldr     w2, [wp2], #4
+        cmp     t1, #2
+        beq     2f
+        bhi     3f
+
+        /* Critical inner Loop: Block with 3 bytes initial overlap */
+        .p2align        2
+1:
+        bic     t1, w1, MSB
+        cmp     t1, w2, S2LOMEM #8
+        sub     r3, w1, b1
+        bic     r3, r3, w1
+        bne     4f
+        ands    r3, r3, b1, lsl #7
+        it      eq
+        ldreq   w2, [wp2], #4
+        bne     5f
+        eor     t1, t1, w1
+        cmp     t1, w2, S2HIMEM #24
+        bne     6f
+        ldr     w1, [wp1], #4
+        b       1b
+4:
+        S2LOMEM        w2, w2, #8
+        b       8f
+
+5:
+#ifdef __ARMEB__
+        /* The syndrome value may contain false ones if the string ends
+        with the bytes 0x01 0x00 */
+        tst     w1, #0xff000000
+        itt     ne
+        tstne   w1, #0x00ff0000
+        tstne   w1, #0x0000ff00
+        beq     7f
+#else
+        bics    r3, r3, #0xff000000
+        bne     7f
+#endif
+        ldrb    w2, [wp2]
+        S2LOMEM  t1, w1, #24
+#ifdef __ARMEB__
+        lsl     w2, w2, #24
+#endif
+        b       8f
+
+6:
+        S2LOMEM  t1, w1, #24
+        and     w2, w2, LSB
+        b       8f
+
+        /* Critical inner Loop: Block with 2 bytes initial overlap */
+        .p2align        2
+2:
+        S2HIMEM  t1, w1, #16
+        sub     r3, w1, b1
+        S2LOMEM  t1, t1, #16
+        bic     r3, r3, w1
+        cmp     t1, w2, S2LOMEM #16
+        bne     4f
+        ands    r3, r3, b1, lsl #7
+        it      eq
+        ldreq   w2, [wp2], #4
+        bne     5f
+        eor     t1, t1, w1
+        cmp     t1, w2, S2HIMEM #16
+        bne     6f
+        ldr     w1, [wp1], #4
+        b       2b
+
+5:
+#ifdef __ARMEB__
+        /* The syndrome value may contain false ones if the string ends
+        with the bytes 0x01 0x00 */
+        tst     w1, #0xff000000
+        it      ne
+        tstne   w1, #0x00ff0000
+        beq     7f
+#else
+        lsls    r3, r3, #16
+        bne     7f
+#endif
+        ldrh    w2, [wp2]
+        S2LOMEM  t1, w1, #16
+#ifdef __ARMEB__
+        lsl     w2, w2, #16
+#endif
+        b       8f
+
+6:
+        S2HIMEM  w2, w2, #16
+        S2LOMEM  t1, w1, #16
+4:
+        S2LOMEM  w2, w2, #16
+        b       8f
+
+        /* Critical inner Loop: Block with 1 byte initial overlap */
+        .p2align        2
+3:
+        and     t1, w1, LSB
+        cmp     t1, w2, S2LOMEM #24
+        sub     r3, w1, b1
+        bic     r3, r3, w1
+        bne     4f
+        ands    r3, r3, b1, lsl #7
+        it      eq
+        ldreq   w2, [wp2], #4
+        bne     5f
+        eor     t1, t1, w1
+        cmp     t1, w2, S2HIMEM #8
+        bne     6f
+        ldr     w1, [wp1], #4
+        b       3b
+4:
+        S2LOMEM  w2, w2, #24
+        b       8f
+5:
+        /* The syndrome value may contain false ones if the string ends
+        with the bytes 0x01 0x00 */
+        tst     w1, LSB
+        beq     7f
+        ldr     w2, [wp2], #4
+6:
+        S2LOMEM  t1, w1, #8
+        bic     w2, w2, MSB
+        b       8f
+7:
+        mov     r0, #0
+        //ldmfd   sp!, {r4, r5}
+        ldr     r4, [sp], #4
+        ldr     r5, [sp], #4
+        RETURN
+8:
+        and     r2, t1, LSB
+        and     r0, w2, LSB
+        cmp     r0, #1
+        it      cs
+        cmpcs   r0, r2
+        itt     eq
+        S2LOMEMEQ        t1, t1, #8
+        S2LOMEMEQ        w2, w2, #8
+        beq     8b
+        sub     r0, r2, r0
+        //ldmfd   sp!, {r4, r5}
+        ldr     r4, [sp], #4
+        ldr     r5, [sp], #4
+        RETURN
+
+#endif /* !(defined (_ISA_THUMB_2) || defined (_ISA_ARM_6)
+            defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) ||
+            (defined (__thumb__) && !defined (__thumb2__))) */

libc/arch-arm/bionic/strcpy.S

@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2010 The Android Open Source Project
+ * Copyright (c) 2008 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Android adaptation and tweak by Jim Huang <jserv@0xlab.org>.
+ */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+ENTRY(strcpy)
+	PLD(r1, #0)
+	eor	r2, r0, r1
+	mov	ip, r0
+	tst	r2, #3
+	bne	4f
+	tst	r1, #3
+	bne	3f
+5:
+	str	r5, [sp, #-4]!
+	mov	r5, #0x01
+	orr	r5, r5, r5, lsl #8
+	orr	r5, r5, r5, lsl #16
+
+	str	r4, [sp, #-4]!
+	tst	r1, #4
+	ldr	r3, [r1], #4
+	beq	2f
+	sub	r2, r3, r5
+	bics	r2, r2, r3
+	tst	r2, r5, lsl #7
+	itt	eq
+	streq	r3, [ip], #4
+	ldreq	r3, [r1], #4
+	bne	1f
+       /* Inner loop.  We now know that r1 is 64-bit aligned, so we
+	  can safely fetch up to two words.  This allows us to avoid
+	  load stalls.  */
+	.p2align 2
+2:
+	PLD(r1, #8)
+	ldr	r4, [r1], #4
+	sub	r2, r3, r5
+	bics	r2, r2, r3
+	tst	r2, r5, lsl #7
+	sub	r2, r4, r5
+	bne	1f
+	str	r3, [ip], #4
+	bics	r2, r2, r4
+	tst	r2, r5, lsl #7
+	itt	eq
+	ldreq	r3, [r1], #4
+	streq	r4, [ip], #4
+	beq	2b
+	mov	r3, r4
+1:
+#ifdef __ARMEB__
+	rors	r3, r3, #24
+#endif
+	strb	r3, [ip], #1
+	tst	r3, #0xff
+#ifdef __ARMEL__
+	ror	r3, r3, #8
+#endif
+	bne	1b
+	ldr	r4, [sp], #4
+	ldr	r5, [sp], #4
+	bx	lr
+
+       /* Strings have the same offset from word alignment, but it's
+	  not zero.  */
+3:
+	tst	r1, #1
+	beq	1f
+	ldrb	r2, [r1], #1
+	strb	r2, [ip], #1
+	cmp	r2, #0
+	it	eq
+	bxeq	lr
+1:
+	tst	r1, #2
+	beq	5b
+	ldrh	r2, [r1], #2
+#ifdef __ARMEB__
+	tst	r2, #0xff00
+	iteet	ne
+	strneh	r2, [ip], #2
+	lsreq	r2, r2, #8
+	streqb	r2, [ip]
+	tstne	r2, #0xff
+#else
+	tst	r2, #0xff
+	itet	ne
+	strneh	r2, [ip], #2
+	streqb	r2, [ip]
+	tstne	r2, #0xff00
+#endif
+	bne	5b
+	bx	lr
+
+       /* src and dst do not have a common word-alignement.  Fall back to
+	  byte copying.  */
+4:
+	ldrb	r2, [r1], #1
+	strb	r2, [ip], #1
+	cmp	r2, #0
+	bne	4b
+	bx	lr
+END(strcpy)

libc/arch-arm/bionic/syscall.S

@@ -25,47 +25,22 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
-#include <sys/linux-syscalls.h>
 
+#include <linux/err.h>
+#include <machine/asm.h>
 
-	.text
-	.align 4
-	.type syscall,#function
-	.globl syscall
- 
-	.text
-	.align
-
-#if __ARM_EABI__
-
-syscall:
+ENTRY(syscall)
     mov     ip, sp
-    stmfd	sp!, {r4, r5, r6, r7}
+    stmfd   sp!, {r4, r5, r6, r7}
     mov     r7, r0
     mov     r0, r1
     mov     r1, r2
     mov     r2, r3
-    ldmfd	ip, {r3, r4, r5, r6}
+    ldmfd   ip, {r3, r4, r5, r6}
     swi     #0
     ldmfd   sp!, {r4, r5, r6, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-
-#else
-
-#ifndef __NR_syscall
-#define __NR_syscall    113
-#endif
-
-syscall:
-    stmfd   sp!, {r4, r5, lr}
-    ldr     r4, [sp, #12]
-    ldr     r5, [sp, #16]
-    swi     __NR_syscall
-    ldmfd   sp!, {r4, r5, lr}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-
-#endif
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(syscall)

libc/arch-arm/bionic/tgkill.S

@@ -25,26 +25,26 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
-#ifndef _ANDROID_BIONIC_LOGD_H
-#define _ANDROID_BIONIC_LOGD_H
 
-#include <stdarg.h>
+#include <linux/err.h>
+#include <asm/unistd.h>
+#include <machine/asm.h>
 
-enum  {
-    ANDROID_LOG_UNKNOWN = 0,
-    ANDROID_LOG_DEFAULT,    /* only for SetMinPriority() */
+/* unlike our auto-generated syscall stubs, this code saves lr
+   on the stack, as well as a few other registers. this makes
+   our stack unwinder happy, when we generate debug stack
+   traces after the C library or other parts of the system
+   abort due to a fatal runtime error (e.g. detection
+   of a corrupted malloc heap).
+*/
 
-    ANDROID_LOG_VERBOSE,
-    ANDROID_LOG_DEBUG,
-    ANDROID_LOG_INFO,
-    ANDROID_LOG_WARN,
-    ANDROID_LOG_ERROR,
-    ANDROID_LOG_FATAL,
-
-    ANDROID_LOG_SILENT,     /* only for SetMinPriority(); must be last */
-};
-
-int __libc_android_log_print(int prio, const char *tag, const char *fmt, ...);
-int __libc_android_log_vprint(int prio, const char *tag, const char *fmt, va_list ap);
-
-#endif /* _ANDROID_BIONIC_LOGD_H */
+ENTRY(tgkill)
+    stmfd   sp!, {r4-r7, ip, lr}
+    ldr     r7, =__NR_tgkill
+    swi     #0
+    ldmfd   sp!, {r4-r7, ip, lr}
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(tgkill)

libc/arch-arm/bionic/tkill.S

@@ -25,6 +25,11 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
+
+#include <linux/err.h>
+#include <asm/unistd.h>
+#include <machine/asm.h>
+
 /* unlike our auto-generated syscall stubs, this code saves lr
    on the stack, as well as a few other registers. this makes
    our stack unwinder happy, when we generate debug stack
@@ -32,22 +37,14 @@
    abort due to a fatal runtime error (e.g. detection
    of a corrupted malloc heap).
 */
-#include <sys/linux-syscalls.h>
 
-#ifndef __NR_tkill
-#define __NR_tkill  238
-#endif
-
-    .text
-    .type tkill, #function
-    .globl tkill
-    .align 4
-
-tkill:
+ENTRY(tkill)
     stmfd   sp!, {r4-r7, ip, lr}
     ldr     r7, =__NR_tkill
     swi     #0
     ldmfd   sp!, {r4-r7, ip, lr}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(tkill)

libc/arch-arm/cortex-a15/bionic/memcpy.S

@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2008 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* Assumes neon instructions and a cache line size of 64 bytes. */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+/*
+ * This code assumes it is running on a processor that supports all arm v7
+ * instructions, that supports neon instructions, and that has a 64 byte
+ * cache line.
+ */
+
+        .text
+        .fpu    neon
+
+#define CACHE_LINE_SIZE     64
+
+ENTRY(memcpy)
+        .save       {r0, lr}
+        /* start preloading as early as possible */
+        pld         [r1, #(CACHE_LINE_SIZE*0)]
+        stmfd       sp!, {r0, lr}
+        pld         [r1, #(CACHE_LINE_SIZE*1)]
+
+        /* do we have at least 16-bytes to copy (needed for alignment below) */
+        cmp         r2, #16
+        blo         5f
+
+        /* align destination to cache-line for the write-buffer */
+        rsb         r3, r0, #0
+        ands        r3, r3, #0xF
+        beq         0f
+
+        /* copy up to 15-bytes (count in r3) */
+        sub         r2, r2, r3
+        movs        ip, r3, lsl #31
+        ldrmib      lr, [r1], #1
+        strmib      lr, [r0], #1
+        ldrcsb      ip, [r1], #1
+        ldrcsb      lr, [r1], #1
+        strcsb      ip, [r0], #1
+        strcsb      lr, [r0], #1
+        movs        ip, r3, lsl #29
+        bge         1f
+        // copies 4 bytes, destination 32-bits aligned
+        vld4.8      {d0[0], d1[0], d2[0], d3[0]}, [r1]!
+        vst4.8      {d0[0], d1[0], d2[0], d3[0]}, [r0, :32]!
+1:      bcc         2f
+        // copies 8 bytes, destination 64-bits aligned
+        vld1.8      {d0}, [r1]!
+        vst1.8      {d0}, [r0, :64]!
+2:
+
+0:      /* preload immediately the next cache line, which we may need */
+        pld         [r1, #(CACHE_LINE_SIZE*0)]
+        pld         [r1, #(CACHE_LINE_SIZE*1)]
+
+        /* make sure we have at least 64 bytes to copy */
+        subs        r2, r2, #64
+        blo         2f
+
+        /* Preload all the cache lines we need.
+         * NOTE: The number of pld below depends on CACHE_LINE_SIZE,
+         * ideally we would increase the distance in the main loop to
+         * avoid the goofy code below. In practice this doesn't seem to make
+         * a big difference.
+         * NOTE: The value CACHE_LINE_SIZE * 4 was chosen through
+         * experimentation.
+         */
+        pld         [r1, #(CACHE_LINE_SIZE*2)]
+        pld         [r1, #(CACHE_LINE_SIZE*3)]
+        pld         [r1, #(CACHE_LINE_SIZE*4)]
+
+1:      /* The main loop copies 64 bytes at a time */
+        vld1.8      {d0  - d3},   [r1]!
+        vld1.8      {d4  - d7},   [r1]!
+        pld         [r1, #(CACHE_LINE_SIZE*4)]
+        subs        r2, r2, #64
+        vst1.8      {d0  - d3},   [r0, :128]!
+        vst1.8      {d4  - d7},   [r0, :128]!
+        bhs         1b
+
+2:      /* fix-up the remaining count and make sure we have >= 32 bytes left */
+        add         r2, r2, #64
+        subs        r2, r2, #32
+        blo         4f
+
+3:      /* 32 bytes at a time. These cache lines were already preloaded */
+        vld1.8      {d0 - d3},  [r1]!
+        subs        r2, r2, #32
+        vst1.8      {d0 - d3},  [r0, :128]!
+        bhs         3b
+4:      /* less than 32 left */
+        add         r2, r2, #32
+        tst         r2, #0x10
+        beq         5f
+        // copies 16 bytes, 128-bits aligned
+        vld1.8      {d0, d1}, [r1]!
+        vst1.8      {d0, d1}, [r0, :128]!
+
+5:      /* copy up to 15-bytes (count in r2) */
+        movs        ip, r2, lsl #29
+        bcc         1f
+        vld1.8      {d0}, [r1]!
+        vst1.8      {d0}, [r0]!
+1:      bge         2f
+        vld4.8      {d0[0], d1[0], d2[0], d3[0]}, [r1]!
+        vst4.8      {d0[0], d1[0], d2[0], d3[0]}, [r0]!
+2:      movs        ip, r2, lsl #31
+        ldrmib      r3, [r1], #1
+        ldrcsb      ip, [r1], #1
+        ldrcsb      lr, [r1], #1
+        strmib      r3, [r0], #1
+        strcsb      ip, [r0], #1
+        strcsb      lr, [r0], #1
+
+        ldmfd       sp!, {r0, lr}
+        bx          lr
+END(memcpy)

libc/arch-arm/cortex-a15/bionic/memset.S

@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2008 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+		/*
+		 * Optimized memset() for ARM.
+         *
+         * memset() returns its first argument.
+		 */
+
+    .fpu    neon
+
+ENTRY(bzero)
+        mov     r2, r1
+        mov     r1, #0
+        // Fall through to memset...
+END(bzero)
+
+ENTRY(memset)
+        .save       {r0}
+        stmfd       sp!, {r0}
+
+        vdup.8      q0, r1
+
+        /* do we have at least 16-bytes to write (needed for alignment below) */
+        cmp         r2, #16
+        blo         3f
+
+        /* align destination to 16 bytes for the write-buffer */
+        rsb         r3, r0, #0
+        ands        r3, r3, #0xF
+        beq         2f
+
+        /* write up to 15-bytes (count in r3) */
+        sub         r2, r2, r3
+        movs        ip, r3, lsl #31
+        strmib      r1, [r0], #1
+        strcsb      r1, [r0], #1
+        strcsb      r1, [r0], #1
+        movs        ip, r3, lsl #29
+        bge         1f
+
+        // writes 4 bytes, 32-bits aligned
+        vst1.32     {d0[0]}, [r0, :32]!
+1:      bcc         2f
+
+        // writes 8 bytes, 64-bits aligned
+        vst1.8      {d0}, [r0, :64]!
+2:
+        /* make sure we have at least 32 bytes to write */
+        subs        r2, r2, #32
+        blo         2f
+        vmov        q1, q0
+
+1:      /* The main loop writes 32 bytes at a time */
+        subs        r2, r2, #32
+        vst1.8      {d0 - d3}, [r0, :128]!
+        bhs         1b
+
+2:      /* less than 32 left */
+        add         r2, r2, #32
+        tst         r2, #0x10
+        beq         3f
+
+        // writes 16 bytes, 128-bits aligned
+        vst1.8      {d0, d1}, [r0, :128]!
+3:      /* write up to 15-bytes (count in r2) */
+        movs        ip, r2, lsl #29
+        bcc         1f
+        vst1.8      {d0}, [r0]!
+1:      bge         2f
+        vst1.32     {d0[0]}, [r0]!
+2:      movs        ip, r2, lsl #31
+        strmib      r1, [r0], #1
+        strcsb      r1, [r0], #1
+        strcsb      r1, [r0], #1
+        ldmfd       sp!, {r0}
+        bx          lr
+END(memset)

libc/arch-arm/cortex-a15/bionic/strcmp.S

@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2013 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+#ifdef __ARMEB__
+#define S2LOMEM lsl
+#define S2LOMEMEQ lsleq
+#define S2HIMEM lsr
+#define MSB 0x000000ff
+#define LSB 0xff000000
+#define BYTE0_OFFSET 24
+#define BYTE1_OFFSET 16
+#define BYTE2_OFFSET 8
+#define BYTE3_OFFSET 0
+#else /* not  __ARMEB__ */
+#define S2LOMEM lsr
+#define S2LOMEMEQ lsreq
+#define S2HIMEM lsl
+#define BYTE0_OFFSET 0
+#define BYTE1_OFFSET 8
+#define BYTE2_OFFSET 16
+#define BYTE3_OFFSET 24
+#define MSB 0xff000000
+#define LSB 0x000000ff
+#endif /* not  __ARMEB__ */
+
+.syntax         unified
+
+#if defined (__thumb__)
+        .thumb
+        .thumb_func
+#endif
+
+ENTRY(strcmp)
+      /* Use LDRD whenever possible.  */
+
+/* The main thing to look out for when comparing large blocks is that
+   the loads do not cross a page boundary when loading past the index
+   of the byte with the first difference or the first string-terminator.
+
+   For example, if the strings are identical and the string-terminator
+   is at index k, byte by byte comparison will not load beyond address
+   s1+k and s2+k; word by word comparison may load up to 3 bytes beyond
+   k; double word - up to 7 bytes.  If the load of these bytes crosses
+   a page boundary, it might cause a memory fault (if the page is not mapped)
+   that would not have happened in byte by byte comparison.
+
+   If an address is (double) word aligned, then a load of a (double) word
+   from that address will not cross a page boundary.
+   Therefore, the algorithm below considers word and double-word alignment
+   of strings separately.  */
+
+/* High-level description of the algorithm.
+
+   * The fast path: if both strings are double-word aligned,
+     use LDRD to load two words from each string in every loop iteration.
+   * If the strings have the same offset from a word boundary,
+     use LDRB to load and compare byte by byte until
+     the first string is aligned to a word boundary (at most 3 bytes).
+     This is optimized for quick return on short unaligned strings.
+   * If the strings have the same offset from a double-word boundary,
+     use LDRD to load two words from each string in every loop iteration, as in the fast path.
+   * If the strings do not have the same offset from a double-word boundary,
+     load a word from the second string before the loop to initialize the queue.
+     Use LDRD to load two words from every string in every loop iteration.
+     Inside the loop, load the second word from the second string only after comparing
+     the first word, using the queued value, to guarantee safety across page boundaries.
+   * If the strings do not have the same offset from a word boundary,
+     use LDR and a shift queue. Order of loads and comparisons matters,
+     similarly to the previous case.
+
+   * Use UADD8 and SEL to compare words, and use REV and CLZ to compute the return value.
+   * The only difference between ARM and Thumb modes is the use of CBZ instruction.
+   * The only difference between big and little endian is the use of REV in little endian
+     to compute the return value, instead of MOV.
+*/
+
+        .macro m_cbz reg label
+#ifdef __thumb2__
+        cbz     \reg, \label
+#else   /* not defined __thumb2__ */
+        cmp     \reg, #0
+        beq     \label
+#endif /* not defined __thumb2__ */
+        .endm /* m_cbz */
+
+        .macro m_cbnz reg label
+#ifdef __thumb2__
+        cbnz    \reg, \label
+#else   /* not defined __thumb2__ */
+        cmp     \reg, #0
+        bne     \label
+#endif /* not defined __thumb2__ */
+        .endm /* m_cbnz */
+
+        .macro  init
+        /* Macro to save temporary registers and prepare magic values.  */
+        subs    sp, sp, #16
+        strd    r4, r5, [sp, #8]
+        strd    r6, r7, [sp]
+        mvn     r6, #0  /* all F */
+        mov     r7, #0  /* all 0 */
+        .endm   /* init */
+
+        .macro  magic_compare_and_branch w1 w2 label
+        /* Macro to compare registers w1 and w2 and conditionally branch to label.  */
+        cmp     \w1, \w2        /* Are w1 and w2 the same?  */
+        magic_find_zero_bytes \w1
+        it      eq
+        cmpeq   ip, #0          /* Is there a zero byte in w1?  */
+        bne     \label
+        .endm /* magic_compare_and_branch */
+
+        .macro  magic_find_zero_bytes w1
+        /* Macro to find all-zero bytes in w1, result is in ip.  */
+#if (defined (__ARM_FEATURE_DSP))
+        uadd8   ip, \w1, r6
+        sel     ip, r7, r6
+#else /* not defined (__ARM_FEATURE_DSP) */
+        /* __ARM_FEATURE_DSP is not defined for some Cortex-M processors.
+        Coincidently, these processors only have Thumb-2 mode, where we can use the
+        the (large) magic constant available directly as an immediate in instructions.
+        Note that we cannot use the magic constant in ARM mode, where we need
+        to create the constant in a register.  */
+        sub     ip, \w1, #0x01010101
+        bic     ip, ip, \w1
+        and     ip, ip, #0x80808080
+#endif /* not defined (__ARM_FEATURE_DSP) */
+        .endm /* magic_find_zero_bytes */
+
+        .macro  setup_return w1 w2
+#ifdef __ARMEB__
+        mov     r1, \w1
+        mov     r2, \w2
+#else /* not  __ARMEB__ */
+        rev     r1, \w1
+        rev     r2, \w2
+#endif /* not  __ARMEB__ */
+        .endm /* setup_return */
+
+        pld [r0, #0]
+        pld [r1, #0]
+
+        /* Are both strings double-word aligned?  */
+        orr     ip, r0, r1
+        tst     ip, #7
+        bne     do_align
+
+        /* Fast path.  */
+        init
+
+doubleword_aligned:
+
+        /* Get here when the strings to compare are double-word aligned.  */
+        /* Compare two words in every iteration.  */
+        .p2align        2
+2:
+        pld [r0, #16]
+        pld [r1, #16]
+
+        /* Load the next double-word from each string.  */
+        ldrd    r2, r3, [r0], #8
+        ldrd    r4, r5, [r1], #8
+
+        magic_compare_and_branch w1=r2, w2=r4, label=return_24
+        magic_compare_and_branch w1=r3, w2=r5, label=return_35
+        b       2b
+
+do_align:
+        /* Is the first string word-aligned?  */
+        ands    ip, r0, #3
+        beq     word_aligned_r0
+
+        /* Fast compare byte by byte until the first string is word-aligned.  */
+        /* The offset of r0 from a word boundary is in ip. Thus, the number of bytes
+        to read until the next word boundary is 4-ip.  */
+        bic     r0, r0, #3
+        ldr     r2, [r0], #4
+        lsls    ip, ip, #31
+        beq     byte2
+        bcs     byte3
+
+byte1:
+        ldrb    ip, [r1], #1
+        uxtb    r3, r2, ror #BYTE1_OFFSET
+        subs    ip, r3, ip
+        bne     fast_return
+        m_cbz   reg=r3, label=fast_return
+
+byte2:
+        ldrb    ip, [r1], #1
+        uxtb    r3, r2, ror #BYTE2_OFFSET
+        subs    ip, r3, ip
+        bne     fast_return
+        m_cbz   reg=r3, label=fast_return
+
+byte3:
+        ldrb    ip, [r1], #1
+        uxtb    r3, r2, ror #BYTE3_OFFSET
+        subs    ip, r3, ip
+        bne     fast_return
+        m_cbnz  reg=r3, label=word_aligned_r0
+
+fast_return:
+        mov     r0, ip
+        bx      lr
+
+word_aligned_r0:
+        init
+        /* The first string is word-aligned.  */
+        /* Is the second string word-aligned?  */
+        ands    ip, r1, #3
+        bne     strcmp_unaligned
+
+word_aligned:
+        /* The strings are word-aligned. */
+        /* Is the first string double-word aligned?  */
+        tst     r0, #4
+        beq     doubleword_aligned_r0
+
+        /* If r0 is not double-word aligned yet, align it by loading
+        and comparing the next word from each string.  */
+        ldr     r2, [r0], #4
+        ldr     r4, [r1], #4
+        magic_compare_and_branch w1=r2 w2=r4 label=return_24
+
+doubleword_aligned_r0:
+        /* Get here when r0 is double-word aligned.  */
+        /* Is r1 doubleword_aligned?  */
+        tst     r1, #4
+        beq     doubleword_aligned
+
+        /* Get here when the strings to compare are word-aligned,
+        r0 is double-word aligned, but r1 is not double-word aligned.  */
+
+        /* Initialize the queue.  */
+        ldr     r5, [r1], #4
+
+        /* Compare two words in every iteration.  */
+        .p2align        2
+3:
+        pld [r0, #16]
+        pld [r1, #16]
+
+        /* Load the next double-word from each string and compare.  */
+        ldrd    r2, r3, [r0], #8
+        magic_compare_and_branch w1=r2 w2=r5 label=return_25
+        ldrd    r4, r5, [r1], #8
+        magic_compare_and_branch w1=r3 w2=r4 label=return_34
+        b       3b
+
+        .macro miscmp_word offsetlo offsethi
+        /* Macro to compare misaligned strings.  */
+        /* r0, r1 are word-aligned, and at least one of the strings
+        is not double-word aligned.  */
+        /* Compare one word in every loop iteration.  */
+        /* OFFSETLO is the original bit-offset of r1 from a word-boundary,
+        OFFSETHI is 32 - OFFSETLO (i.e., offset from the next word).  */
+
+        /* Initialize the shift queue.  */
+        ldr     r5, [r1], #4
+
+        /* Compare one word from each string in every loop iteration.  */
+        .p2align        2
+7:
+        ldr     r3, [r0], #4
+        S2LOMEM r5, r5, #\offsetlo
+        magic_find_zero_bytes w1=r3
+        cmp     r7, ip, S2HIMEM #\offsetlo
+        and     r2, r3, r6, S2LOMEM #\offsetlo
+        it      eq
+        cmpeq   r2, r5
+        bne     return_25
+        ldr     r5, [r1], #4
+        cmp     ip, #0
+        eor r3, r2, r3
+        S2HIMEM r2, r5, #\offsethi
+        it      eq
+        cmpeq   r3, r2
+        bne     return_32
+        b       7b
+        .endm /* miscmp_word */
+
+strcmp_unaligned:
+        /* r0 is word-aligned, r1 is at offset ip from a word.  */
+        /* Align r1 to the (previous) word-boundary.  */
+        bic     r1, r1, #3
+
+        /* Unaligned comparison word by word using LDRs. */
+        cmp     ip, #2
+        beq     miscmp_word_16                    /* If ip == 2.  */
+        bge     miscmp_word_24                    /* If ip == 3.  */
+        miscmp_word offsetlo=8 offsethi=24        /* If ip == 1.  */
+miscmp_word_16:  miscmp_word offsetlo=16 offsethi=16
+miscmp_word_24:  miscmp_word offsetlo=24 offsethi=8
+
+
+return_32:
+        setup_return w1=r3, w2=r2
+        b       do_return
+return_34:
+        setup_return w1=r3, w2=r4
+        b       do_return
+return_25:
+        setup_return w1=r2, w2=r5
+        b       do_return
+return_35:
+        setup_return w1=r3, w2=r5
+        b       do_return
+return_24:
+        setup_return w1=r2, w2=r4
+
+do_return:
+
+#ifdef __ARMEB__
+        mov     r0, ip
+#else /* not  __ARMEB__ */
+        rev     r0, ip
+#endif /* not  __ARMEB__ */
+
+        /* Restore temporaries early, before computing the return value.  */
+        ldrd    r6, r7, [sp]
+        ldrd    r4, r5, [sp, #8]
+        adds    sp, sp, #16
+
+        /* There is a zero or a different byte between r1 and r2.  */
+        /* r0 contains a mask of all-zero bytes in r1.  */
+        /* Using r0 and not ip here because cbz requires low register.  */
+        m_cbz   reg=r0, label=compute_return_value
+        clz     r0, r0
+        /* r0 contains the number of bits on the left of the first all-zero byte in r1.  */
+        rsb     r0, r0, #24
+        /* Here, r0 contains the number of bits on the right of the first all-zero byte in r1.  */
+        lsr     r1, r1, r0
+        lsr     r2, r2, r0
+
+compute_return_value:
+        movs    r0, #1
+        cmp     r1, r2
+        /* The return value is computed as follows.
+        If r1>r2 then (C==1 and Z==0) and LS doesn't hold and r0 is #1 at return.
+        If r1<r2 then (C==0 and Z==0) and we execute SBC with carry_in=0,
+        which means r0:=r0-r0-1 and r0 is #-1 at return.
+        If r1=r2 then (C==1 and Z==1) and we execute SBC with carry_in=1,
+        which means r0:=r0-r0 and r0 is #0 at return.
+        (C==0 and Z==1) cannot happen because the carry bit is "not borrow".  */
+        it      ls
+        sbcls   r0, r0, r0
+        bx      lr
+END(strcmp)

libc/arch-arm/cortex-a15/cortex-a15.mk

@@ -0,0 +1,5 @@
+$(call libc-add-cpu-variant-src,MEMCPY,arch-arm/cortex-a15/bionic/memcpy.S)
+$(call libc-add-cpu-variant-src,MEMSET,arch-arm/cortex-a15/bionic/memset.S)
+$(call libc-add-cpu-variant-src,STRCMP,arch-arm/cortex-a15/bionic/strcmp.S)
+
+include bionic/libc/arch-arm/generic/generic.mk

libc/arch-arm/cortex-a7/cortex-a7.mk

@@ -0,0 +1 @@
+include bionic/libc/arch-arm/cortex-a15/cortex-a15.mk

libc/arch-arm/cortex-a9/bionic/memcpy.S

@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2008 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+/*
+ * This code assumes it is running on a processor that supports all arm v7
+ * instructions, that supports neon instructions, and that has a 32 byte
+ * cache line.
+ */
+
+        .text
+        .fpu    neon
+
+#define CACHE_LINE_SIZE     32
+
+ENTRY(memcpy)
+        .save       {r0, lr}
+        /* start preloading as early as possible */
+        pld         [r1, #(CACHE_LINE_SIZE * 0)]
+        stmfd       sp!, {r0, lr}
+        pld         [r1, #(CACHE_LINE_SIZE * 2)]
+
+        // Check so divider is at least 16 bytes, needed for alignment code.
+        cmp         r2, #16
+        blo         5f
+
+
+        /* check if buffers are aligned. If so, run arm-only version */
+        eor         r3, r0, r1
+        ands        r3, r3, #0x3
+        beq         11f
+
+        /* Check the upper size limit for Neon unaligned memory access in memcpy */
+        cmp         r2, #224
+        blo         3f
+
+        /* align destination to 16 bytes for the write-buffer */
+        rsb         r3, r0, #0
+        ands        r3, r3, #0xF
+        beq         3f
+
+        /* copy up to 15-bytes (count in r3) */
+        sub         r2, r2, r3
+        movs        ip, r3, lsl #31
+        ldrmib      lr, [r1], #1
+        strmib      lr, [r0], #1
+        ldrcsb      ip, [r1], #1
+        ldrcsb      lr, [r1], #1
+        strcsb      ip, [r0], #1
+        strcsb      lr, [r0], #1
+        movs        ip, r3, lsl #29
+        bge         1f
+        // copies 4 bytes, destination 32-bits aligned
+        vld1.32     {d0[0]}, [r1]!
+        vst1.32     {d0[0]}, [r0, :32]!
+1:      bcc         2f
+        // copies 8 bytes, destination 64-bits aligned
+        vld1.8      {d0}, [r1]!
+        vst1.8      {d0}, [r0, :64]!
+2:
+        /* preload immediately the next cache line, which we may need */
+        pld         [r1, #(CACHE_LINE_SIZE * 0)]
+        pld         [r1, #(CACHE_LINE_SIZE * 2)]
+3:
+        /* make sure we have at least 64 bytes to copy */
+        subs        r2, r2, #64
+        blo         2f
+
+        /* preload all the cache lines we need */
+        pld         [r1, #(CACHE_LINE_SIZE * 4)]
+        pld         [r1, #(CACHE_LINE_SIZE * 6)]
+
+1:      /* The main loop copies 64 bytes at a time */
+        vld1.8      {d0 - d3}, [r1]!
+        vld1.8      {d4 - d7}, [r1]!
+        pld         [r1, #(CACHE_LINE_SIZE * 6)]
+        subs        r2, r2, #64
+        vst1.8      {d0 - d3}, [r0]!
+        vst1.8      {d4 - d7}, [r0]!
+        bhs         1b
+
+2:      /* fix-up the remaining count and make sure we have >= 32 bytes left */
+        add         r2, r2, #64
+        subs        r2, r2, #32
+        blo         4f
+
+3:      /* 32 bytes at a time. These cache lines were already preloaded */
+        vld1.8      {d0 - d3}, [r1]!
+        subs        r2, r2, #32
+        vst1.8      {d0 - d3}, [r0]!
+        bhs         3b
+
+4:      /* less than 32 left */
+        add         r2, r2, #32
+        tst         r2, #0x10
+        beq         5f
+        // copies 16 bytes, 128-bits aligned
+        vld1.8      {d0, d1}, [r1]!
+        vst1.8      {d0, d1}, [r0]!
+5:      /* copy up to 15-bytes (count in r2) */
+        movs        ip, r2, lsl #29
+        bcc         1f
+        vld1.8      {d0}, [r1]!
+        vst1.8      {d0}, [r0]!
+1:      bge         2f
+        vld1.32     {d0[0]}, [r1]!
+        vst1.32     {d0[0]}, [r0]!
+2:      movs        ip, r2, lsl #31
+        ldrmib      r3, [r1], #1
+        ldrcsb      ip, [r1], #1
+        ldrcsb      lr, [r1], #1
+        strmib      r3, [r0], #1
+        strcsb      ip, [r0], #1
+        strcsb      lr, [r0], #1
+
+        ldmfd       sp!, {r0, lr}
+        bx          lr
+11:
+        /* Simple arm-only copy loop to handle aligned copy operations */
+        stmfd       sp!, {r4, r5, r6, r7, r8}
+        pld         [r1, #(CACHE_LINE_SIZE * 4)]
+
+        /* Check alignment */
+        rsb         r3, r1, #0
+        ands        r3, #3
+        beq         2f
+
+        /* align source to 32 bits. We need to insert 2 instructions between
+         * a ldr[b|h] and str[b|h] because byte and half-word instructions
+         * stall 2 cycles.
+         */
+        movs        r12, r3, lsl #31
+        sub         r2, r2, r3      /* we know that r3 <= r2 because r2 >= 4 */
+        ldrmib      r3, [r1], #1
+        ldrcsb      r4, [r1], #1
+        ldrcsb      r5, [r1], #1
+        strmib      r3, [r0], #1
+        strcsb      r4, [r0], #1
+        strcsb      r5, [r0], #1
+
+2:
+        subs        r2, r2, #64
+        blt         4f
+
+3:      /* Main copy loop, copying 64 bytes at a time */
+        pld         [r1, #(CACHE_LINE_SIZE * 8)]
+        ldmia       r1!, {r3, r4, r5, r6, r7, r8, r12, lr}
+        stmia       r0!, {r3, r4, r5, r6, r7, r8, r12, lr}
+        ldmia       r1!, {r3, r4, r5, r6, r7, r8, r12, lr}
+        stmia       r0!, {r3, r4, r5, r6, r7, r8, r12, lr}
+        subs        r2, r2, #64
+        bge         3b
+
+4:      /* Check if there are > 32 bytes left */
+        adds        r2, r2, #64
+        subs        r2, r2, #32
+        blt         5f
+
+        /* Copy 32 bytes */
+        ldmia       r1!, {r3, r4, r5, r6, r7, r8, r12, lr}
+        stmia       r0!, {r3, r4, r5, r6, r7, r8, r12, lr}
+        subs        r2, #32
+
+5:      /* Handle any remaining bytes */
+        adds        r2, #32
+        beq         6f
+
+        movs        r12, r2, lsl #28
+        ldmcsia     r1!, {r3, r4, r5, r6}   /* 16 bytes */
+        ldmmiia     r1!, {r7, r8}           /*  8 bytes */
+        stmcsia     r0!, {r3, r4, r5, r6}
+        stmmiia     r0!, {r7, r8}
+        movs        r12, r2, lsl #30
+        ldrcs       r3, [r1], #4            /*  4 bytes */
+        ldrmih      r4, [r1], #2            /*  2 bytes */
+        strcs       r3, [r0], #4
+        strmih      r4, [r0], #2
+        tst         r2, #0x1
+        ldrneb      r3, [r1]                /*  last byte  */
+        strneb      r3, [r0]
+6:
+        ldmfd       sp!, {r4, r5, r6, r7, r8}
+        ldmfd       sp!, {r0, pc}
+END(memcpy)

libc/arch-arm/cortex-a9/bionic/memset.S

@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2008 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+/*
+ * This code assumes it is running on a processor that supports all arm v7
+ * instructions and that supports neon instructions.
+ */
+
+    .fpu    neon
+
+ENTRY(bzero)
+        mov     r2, r1
+        mov     r1, #0
+END(bzero)
+
+/* memset() returns its first argument.  */
+ENTRY(memset)
+        # The neon memset only wins for less than 132.
+        cmp         r2, #132
+        bhi         11f
+
+        .save       {r0}
+        stmfd       sp!, {r0}
+
+        vdup.8      q0, r1
+
+        /* make sure we have at least 32 bytes to write */
+        subs        r2, r2, #32
+        blo         2f
+        vmov        q1, q0
+
+1:      /* The main loop writes 32 bytes at a time */
+        subs        r2, r2, #32
+        vst1.8      {d0 - d3}, [r0]!
+        bhs         1b
+
+2:      /* less than 32 left */
+        add         r2, r2, #32
+        tst         r2, #0x10
+        beq         3f
+
+        // writes 16 bytes, 128-bits aligned
+        vst1.8      {d0, d1}, [r0]!
+3:      /* write up to 15-bytes (count in r2) */
+        movs        ip, r2, lsl #29
+        bcc         1f
+        vst1.8      {d0}, [r0]!
+1:      bge         2f
+        vst1.32     {d0[0]}, [r0]!
+2:      movs        ip, r2, lsl #31
+        strmib      r1, [r0], #1
+        strcsb      r1, [r0], #1
+        strcsb      r1, [r0], #1
+        ldmfd       sp!, {r0}
+        bx          lr
+11:
+        /* compute the offset to align the destination
+         * offset = (4-(src&3))&3 = -src & 3
+         */
+
+        .save       {r0, r4-r7, lr}
+        stmfd       sp!, {r0, r4-r7, lr}
+        rsb         r3, r0, #0
+        ands        r3, r3, #3
+        cmp         r3, r2
+        movhi       r3, r2
+
+        /* splat r1 */
+        mov         r1, r1, lsl #24
+        orr         r1, r1, r1, lsr #8
+        orr         r1, r1, r1, lsr #16
+
+        movs        r12, r3, lsl #31
+        strcsb      r1, [r0], #1    /* can't use strh (alignment unknown) */
+        strcsb      r1, [r0], #1
+        strmib      r1, [r0], #1
+        subs        r2, r2, r3
+        ldmlsfd     sp!, {r0, r4-r7, lr}   /* return */
+        bxls        lr
+
+        /* align the destination to a cache-line */
+        mov         r12, r1
+        mov         lr, r1
+        mov         r4, r1
+        mov         r5, r1
+        mov         r6, r1
+        mov         r7, r1
+
+        rsb         r3, r0, #0
+        ands        r3, r3, #0x1C
+        beq         3f
+        cmp         r3, r2
+        andhi       r3, r2, #0x1C
+        sub         r2, r2, r3
+
+        /* conditionally writes 0 to 7 words (length in r3) */
+        movs        r3, r3, lsl #28
+        stmcsia     r0!, {r1, lr}
+        stmcsia     r0!, {r1, lr}
+        stmmiia     r0!, {r1, lr}
+        movs        r3, r3, lsl #2
+        strcs       r1, [r0], #4
+
+3:
+        subs        r2, r2, #32
+        mov         r3, r1
+        bmi         2f
+1:      subs        r2, r2, #32
+        stmia       r0!, {r1,r3,r4,r5,r6,r7,r12,lr}
+        bhs         1b
+2:      add         r2, r2, #32
+
+        /* conditionally stores 0 to 31 bytes */
+        movs        r2, r2, lsl #28
+        stmcsia     r0!, {r1,r3,r12,lr}
+        stmmiia     r0!, {r1, lr}
+        movs        r2, r2, lsl #2
+        strcs       r1, [r0], #4
+        strmih      r1, [r0], #2
+        movs        r2, r2, lsl #2
+        strcsb      r1, [r0]
+        ldmfd       sp!, {r0, r4-r7, lr}
+        bx          lr
+END(memset)

libc/arch-arm/cortex-a9/bionic/strcmp.S

@@ -0,0 +1,544 @@
+/*
+ * Copyright (c) 2013 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+#ifdef __ARMEB__
+#define S2LOMEM lsl
+#define S2LOMEMEQ lsleq
+#define S2HIMEM lsr
+#define MSB 0x000000ff
+#define LSB 0xff000000
+#define BYTE0_OFFSET 24
+#define BYTE1_OFFSET 16
+#define BYTE2_OFFSET 8
+#define BYTE3_OFFSET 0
+#else /* not  __ARMEB__ */
+#define S2LOMEM lsr
+#define S2LOMEMEQ lsreq
+#define S2HIMEM lsl
+#define BYTE0_OFFSET 0
+#define BYTE1_OFFSET 8
+#define BYTE2_OFFSET 16
+#define BYTE3_OFFSET 24
+#define MSB 0xff000000
+#define LSB 0x000000ff
+#endif /* not  __ARMEB__ */
+
+.syntax         unified
+
+#if defined (__thumb__)
+        .thumb
+        .thumb_func
+#endif
+
+ENTRY(strcmp)
+      /* Use LDRD whenever possible.  */
+
+/* The main thing to look out for when comparing large blocks is that
+   the loads do not cross a page boundary when loading past the index
+   of the byte with the first difference or the first string-terminator.
+
+   For example, if the strings are identical and the string-terminator
+   is at index k, byte by byte comparison will not load beyond address
+   s1+k and s2+k; word by word comparison may load up to 3 bytes beyond
+   k; double word - up to 7 bytes.  If the load of these bytes crosses
+   a page boundary, it might cause a memory fault (if the page is not mapped)
+   that would not have happened in byte by byte comparison.
+
+   If an address is (double) word aligned, then a load of a (double) word
+   from that address will not cross a page boundary.
+   Therefore, the algorithm below considers word and double-word alignment
+   of strings separately.  */
+
+/* High-level description of the algorithm.
+
+   * The fast path: if both strings are double-word aligned,
+     use LDRD to load two words from each string in every loop iteration.
+   * If the strings have the same offset from a word boundary,
+     use LDRB to load and compare byte by byte until
+     the first string is aligned to a word boundary (at most 3 bytes).
+     This is optimized for quick return on short unaligned strings.
+   * If the strings have the same offset from a double-word boundary,
+     use LDRD to load two words from each string in every loop iteration, as in the fast path.
+   * If the strings do not have the same offset from a double-word boundary,
+     load a word from the second string before the loop to initialize the queue.
+     Use LDRD to load two words from every string in every loop iteration.
+     Inside the loop, load the second word from the second string only after comparing
+     the first word, using the queued value, to guarantee safety across page boundaries.
+   * If the strings do not have the same offset from a word boundary,
+     use LDR and a shift queue. Order of loads and comparisons matters,
+     similarly to the previous case.
+
+   * Use UADD8 and SEL to compare words, and use REV and CLZ to compute the return value.
+   * The only difference between ARM and Thumb modes is the use of CBZ instruction.
+   * The only difference between big and little endian is the use of REV in little endian
+     to compute the return value, instead of MOV.
+*/
+
+        .macro m_cbz reg label
+#ifdef __thumb2__
+        cbz     \reg, \label
+#else   /* not defined __thumb2__ */
+        cmp     \reg, #0
+        beq     \label
+#endif /* not defined __thumb2__ */
+        .endm /* m_cbz */
+
+        .macro m_cbnz reg label
+#ifdef __thumb2__
+        cbnz    \reg, \label
+#else   /* not defined __thumb2__ */
+        cmp     \reg, #0
+        bne     \label
+#endif /* not defined __thumb2__ */
+        .endm /* m_cbnz */
+
+        .macro  init
+        /* Macro to save temporary registers and prepare magic values.  */
+        subs    sp, sp, #16
+        strd    r4, r5, [sp, #8]
+        strd    r6, r7, [sp]
+        mvn     r6, #0  /* all F */
+        mov     r7, #0  /* all 0 */
+        .endm   /* init */
+
+        .macro  magic_compare_and_branch w1 w2 label
+        /* Macro to compare registers w1 and w2 and conditionally branch to label.  */
+        cmp     \w1, \w2        /* Are w1 and w2 the same?  */
+        magic_find_zero_bytes \w1
+        it      eq
+        cmpeq   ip, #0          /* Is there a zero byte in w1?  */
+        bne     \label
+        .endm /* magic_compare_and_branch */
+
+        .macro  magic_find_zero_bytes w1
+        /* Macro to find all-zero bytes in w1, result is in ip.  */
+#if (defined (__ARM_FEATURE_DSP))
+        uadd8   ip, \w1, r6
+        sel     ip, r7, r6
+#else /* not defined (__ARM_FEATURE_DSP) */
+        /* __ARM_FEATURE_DSP is not defined for some Cortex-M processors.
+        Coincidently, these processors only have Thumb-2 mode, where we can use the
+        the (large) magic constant available directly as an immediate in instructions.
+        Note that we cannot use the magic constant in ARM mode, where we need
+        to create the constant in a register.  */
+        sub     ip, \w1, #0x01010101
+        bic     ip, ip, \w1
+        and     ip, ip, #0x80808080
+#endif /* not defined (__ARM_FEATURE_DSP) */
+        .endm /* magic_find_zero_bytes */
+
+        .macro  setup_return w1 w2
+#ifdef __ARMEB__
+        mov     r1, \w1
+        mov     r2, \w2
+#else /* not  __ARMEB__ */
+        rev     r1, \w1
+        rev     r2, \w2
+#endif /* not  __ARMEB__ */
+        .endm /* setup_return */
+
+        pld [r0, #0]
+        pld [r1, #0]
+
+        /* Are both strings double-word aligned?  */
+        orr     ip, r0, r1
+        tst     ip, #7
+        bne     do_align
+
+        /* Fast path.  */
+        init
+
+doubleword_aligned:
+
+        /* Get here when the strings to compare are double-word aligned.  */
+        /* Compare two words in every iteration.  */
+        .p2align        2
+2:
+        pld [r0, #16]
+        pld [r1, #16]
+
+        /* Load the next double-word from each string.  */
+        ldrd    r2, r3, [r0], #8
+        ldrd    r4, r5, [r1], #8
+
+        magic_compare_and_branch w1=r2, w2=r4, label=return_24
+        magic_compare_and_branch w1=r3, w2=r5, label=return_35
+        b       2b
+
+do_align:
+        /* Is the first string word-aligned?  */
+        ands    ip, r0, #3
+        beq     word_aligned_r0
+
+        /* Fast compare byte by byte until the first string is word-aligned.  */
+        /* The offset of r0 from a word boundary is in ip. Thus, the number of bytes
+        to read until the next word boundary is 4-ip.  */
+        bic     r0, r0, #3
+        ldr     r2, [r0], #4
+        lsls    ip, ip, #31
+        beq     byte2
+        bcs     byte3
+
+byte1:
+        ldrb    ip, [r1], #1
+        uxtb    r3, r2, ror #BYTE1_OFFSET
+        subs    ip, r3, ip
+        bne     fast_return
+        m_cbz   reg=r3, label=fast_return
+
+byte2:
+        ldrb    ip, [r1], #1
+        uxtb    r3, r2, ror #BYTE2_OFFSET
+        subs    ip, r3, ip
+        bne     fast_return
+        m_cbz   reg=r3, label=fast_return
+
+byte3:
+        ldrb    ip, [r1], #1
+        uxtb    r3, r2, ror #BYTE3_OFFSET
+        subs    ip, r3, ip
+        bne     fast_return
+        m_cbnz  reg=r3, label=word_aligned_r0
+
+fast_return:
+        mov     r0, ip
+        bx      lr
+
+word_aligned_r0:
+        init
+        /* The first string is word-aligned.  */
+        /* Is the second string word-aligned?  */
+        ands    ip, r1, #3
+        bne     strcmp_unaligned
+
+word_aligned:
+        /* The strings are word-aligned. */
+        /* Is the first string double-word aligned?  */
+        tst     r0, #4
+        beq     doubleword_aligned_r0
+
+        /* If r0 is not double-word aligned yet, align it by loading
+        and comparing the next word from each string.  */
+        ldr     r2, [r0], #4
+        ldr     r4, [r1], #4
+        magic_compare_and_branch w1=r2 w2=r4 label=return_24
+
+doubleword_aligned_r0:
+        /* Get here when r0 is double-word aligned.  */
+        /* Is r1 doubleword_aligned?  */
+        tst     r1, #4
+        beq     doubleword_aligned
+
+        /* Get here when the strings to compare are word-aligned,
+        r0 is double-word aligned, but r1 is not double-word aligned.  */
+
+        /* Initialize the queue.  */
+        ldr     r5, [r1], #4
+
+        /* Compare two words in every iteration.  */
+        .p2align        2
+3:
+        pld [r0, #16]
+        pld [r1, #16]
+
+        /* Load the next double-word from each string and compare.  */
+        ldrd    r2, r3, [r0], #8
+        magic_compare_and_branch w1=r2 w2=r5 label=return_25
+        ldrd    r4, r5, [r1], #8
+        magic_compare_and_branch w1=r3 w2=r4 label=return_34
+        b       3b
+
+        .macro miscmp_word offsetlo offsethi
+        /* Macro to compare misaligned strings.  */
+        /* r0, r1 are word-aligned, and at least one of the strings
+        is not double-word aligned.  */
+        /* Compare one word in every loop iteration.  */
+        /* OFFSETLO is the original bit-offset of r1 from a word-boundary,
+        OFFSETHI is 32 - OFFSETLO (i.e., offset from the next word).  */
+
+        /* Initialize the shift queue.  */
+        ldr     r5, [r1], #4
+
+        /* Compare one word from each string in every loop iteration.  */
+        .p2align        2
+7:
+        ldr     r3, [r0], #4
+        S2LOMEM r5, r5, #\offsetlo
+        magic_find_zero_bytes w1=r3
+        cmp     r7, ip, S2HIMEM #\offsetlo
+        and     r2, r3, r6, S2LOMEM #\offsetlo
+        it      eq
+        cmpeq   r2, r5
+        bne     return_25
+        ldr     r5, [r1], #4
+        cmp     ip, #0
+        eor r3, r2, r3
+        S2HIMEM r2, r5, #\offsethi
+        it      eq
+        cmpeq   r3, r2
+        bne     return_32
+        b       7b
+        .endm /* miscmp_word */
+
+return_32:
+        setup_return w1=r3, w2=r2
+        b       do_return
+return_34:
+        setup_return w1=r3, w2=r4
+        b       do_return
+return_25:
+        setup_return w1=r2, w2=r5
+        b       do_return
+return_35:
+        setup_return w1=r3, w2=r5
+        b       do_return
+return_24:
+        setup_return w1=r2, w2=r4
+
+do_return:
+
+#ifdef __ARMEB__
+        mov     r0, ip
+#else /* not  __ARMEB__ */
+        rev     r0, ip
+#endif /* not  __ARMEB__ */
+
+        /* Restore temporaries early, before computing the return value.  */
+        ldrd    r6, r7, [sp]
+        ldrd    r4, r5, [sp, #8]
+        adds    sp, sp, #16
+
+        /* There is a zero or a different byte between r1 and r2.  */
+        /* r0 contains a mask of all-zero bytes in r1.  */
+        /* Using r0 and not ip here because cbz requires low register.  */
+        m_cbz   reg=r0, label=compute_return_value
+        clz     r0, r0
+        /* r0 contains the number of bits on the left of the first all-zero byte in r1.  */
+        rsb     r0, r0, #24
+        /* Here, r0 contains the number of bits on the right of the first all-zero byte in r1.  */
+        lsr     r1, r1, r0
+        lsr     r2, r2, r0
+
+compute_return_value:
+        movs    r0, #1
+        cmp     r1, r2
+        /* The return value is computed as follows.
+        If r1>r2 then (C==1 and Z==0) and LS doesn't hold and r0 is #1 at return.
+        If r1<r2 then (C==0 and Z==0) and we execute SBC with carry_in=0,
+        which means r0:=r0-r0-1 and r0 is #-1 at return.
+        If r1=r2 then (C==1 and Z==1) and we execute SBC with carry_in=1,
+        which means r0:=r0-r0 and r0 is #0 at return.
+        (C==0 and Z==1) cannot happen because the carry bit is "not borrow".  */
+        it      ls
+        sbcls   r0, r0, r0
+        bx      lr
+
+    /* The code from the previous version of strcmp.S handles all of the
+     * cases where the first string and seconds string cannot both be
+     * aligned to a word boundary faster than the new algorithm. See
+     * bionic/libc/arch-arm/cortex-a15/bionic/strcmp.S for the unedited
+     * version of the code.
+     */
+strcmp_unaligned:
+	wp1 .req r0
+	wp2 .req r1
+	b1  .req r2
+	w1  .req r4
+	w2  .req r5
+	t1  .req ip
+	@ r3 is scratch
+
+2:
+	mov	b1, #1
+	orr	b1, b1, b1, lsl #8
+	orr	b1, b1, b1, lsl #16
+
+	and	t1, wp2, #3
+	bic	wp2, wp2, #3
+	ldr	w1, [wp1], #4
+	ldr	w2, [wp2], #4
+	cmp	t1, #2
+	beq	2f
+	bhi	3f
+
+	/* Critical inner Loop: Block with 3 bytes initial overlap */
+	.p2align	2
+1:
+	bic	t1, w1, #MSB
+	cmp	t1, w2, S2LOMEM #8
+	sub	r3, w1, b1
+	bic	r3, r3, w1
+	bne	4f
+	ands	r3, r3, b1, lsl #7
+	it	eq
+	ldreq	w2, [wp2], #4
+	bne	5f
+	eor	t1, t1, w1
+	cmp	t1, w2, S2HIMEM #24
+	bne	6f
+	ldr	w1, [wp1], #4
+	b	1b
+4:
+	S2LOMEM	w2, w2, #8
+	b	8f
+
+5:
+#ifdef __ARMEB__
+	/* The syndrome value may contain false ones if the string ends
+	 * with the bytes 0x01 0x00
+	 */
+	tst	w1, #0xff000000
+	itt	ne
+	tstne	w1, #0x00ff0000
+	tstne	w1, #0x0000ff00
+	beq	7f
+#else
+	bics	r3, r3, #0xff000000
+	bne	7f
+#endif
+	ldrb	w2, [wp2]
+	S2LOMEM	t1, w1, #24
+#ifdef __ARMEB__
+	lsl	w2, w2, #24
+#endif
+	b	8f
+
+6:
+	S2LOMEM	t1, w1, #24
+	and	w2, w2, #LSB
+	b	8f
+
+	/* Critical inner Loop: Block with 2 bytes initial overlap */
+	.p2align	2
+2:
+	S2HIMEM	t1, w1, #16
+	sub	r3, w1, b1
+	S2LOMEM	t1, t1, #16
+	bic	r3, r3, w1
+	cmp	t1, w2, S2LOMEM #16
+	bne	4f
+	ands	r3, r3, b1, lsl #7
+	it	eq
+	ldreq	w2, [wp2], #4
+	bne	5f
+	eor	t1, t1, w1
+	cmp	t1, w2, S2HIMEM #16
+	bne	6f
+	ldr	w1, [wp1], #4
+	b	2b
+
+5:
+#ifdef __ARMEB__
+	/* The syndrome value may contain false ones if the string ends
+	 * with the bytes 0x01 0x00
+	 */
+	tst	w1, #0xff000000
+	it	ne
+	tstne	w1, #0x00ff0000
+	beq	7f
+#else
+	lsls	r3, r3, #16
+	bne	7f
+#endif
+	ldrh	w2, [wp2]
+	S2LOMEM	t1, w1, #16
+#ifdef __ARMEB__
+	lsl	w2, w2, #16
+#endif
+	b	8f
+
+6:
+	S2HIMEM	w2, w2, #16
+	S2LOMEM	t1, w1, #16
+4:
+	S2LOMEM	w2, w2, #16
+	b	8f
+
+	/* Critical inner Loop: Block with 1 byte initial overlap */
+	.p2align	2
+3:
+	and	t1, w1, #LSB
+	cmp	t1, w2, S2LOMEM #24
+	sub	r3, w1, b1
+	bic	r3, r3, w1
+	bne	4f
+	ands	r3, r3, b1, lsl #7
+	it	eq
+	ldreq	w2, [wp2], #4
+	bne	5f
+	eor	t1, t1, w1
+	cmp	t1, w2, S2HIMEM #8
+	bne	6f
+	ldr	w1, [wp1], #4
+	b	3b
+4:
+	S2LOMEM	w2, w2, #24
+	b	8f
+5:
+	/* The syndrome value may contain false ones if the string ends
+	 * with the bytes 0x01 0x00
+	 */
+	tst	w1, #LSB
+	beq	7f
+	ldr	w2, [wp2], #4
+6:
+	S2LOMEM	t1, w1, #8
+	bic	w2, w2, #MSB
+	b	8f
+7:
+	mov	r0, #0
+
+    /* Restore registers and stack. */
+    ldrd    r6, r7, [sp]
+    ldrd    r4, r5, [sp, #8]
+    adds    sp, sp, #16
+
+	bx	lr
+
+8:
+	and	r2, t1, #LSB
+	and	r0, w2, #LSB
+	cmp	r0, #1
+	it	cs
+	cmpcs	r0, r2
+	itt	eq
+	S2LOMEMEQ	t1, t1, #8
+	S2LOMEMEQ	w2, w2, #8
+	beq	8b
+	sub	r0, r2, r0
+
+    /* Restore registers and stack. */
+    ldrd    r6, r7, [sp]
+    ldrd    r4, r5, [sp, #8]
+    adds    sp, sp, #16
+
+	bx	lr
+END(strcmp)

libc/arch-arm/cortex-a9/cortex-a9.mk

@@ -0,0 +1,5 @@
+$(call libc-add-cpu-variant-src,MEMCPY,arch-arm/cortex-a9/bionic/memcpy.S)
+$(call libc-add-cpu-variant-src,MEMSET,arch-arm/cortex-a9/bionic/memset.S)
+$(call libc-add-cpu-variant-src,STRCMP,arch-arm/cortex-a9/bionic/strcmp.S)
+
+include bionic/libc/arch-arm/generic/generic.mk

libc/arch-arm/generic/bionic/memcpy.S

@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2008 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+        /*
+         * Optimized memcpy() for ARM.
+         *
+         * note that memcpy() always returns the destination pointer,
+         * so we have to preserve R0.
+         */
+
+ENTRY(memcpy)
+        /* The stack must always be 64-bits aligned to be compliant with the
+         * ARM ABI. Since we have to save R0, we might as well save R4
+         * which we can use for better pipelining of the reads below
+         */
+        .save       {r0, r4, lr}
+        stmfd       sp!, {r0, r4, lr}
+        /* Making room for r5-r11 which will be spilled later */
+        .pad        #28
+        sub         sp, sp, #28
+
+        // preload the destination because we'll align it to a cache line
+        // with small writes. Also start the source "pump".
+        PLD         (r0, #0)
+        PLD         (r1, #0)
+        PLD         (r1, #32)
+
+        /* it simplifies things to take care of len<4 early */
+        cmp         r2, #4
+        blo         copy_last_3_and_return
+
+        /* compute the offset to align the source
+         * offset = (4-(src&3))&3 = -src & 3
+         */
+        rsb         r3, r1, #0
+        ands        r3, r3, #3
+        beq         src_aligned
+
+        /* align source to 32 bits. We need to insert 2 instructions between
+         * a ldr[b|h] and str[b|h] because byte and half-word instructions
+         * stall 2 cycles.
+         */
+        movs        r12, r3, lsl #31
+        sub         r2, r2, r3      /* we know that r3 <= r2 because r2 >= 4 */
+        ldrmib      r3, [r1], #1
+        ldrcsb      r4, [r1], #1
+        ldrcsb      r12,[r1], #1
+        strmib      r3, [r0], #1
+        strcsb      r4, [r0], #1
+        strcsb      r12,[r0], #1
+
+src_aligned:
+
+        /* see if src and dst are aligned together (congruent) */
+        eor         r12, r0, r1
+        tst         r12, #3
+        bne         non_congruent
+
+        /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
+         * frame. Don't update sp.
+         */
+        stmea       sp, {r5-r11}
+
+        /* align the destination to a cache-line */
+        rsb         r3, r0, #0
+        ands        r3, r3, #0x1C
+        beq         congruent_aligned32
+        cmp         r3, r2
+        andhi       r3, r2, #0x1C
+
+        /* conditionally copies 0 to 7 words (length in r3) */
+        movs        r12, r3, lsl #28
+        ldmcsia     r1!, {r4, r5, r6, r7}   /* 16 bytes */
+        ldmmiia     r1!, {r8, r9}           /*  8 bytes */
+        stmcsia     r0!, {r4, r5, r6, r7}
+        stmmiia     r0!, {r8, r9}
+        tst         r3, #0x4
+        ldrne       r10,[r1], #4            /*  4 bytes */
+        strne       r10,[r0], #4
+        sub         r2, r2, r3
+
+congruent_aligned32:
+        /*
+         * here source is aligned to 32 bytes.
+         */
+
+cached_aligned32:
+        subs        r2, r2, #32
+        blo         less_than_32_left
+
+        /*
+         * We preload a cache-line up to 64 bytes ahead. On the 926, this will
+         * stall only until the requested world is fetched, but the linefill
+         * continues in the the background.
+         * While the linefill is going, we write our previous cache-line
+         * into the write-buffer (which should have some free space).
+         * When the linefill is done, the writebuffer will
+         * start dumping its content into memory
+         *
+         * While all this is going, we then load a full cache line into
+         * 8 registers, this cache line should be in the cache by now
+         * (or partly in the cache).
+         *
+         * This code should work well regardless of the source/dest alignment.
+         *
+         */
+
+        // Align the preload register to a cache-line because the cpu does
+        // "critical word first" (the first word requested is loaded first).
+        bic         r12, r1, #0x1F
+        add         r12, r12, #64
+
+1:      ldmia       r1!, { r4-r11 }
+        PLD         (r12, #64)
+        subs        r2, r2, #32
+
+        // NOTE: if r12 is more than 64 ahead of r1, the following ldrhi
+        // for ARM9 preload will not be safely guarded by the preceding subs.
+        // When it is safely guarded the only possibility to have SIGSEGV here
+        // is because the caller overstates the length.
+        ldrhi       r3, [r12], #32      /* cheap ARM9 preload */
+        stmia       r0!, { r4-r11 }
+        bhs         1b
+
+        add         r2, r2, #32
+
+
+
+
+less_than_32_left:
+        /*
+         * less than 32 bytes left at this point (length in r2)
+         */
+
+        /* skip all this if there is nothing to do, which should
+         * be a common case (if not executed the code below takes
+         * about 16 cycles)
+         */
+        tst         r2, #0x1F
+        beq         1f
+
+        /* conditionnaly copies 0 to 31 bytes */
+        movs        r12, r2, lsl #28
+        ldmcsia     r1!, {r4, r5, r6, r7}   /* 16 bytes */
+        ldmmiia     r1!, {r8, r9}           /*  8 bytes */
+        stmcsia     r0!, {r4, r5, r6, r7}
+        stmmiia     r0!, {r8, r9}
+        movs        r12, r2, lsl #30
+        ldrcs       r3, [r1], #4            /*  4 bytes */
+        ldrmih      r4, [r1], #2            /*  2 bytes */
+        strcs       r3, [r0], #4
+        strmih      r4, [r0], #2
+        tst         r2, #0x1
+        ldrneb      r3, [r1]                /*  last byte  */
+        strneb      r3, [r0]
+
+        /* we're done! restore everything and return */
+1:      ldmfd       sp!, {r5-r11}
+        ldmfd       sp!, {r0, r4, lr}
+        bx          lr
+
+        /********************************************************************/
+
+non_congruent:
+        /*
+         * here source is aligned to 4 bytes
+         * but destination is not.
+         *
+         * in the code below r2 is the number of bytes read
+         * (the number of bytes written is always smaller, because we have
+         * partial words in the shift queue)
+         */
+        cmp         r2, #4
+        blo         copy_last_3_and_return
+
+        /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
+         * frame. Don't update sp.
+         */
+        stmea       sp, {r5-r11}
+
+        /* compute shifts needed to align src to dest */
+        rsb         r5, r0, #0
+        and         r5, r5, #3          /* r5 = # bytes in partial words */
+        mov         r12, r5, lsl #3     /* r12 = right */
+        rsb         lr, r12, #32        /* lr = left  */
+
+        /* read the first word */
+        ldr         r3, [r1], #4
+        sub         r2, r2, #4
+
+        /* write a partial word (0 to 3 bytes), such that destination
+         * becomes aligned to 32 bits (r5 = nb of words to copy for alignment)
+         */
+        movs        r5, r5, lsl #31
+        strmib      r3, [r0], #1
+        movmi       r3, r3, lsr #8
+        strcsb      r3, [r0], #1
+        movcs       r3, r3, lsr #8
+        strcsb      r3, [r0], #1
+        movcs       r3, r3, lsr #8
+
+        cmp         r2, #4
+        blo         partial_word_tail
+
+        /* Align destination to 32 bytes (cache line boundary) */
+1:      tst         r0, #0x1c
+        beq         2f
+        ldr         r5, [r1], #4
+        sub         r2, r2, #4
+        orr         r4, r3, r5,     lsl lr
+        mov         r3, r5,         lsr r12
+        str         r4, [r0], #4
+        cmp         r2, #4
+        bhs         1b
+        blo         partial_word_tail
+
+        /* copy 32 bytes at a time */
+2:      subs        r2, r2, #32
+        blo         less_than_thirtytwo
+
+        /* Use immediate mode for the shifts, because there is an extra cycle
+         * for register shifts, which could account for up to 50% of
+         * performance hit.
+         */
+
+        cmp         r12, #24
+        beq         loop24
+        cmp         r12, #8
+        beq         loop8
+
+loop16:
+        ldr         r12, [r1], #4
+1:      mov         r4, r12
+        ldmia       r1!, {   r5,r6,r7,  r8,r9,r10,r11}
+        PLD         (r1, #64)
+        subs        r2, r2, #32
+        ldrhs       r12, [r1], #4
+        orr         r3, r3, r4,     lsl #16
+        mov         r4, r4,         lsr #16
+        orr         r4, r4, r5,     lsl #16
+        mov         r5, r5,         lsr #16
+        orr         r5, r5, r6,     lsl #16
+        mov         r6, r6,         lsr #16
+        orr         r6, r6, r7,     lsl #16
+        mov         r7, r7,         lsr #16
+        orr         r7, r7, r8,     lsl #16
+        mov         r8, r8,         lsr #16
+        orr         r8, r8, r9,     lsl #16
+        mov         r9, r9,         lsr #16
+        orr         r9, r9, r10,    lsl #16
+        mov         r10, r10,       lsr #16
+        orr         r10, r10, r11,  lsl #16
+        stmia       r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
+        mov         r3, r11,        lsr #16
+        bhs         1b
+        b           less_than_thirtytwo
+
+loop8:
+        ldr         r12, [r1], #4
+1:      mov         r4, r12
+        ldmia       r1!, {   r5,r6,r7,  r8,r9,r10,r11}
+        PLD         (r1, #64)
+        subs        r2, r2, #32
+        ldrhs       r12, [r1], #4
+        orr         r3, r3, r4,     lsl #24
+        mov         r4, r4,         lsr #8
+        orr         r4, r4, r5,     lsl #24
+        mov         r5, r5,         lsr #8
+        orr         r5, r5, r6,     lsl #24
+        mov         r6, r6,         lsr #8
+        orr         r6, r6, r7,     lsl #24
+        mov         r7, r7,         lsr #8
+        orr         r7, r7, r8,     lsl #24
+        mov         r8, r8,         lsr #8
+        orr         r8, r8, r9,     lsl #24
+        mov         r9, r9,         lsr #8
+        orr         r9, r9, r10,    lsl #24
+        mov         r10, r10,       lsr #8
+        orr         r10, r10, r11,  lsl #24
+        stmia       r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
+        mov         r3, r11,        lsr #8
+        bhs         1b
+        b           less_than_thirtytwo
+
+loop24:
+        ldr         r12, [r1], #4
+1:      mov         r4, r12
+        ldmia       r1!, {   r5,r6,r7,  r8,r9,r10,r11}
+        PLD         (r1, #64)
+        subs        r2, r2, #32
+        ldrhs       r12, [r1], #4
+        orr         r3, r3, r4,     lsl #8
+        mov         r4, r4,         lsr #24
+        orr         r4, r4, r5,     lsl #8
+        mov         r5, r5,         lsr #24
+        orr         r5, r5, r6,     lsl #8
+        mov         r6, r6,         lsr #24
+        orr         r6, r6, r7,     lsl #8
+        mov         r7, r7,         lsr #24
+        orr         r7, r7, r8,     lsl #8
+        mov         r8, r8,         lsr #24
+        orr         r8, r8, r9,     lsl #8
+        mov         r9, r9,         lsr #24
+        orr         r9, r9, r10,    lsl #8
+        mov         r10, r10,       lsr #24
+        orr         r10, r10, r11,  lsl #8
+        stmia       r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
+        mov         r3, r11,        lsr #24
+        bhs         1b
+
+
+less_than_thirtytwo:
+        /* copy the last 0 to 31 bytes of the source */
+        rsb         r12, lr, #32        /* we corrupted r12, recompute it  */
+        add         r2, r2, #32
+        cmp         r2, #4
+        blo         partial_word_tail
+
+1:      ldr         r5, [r1], #4
+        sub         r2, r2, #4
+        orr         r4, r3, r5,     lsl lr
+        mov         r3, r5,         lsr r12
+        str         r4, [r0], #4
+        cmp         r2, #4
+        bhs         1b
+
+partial_word_tail:
+        /* we have a partial word in the input buffer */
+        movs        r5, lr, lsl #(31-3)
+        strmib      r3, [r0], #1
+        movmi       r3, r3, lsr #8
+        strcsb      r3, [r0], #1
+        movcs       r3, r3, lsr #8
+        strcsb      r3, [r0], #1
+
+        /* Refill spilled registers from the stack. Don't update sp. */
+        ldmfd       sp, {r5-r11}
+
+copy_last_3_and_return:
+        movs        r2, r2, lsl #31 /* copy remaining 0, 1, 2 or 3 bytes */
+        ldrmib      r2, [r1], #1
+        ldrcsb      r3, [r1], #1
+        ldrcsb      r12,[r1]
+        strmib      r2, [r0], #1
+        strcsb      r3, [r0], #1
+        strcsb      r12,[r0]
+
+        /* we're done! restore sp and spilled registers and return */
+        add         sp,  sp, #28
+        ldmfd       sp!, {r0, r4, lr}
+        bx          lr
+END(memcpy)

libc/arch-arm/generic/bionic/memset.S

@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2008 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <machine/asm.h>
+
+        /*
+         * Optimized memset() for ARM.
+         *
+         * memset() returns its first argument.
+         */
+
+ENTRY(bzero)
+        mov     r2, r1
+        mov     r1, #0
+END(bzero)
+
+ENTRY(memset)
+        /* compute the offset to align the destination
+         * offset = (4-(src&3))&3 = -src & 3
+         */
+        .save       {r0, r4-r7, lr}
+        stmfd       sp!, {r0, r4-r7, lr}
+        rsb         r3, r0, #0
+        ands        r3, r3, #3
+        cmp         r3, r2
+        movhi       r3, r2
+
+        /* splat r1 */
+        mov         r1, r1, lsl #24
+        orr         r1, r1, r1, lsr #8
+        orr         r1, r1, r1, lsr #16
+
+        movs        r12, r3, lsl #31
+        strcsb      r1, [r0], #1    /* can't use strh (alignment unknown) */
+        strcsb      r1, [r0], #1
+        strmib      r1, [r0], #1
+        subs        r2, r2, r3
+        ldmlsfd     sp!, {r0, r4-r7, lr}    /* return */
+        bxls        lr
+
+        /* align the destination to a cache-line */
+        mov         r12, r1
+        mov         lr, r1
+        mov         r4, r1
+        mov         r5, r1
+        mov         r6, r1
+        mov         r7, r1
+
+        rsb         r3, r0, #0
+        ands        r3, r3, #0x1C
+        beq         3f
+        cmp         r3, r2
+        andhi       r3, r2, #0x1C
+        sub         r2, r2, r3
+
+        /* conditionally writes 0 to 7 words (length in r3) */
+        movs        r3, r3, lsl #28
+        stmcsia     r0!, {r1, lr}
+        stmcsia     r0!, {r1, lr}
+        stmmiia     r0!, {r1, lr}
+        movs        r3, r3, lsl #2
+        strcs       r1, [r0], #4
+
+3:
+        subs        r2, r2, #32
+        mov         r3, r1
+        bmi         2f
+1:      subs        r2, r2, #32
+        stmia       r0!, {r1,r3,r4,r5,r6,r7,r12,lr}
+        bhs         1b
+2:      add         r2, r2, #32
+
+        /* conditionally stores 0 to 31 bytes */
+        movs        r2, r2, lsl #28
+        stmcsia     r0!, {r1,r3,r12,lr}
+        stmmiia     r0!, {r1, lr}
+        movs        r2, r2, lsl #2
+        strcs       r1, [r0], #4
+        strmih      r1, [r0], #2
+        movs        r2, r2, lsl #2
+        strcsb      r1, [r0]
+        ldmfd       sp!, {r0, r4-r7, lr}
+        bx          lr
+END(memset)

libc/arch-arm/generic/bionic/strcmp.S

@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2011 The Android Open Source Project
+ * Copyright (c) 2008 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+	.text
+
+#ifdef __ARMEB__
+#define SHFT2LSB lsl
+#define SHFT2LSBEQ lsleq
+#define SHFT2MSB lsr
+#define SHFT2MSBEQ lsreq
+#define MSB 0x000000ff
+#define LSB 0xff000000
+#else
+#define SHFT2LSB lsr
+#define SHFT2LSBEQ lsreq
+#define SHFT2MSB lsl
+#define SHFT2MSBEQ lsleq
+#define MSB 0xff000000
+#define LSB 0x000000ff
+#endif
+
+#define magic1(REG) REG
+#define magic2(REG) REG, lsl #7
+
+ENTRY(strcmp)
+	PLD(r0, #0)
+	PLD(r1, #0)
+	eor	r2, r0, r1
+	tst	r2, #3
+
+	/* Strings not at same byte offset from a word boundary.  */
+	bne	.Lstrcmp_unaligned
+	ands	r2, r0, #3
+	bic	r0, r0, #3
+	bic	r1, r1, #3
+	ldr	ip, [r0], #4
+	it	eq
+	ldreq	r3, [r1], #4
+	beq	1f
+
+	/* Although s1 and s2 have identical initial alignment, they are
+	 * not currently word aligned.  Rather than comparing bytes,
+	 * make sure that any bytes fetched from before the addressed
+	 * bytes are forced to 0xff.  Then they will always compare
+	 * equal.
+	 */
+	eor	r2, r2, #3
+	lsl	r2, r2, #3
+	mvn	r3, #MSB
+	SHFT2LSB	r2, r3, r2
+	ldr	r3, [r1], #4
+	orr	ip, ip, r2
+	orr	r3, r3, r2
+1:
+	/* Load the 'magic' constant 0x01010101. */
+	str	r4, [sp, #-4]!
+	mov	r4, #1
+	orr	r4, r4, r4, lsl #8
+	orr	r4, r4, r4, lsl #16
+	.p2align	2
+4:
+	PLD(r0, #8)
+	PLD(r1, #8)
+	sub	r2, ip, magic1(r4)
+	cmp	ip, r3
+	itttt	eq
+
+	/* check for any zero bytes in first word */
+	biceq	r2, r2, ip
+	tsteq	r2, magic2(r4)
+	ldreq	ip, [r0], #4
+	ldreq	r3, [r1], #4
+	beq	4b
+2:
+	/* There's a zero or a different byte in the word */
+	SHFT2MSB	r0, ip, #24
+	SHFT2LSB	ip, ip, #8
+	cmp	r0, #1
+	it	cs
+	cmpcs	r0, r3, SHFT2MSB #24
+	it	eq
+	SHFT2LSBEQ r3, r3, #8
+	beq	2b
+	/* On a big-endian machine, r0 contains the desired byte in bits
+	 * 0-7; on a little-endian machine they are in bits 24-31.  In
+	 * both cases the other bits in r0 are all zero.  For r3 the
+	 * interesting byte is at the other end of the word, but the
+	 * other bits are not necessarily zero.  We need a signed result
+	 * representing the differnece in the unsigned bytes, so for the
+	 * little-endian case we can't just shift the interesting bits up.
+	 */
+#ifdef __ARMEB__
+	sub	r0, r0, r3, lsr #24
+#else
+	and	r3, r3, #255
+	/* No RSB instruction in Thumb2 */
+#ifdef __thumb2__
+	lsr	r0, r0, #24
+	sub	r0, r0, r3
+#else
+	rsb	r0, r3, r0, lsr #24
+#endif
+#endif
+	ldr	r4, [sp], #4
+	bx	lr
+
+.Lstrcmp_unaligned:
+	wp1 .req r0
+	wp2 .req r1
+	b1  .req r2
+	w1  .req r4
+	w2  .req r5
+	t1  .req ip
+	@ r3 is scratch
+
+	/* First of all, compare bytes until wp1(sp1) is word-aligned. */
+1:
+	tst	wp1, #3
+	beq	2f
+	ldrb	r2, [wp1], #1
+	ldrb	r3, [wp2], #1
+	cmp	r2, #1
+	it	cs
+	cmpcs	r2, r3
+	beq	1b
+	sub	r0, r2, r3
+	bx	lr
+
+2:
+	str	r5, [sp, #-4]!
+	str	r4, [sp, #-4]!
+	mov	b1, #1
+	orr	b1, b1, b1, lsl #8
+	orr	b1, b1, b1, lsl #16
+
+	and	t1, wp2, #3
+	bic	wp2, wp2, #3
+	ldr	w1, [wp1], #4
+	ldr	w2, [wp2], #4
+	cmp	t1, #2
+	beq	2f
+	bhi	3f
+
+	/* Critical inner Loop: Block with 3 bytes initial overlap */
+	.p2align	2
+1:
+	bic	t1, w1, #MSB
+	cmp	t1, w2, SHFT2LSB #8
+	sub	r3, w1, b1
+	bic	r3, r3, w1
+	bne	4f
+	ands	r3, r3, b1, lsl #7
+	it	eq
+	ldreq	w2, [wp2], #4
+	bne	5f
+	eor	t1, t1, w1
+	cmp	t1, w2, SHFT2MSB #24
+	bne	6f
+	ldr	w1, [wp1], #4
+	b	1b
+4:
+	SHFT2LSB	w2, w2, #8
+	b	8f
+
+5:
+#ifdef __ARMEB__
+	/* The syndrome value may contain false ones if the string ends
+	 * with the bytes 0x01 0x00
+	 */
+	tst	w1, #0xff000000
+	itt	ne
+	tstne	w1, #0x00ff0000
+	tstne	w1, #0x0000ff00
+	beq	7f
+#else
+	bics	r3, r3, #0xff000000
+	bne	7f
+#endif
+	ldrb	w2, [wp2]
+	SHFT2LSB	t1, w1, #24
+#ifdef __ARMEB__
+	lsl	w2, w2, #24
+#endif
+	b	8f
+
+6:
+	SHFT2LSB	t1, w1, #24
+	and	w2, w2, #LSB
+	b	8f
+
+	/* Critical inner Loop: Block with 2 bytes initial overlap */
+	.p2align	2
+2:
+	SHFT2MSB	t1, w1, #16
+	sub	r3, w1, b1
+	SHFT2LSB	t1, t1, #16
+	bic	r3, r3, w1
+	cmp	t1, w2, SHFT2LSB #16
+	bne	4f
+	ands	r3, r3, b1, lsl #7
+	it	eq
+	ldreq	w2, [wp2], #4
+	bne	5f
+	eor	t1, t1, w1
+	cmp	t1, w2, SHFT2MSB #16
+	bne	6f
+	ldr	w1, [wp1], #4
+	b	2b
+
+5:
+#ifdef __ARMEB__
+	/* The syndrome value may contain false ones if the string ends
+	 * with the bytes 0x01 0x00
+	 */
+	tst	w1, #0xff000000
+	it	ne
+	tstne	w1, #0x00ff0000
+	beq	7f
+#else
+	lsls	r3, r3, #16
+	bne	7f
+#endif
+	ldrh	w2, [wp2]
+	SHFT2LSB	t1, w1, #16
+#ifdef __ARMEB__
+	lsl	w2, w2, #16
+#endif
+	b	8f
+
+6:
+	SHFT2MSB	w2, w2, #16
+	SHFT2LSB	t1, w1, #16
+4:
+	SHFT2LSB	w2, w2, #16
+	b	8f
+
+	/* Critical inner Loop: Block with 1 byte initial overlap */
+	.p2align	2
+3:
+	and	t1, w1, #LSB
+	cmp	t1, w2, SHFT2LSB #24
+	sub	r3, w1, b1
+	bic	r3, r3, w1
+	bne	4f
+	ands	r3, r3, b1, lsl #7
+	it	eq
+	ldreq	w2, [wp2], #4
+	bne	5f
+	eor	t1, t1, w1
+	cmp	t1, w2, SHFT2MSB #8
+	bne	6f
+	ldr	w1, [wp1], #4
+	b	3b
+4:
+	SHFT2LSB	w2, w2, #24
+	b	8f
+5:
+	/* The syndrome value may contain false ones if the string ends
+	 * with the bytes 0x01 0x00
+	 */
+	tst	w1, #LSB
+	beq	7f
+	ldr	w2, [wp2], #4
+6:
+	SHFT2LSB	t1, w1, #8
+	bic	w2, w2, #MSB
+	b	8f
+7:
+	mov	r0, #0
+	ldr	r4, [sp], #4
+	ldr	r5, [sp], #4
+	bx	lr
+
+8:
+	and	r2, t1, #LSB
+	and	r0, w2, #LSB
+	cmp	r0, #1
+	it	cs
+	cmpcs	r0, r2
+	itt	eq
+	SHFT2LSBEQ	t1, t1, #8
+	SHFT2LSBEQ	w2, w2, #8
+	beq	8b
+	sub	r0, r2, r0
+	ldr	r4, [sp], #4
+	ldr	r5, [sp], #4
+	bx	lr
+END(strcmp)

libc/arch-arm/generic/generic.mk

@@ -0,0 +1,3 @@
+$(call libc-add-cpu-variant-src,MEMCPY,arch-arm/generic/bionic/memcpy.S)
+$(call libc-add-cpu-variant-src,MEMSET,arch-arm/generic/bionic/memset.S)
+$(call libc-add-cpu-variant-src,STRCMP,arch-arm/generic/bionic/strcmp.S)

libc/arch-arm/include/endian.h

@@ -1,10 +0,0 @@
-/*	$OpenBSD: endian.h,v 1.3 2005/12/13 00:35:23 millert Exp $	*/
-
-#ifdef __ARMEB__
-#define _BYTE_ORDER _BIG_ENDIAN
-#else
-#define _BYTE_ORDER _LITTLE_ENDIAN
-#endif
-#define	__STRICT_ALIGNMENT
-#include <sys/types.h>
-#include <sys/endian.h>

libc/arch-arm/include/machine/_types.h

@@ -35,17 +35,6 @@
 #ifndef _ARM__TYPES_H_
 #define _ARM__TYPES_H_
 
-
-#if !defined(__ARM_EABI__)
-/* the kernel defines size_t as unsigned int, but g++ wants it to be unsigned long */
-#define _SIZE_T
-#define _SSIZE_T
-#define _PTRDIFF_T
-typedef unsigned long  size_t;
-typedef long           ssize_t;
-typedef long           ptrdiff_t;
-#endif
-
 /* 7.18.1.1 Exact-width integer types */
 typedef	__signed char		__int8_t;
 typedef	unsigned char		__uint8_t;
@@ -98,6 +87,8 @@ typedef unsigned long		__psize_t;
 /* Standard system types */
 typedef int			__clock_t;
 typedef int			__clockid_t;
+typedef double			__double_t;
+typedef float			__float_t;
 typedef long			__ptrdiff_t;
 typedef	int			__time_t;
 typedef int			__timer_t;
@@ -116,10 +107,4 @@ typedef	int			__rune_t;
 typedef	void *			__wctrans_t;
 typedef	void *			__wctype_t;
 
-#ifdef __ARMEB__
-#define _BYTE_ORDER _BIG_ENDIAN
-#else
-#define _BYTE_ORDER _LITTLE_ENDIAN
-#endif
-
 #endif	/* _ARM__TYPES_H_ */

libc/arch-arm/include/machine/asm.h

@@ -70,7 +70,13 @@
 #define _ASM_TYPE_FUNCTION	#function
 #define _ASM_TYPE_OBJECT	#object
 #define _ENTRY(x) \
-	.text; _ALIGN_TEXT; .globl x; .type x,_ASM_TYPE_FUNCTION; x:
+	.text; _ALIGN_TEXT; .globl x; .type x,_ASM_TYPE_FUNCTION; x: .fnstart
+
+#define _ASM_SIZE(x)	.size x, .-x;
+
+#define _END(x) \
+	.fnend; \
+	_ASM_SIZE(x)
 
 #ifdef GPROF
 # ifdef __ELF__
@@ -86,8 +92,16 @@
 
 #define	ENTRY(y)	_ENTRY(_C_LABEL(y)); _PROF_PROLOGUE
 #define	ENTRY_NP(y)	_ENTRY(_C_LABEL(y))
+#define	END(y)		_END(_C_LABEL(y))
 #define	ASENTRY(y)	_ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE
 #define	ASENTRY_NP(y)	_ENTRY(_ASM_LABEL(y))
+#define	ASEND(y)	_END(_ASM_LABEL(y))
+
+#ifdef __ELF__
+#define ENTRY_PRIVATE(y)  ENTRY(y); .hidden _C_LABEL(y)
+#else
+#define ENTRY_PRIVATE(y)  ENTRY(y)
+#endif
 
 #define	ASMSTR		.asciz
 

libc/arch-arm/include/machine/cpu-features.h

@@ -185,6 +185,7 @@
 #endif
 
 /* Assembly-only macros */
+#ifdef __ASSEMBLY__
 
 /* define a handy PLD(address) macro since the cache preload
  * is an optional opcode
@@ -195,4 +196,6 @@
 #  define  PLD(reg,offset)    /* nothing */
 #endif
 
+#endif /* ! __ASSEMBLY__ */
+
 #endif /* _ARM_MACHINE_CPU_FEATURES_H */

libc/arch-arm/include/machine/elf_machdep.h

@@ -0,0 +1,138 @@
+/*	$NetBSD: elf_machdep.h,v 1.10 2012/08/05 04:12:46 matt Exp $	*/
+
+#ifndef _ARM_ELF_MACHDEP_H_
+#define _ARM_ELF_MACHDEP_H_
+
+#if defined(__ARMEB__)
+#define ELF32_MACHDEP_ENDIANNESS	ELFDATA2MSB
+#else
+#define ELF32_MACHDEP_ENDIANNESS	ELFDATA2LSB
+#endif
+
+#define ELF64_MACHDEP_ENDIANNESS	XXX	/* break compilation */
+#define ELF64_MACHDEP_ID_CASES                                          \
+		/* no 64-bit ELF machine types supported */
+
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_ARM_RELEXEC		0x00000001
+#define EF_ARM_HASENTRY		0x00000002
+#define EF_ARM_INTERWORK	0x00000004 /* GNU binutils 000413 */
+#define EF_ARM_SYMSARESORTED	0x00000004 /* ARM ELF A08 */
+#define EF_ARM_APCS_26		0x00000008 /* GNU binutils 000413 */
+#define EF_ARM_DYNSYMSUSESEGIDX	0x00000008 /* ARM ELF B01 */
+#define EF_ARM_APCS_FLOAT	0x00000010 /* GNU binutils 000413 */
+#define EF_ARM_MAPSYMSFIRST	0x00000010 /* ARM ELF B01 */
+#define EF_ARM_PIC		0x00000020
+#define EF_ARM_ALIGN8		0x00000040 /* 8-bit structure alignment.  */
+#define EF_ARM_NEW_ABI		0x00000080
+#define EF_ARM_OLD_ABI		0x00000100
+#define EF_ARM_SOFT_FLOAT	0x00000200
+#define EF_ARM_EABIMASK		0xff000000
+#define	EF_ARM_EABI_VER1	0x01000000
+#define	EF_ARM_EABI_VER2	0x02000000
+#define	EF_ARM_EABI_VER3	0x03000000
+#define	EF_ARM_EABI_VER4	0x04000000
+#define	EF_ARM_EABI_VER5	0x05000000
+
+#define	ELF32_MACHDEP_ID_CASES						\
+		case EM_ARM:						\
+			break;
+
+#define	ELF32_MACHDEP_ID	EM_ARM
+
+#define ARCH_ELFSIZE		32	/* MD native binary size */
+
+/* Processor specific relocation types */
+
+#define R_ARM_NONE		0
+#define R_ARM_PC24		1
+#define R_ARM_ABS32		2
+#define R_ARM_REL32		3
+#define R_ARM_PC13		4
+#define R_ARM_ABS16		5
+#define R_ARM_ABS12		6
+#define R_ARM_THM_ABS5		7
+#define R_ARM_ABS8		8
+#define R_ARM_SBREL32		9
+#define R_ARM_THM_PC22		10
+#define R_ARM_THM_PC8		11
+#define R_ARM_AMP_VCALL9	12
+#define R_ARM_SWI24		13
+#define R_ARM_THM_SWI8		14
+#define R_ARM_XPC25		15
+#define R_ARM_THM_XPC22		16
+
+/* TLS relocations */
+#define R_ARM_TLS_DTPMOD32	17	/* ID of module containing symbol */
+#define R_ARM_TLS_DTPOFF32	18	/* Offset in TLS block */
+#define R_ARM_TLS_TPOFF32	19	/* Offset in static TLS block */
+
+/* 20-31 are reserved for ARM Linux. */
+#define R_ARM_COPY		20
+#define R_ARM_GLOB_DAT		21
+#define	R_ARM_JUMP_SLOT		22
+#define R_ARM_RELATIVE		23
+#define	R_ARM_GOTOFF		24
+#define R_ARM_GOTPC		25
+#define R_ARM_GOT32		26
+#define R_ARM_PLT32		27
+
+#define R_ARM_ALU_PCREL_7_0	32
+#define R_ARM_ALU_PCREL_15_8	33
+#define R_ARM_ALU_PCREL_23_15	34
+#define R_ARM_ALU_SBREL_11_0	35
+#define R_ARM_ALU_SBREL_19_12	36
+#define R_ARM_ALU_SBREL_27_20	37
+
+/* 96-111 are reserved to G++. */
+#define R_ARM_GNU_VTENTRY	100
+#define R_ARM_GNU_VTINHERIT	101
+#define R_ARM_THM_PC11		102
+#define R_ARM_THM_PC9		103
+
+/* More TLS relocations */
+#define R_ARM_TLS_GD32		104	/* PC-rel 32 bit for global dynamic */
+#define R_ARM_TLS_LDM32		105	/* PC-rel 32 bit for local dynamic */
+#define R_ARM_TLS_LDO32		106	/* 32 bit offset relative to TLS */
+#define R_ARM_TLS_IE32		107	/* PC-rel 32 bit for GOT entry of */
+#define R_ARM_TLS_LE32		108
+#define R_ARM_TLS_LDO12		109
+#define R_ARM_TLS_LE12		110
+#define R_ARM_TLS_IE12GP	111
+
+/* 112-127 are reserved for private experiments. */
+
+#define R_ARM_RXPC25		249
+#define R_ARM_RSBREL32		250
+#define R_ARM_THM_RPC22		251
+#define R_ARM_RREL32		252
+#define R_ARM_RABS32		253
+#define R_ARM_RPC24		254
+#define R_ARM_RBASE		255
+
+#define R_TYPE(name)		__CONCAT(R_ARM_,name)
+
+/* Processor specific program header flags */
+#define PF_ARM_SB		0x10000000
+#define PF_ARM_PI		0x20000000
+#define PF_ARM_ENTRY		0x80000000
+
+/* Processor specific section header flags */
+#define SHF_ENTRYSECT		0x10000000
+#define SHF_COMDEF		0x80000000
+
+/* Processor specific symbol types */
+#define STT_ARM_TFUNC		STT_LOPROC
+
+#ifdef _KERNEL
+#ifdef ELFSIZE
+#define	ELF_MD_PROBE_FUNC	ELFNAME2(arm_netbsd,probe)
+#endif
+
+struct exec_package;
+
+int arm_netbsd_elf32_probe(struct lwp *, struct exec_package *, void *, char *,
+	vaddr_t *);
+#endif
+
+#endif /* _ARM_ELF_MACHDEP_H_ */

libc/arch-arm/include/machine/endian.h

@@ -0,0 +1,89 @@
+/*	$OpenBSD: endian.h,v 1.3 2005/12/13 00:35:23 millert Exp $	*/
+
+/*
+ * Copyright (C) 2010 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ENDIAN_H_
+#define _ARM_ENDIAN_H_
+
+#ifdef __GNUC__
+
+/*
+ * REV and REV16 weren't available on ARM5 or ARM4.
+ * We don't include <machine/cpu-features.h> because it pollutes the
+ * namespace with macros like PLD.
+ */
+#if !defined __ARM_ARCH_5__ && !defined __ARM_ARCH_5T__ && \
+    !defined __ARM_ARCH_5TE__ && !defined __ARM_ARCH_5TEJ__ && \
+    !defined __ARM_ARCH_4T__ && !defined __ARM_ARCH_4__
+
+/* According to RealView Assembler User's Guide, REV and REV16 are available
+ * in Thumb code and 16-bit instructions when used in Thumb-2 code.
+ *
+ * REV Rd, Rm
+ *   Rd and Rm must both be Lo registers.
+ *
+ * REV16 Rd, Rm
+ *   Rd and Rm must both be Lo registers.
+ *
+ * The +l constraint takes care of this without constraining us in ARM mode.
+ */
+#define __swap16md(x) ({                                        \
+    register u_int16_t _x = (x);                                \
+    __asm volatile ("rev16 %0, %0" : "+l" (_x));                \
+    _x;                                                         \
+})
+
+#define __swap32md(x) ({                                        \
+    register u_int32_t _x = (x);                                \
+    __asm volatile ("rev %0, %0" : "+l" (_x));                  \
+    _x;                                                         \
+})
+
+#define __swap64md(x) ({                                        \
+    u_int64_t _swap64md_x = (x);                                \
+    (u_int64_t) __swap32md(_swap64md_x >> 32) |                 \
+        (u_int64_t) __swap32md(_swap64md_x & 0xffffffff) << 32; \
+})
+
+/* Tell sys/endian.h we have MD variants of the swap macros.  */
+#define MD_SWAP
+
+#endif  /* __ARM_ARCH__ */
+#endif  /* __GNUC__ */
+
+#if defined(__ARMEB__)
+#define _BYTE_ORDER _BIG_ENDIAN
+#else
+#define _BYTE_ORDER _LITTLE_ENDIAN
+#endif
+#define __STRICT_ALIGNMENT
+#include <sys/types.h>
+#include <sys/endian.h>
+
+#endif  /* !_ARM_ENDIAN_H_ */

libc/arch-arm/krait/bionic/memcpy.S

@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2008 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* Assumes neon instructions and a cache line size of 32 bytes. */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+/*
+ * This code assumes it is running on a processor that supports all arm v7
+ * instructions, that supports neon instructions, and that has a 32 byte
+ * cache line.
+ */
+
+        .text
+        .fpu    neon
+
+#define CACHE_LINE_SIZE     32
+
+ENTRY(memcpy)
+        .save       {r0, lr}
+        /* start preloading as early as possible */
+        pld         [r1, #(CACHE_LINE_SIZE*0)]
+        stmfd       sp!, {r0, lr}
+        pld         [r1, #(CACHE_LINE_SIZE*2)]
+
+        /* do we have at least 16-bytes to copy (needed for alignment below) */
+        cmp         r2, #16
+        blo         5f
+
+        /* align destination to cache-line for the write-buffer */
+        rsb         r3, r0, #0
+        ands        r3, r3, #0xF
+        beq         0f
+
+        /* copy up to 15-bytes (count in r3) */
+        sub         r2, r2, r3
+        movs        ip, r3, lsl #31
+        ldrmib      lr, [r1], #1
+        strmib      lr, [r0], #1
+        ldrcsb      ip, [r1], #1
+        ldrcsb      lr, [r1], #1
+        strcsb      ip, [r0], #1
+        strcsb      lr, [r0], #1
+        movs        ip, r3, lsl #29
+        bge         1f
+        // copies 4 bytes, destination 32-bits aligned
+        vld4.8      {d0[0], d1[0], d2[0], d3[0]}, [r1]!
+        vst4.8      {d0[0], d1[0], d2[0], d3[0]}, [r0, :32]!
+1:      bcc         2f
+        // copies 8 bytes, destination 64-bits aligned
+        vld1.8      {d0}, [r1]!
+        vst1.8      {d0}, [r0, :64]!
+2:
+
+0:      /* preload immediately the next cache line, which we may need */
+        pld         [r1, #(CACHE_LINE_SIZE*0)]
+        pld         [r1, #(CACHE_LINE_SIZE*2)]
+
+        /* make sure we have at least 64 bytes to copy */
+        subs        r2, r2, #64
+        blo         2f
+
+        /* Preload all the cache lines we need.
+         * NOTE: The number of pld below depends on CACHE_LINE_SIZE,
+         * ideally we would increase the distance in the main loop to
+         * avoid the goofy code below. In practice this doesn't seem to make
+         * a big difference.
+         * NOTE: The value CACHE_LINE_SIZE * 8 was chosen through
+         * experimentation.
+         */
+        pld         [r1, #(CACHE_LINE_SIZE*4)]
+        pld         [r1, #(CACHE_LINE_SIZE*6)]
+        pld         [r1, #(CACHE_LINE_SIZE*8)]
+
+1:      /* The main loop copies 64 bytes at a time */
+        vld1.8      {d0  - d3},   [r1]!
+        vld1.8      {d4  - d7},   [r1]!
+        pld         [r1, #(CACHE_LINE_SIZE*8)]
+        subs        r2, r2, #64
+        vst1.8      {d0  - d3},   [r0, :128]!
+        vst1.8      {d4  - d7},   [r0, :128]!
+        bhs         1b
+
+2:      /* fix-up the remaining count and make sure we have >= 32 bytes left */
+        add         r2, r2, #64
+        subs        r2, r2, #32
+        blo         4f
+
+3:      /* 32 bytes at a time. These cache lines were already preloaded */
+        vld1.8      {d0 - d3},  [r1]!
+        subs        r2, r2, #32
+        vst1.8      {d0 - d3},  [r0, :128]!
+        bhs         3b
+4:      /* less than 32 left */
+        add         r2, r2, #32
+        tst         r2, #0x10
+        beq         5f
+        // copies 16 bytes, 128-bits aligned
+        vld1.8      {d0, d1}, [r1]!
+        vst1.8      {d0, d1}, [r0, :128]!
+
+5:      /* copy up to 15-bytes (count in r2) */
+        movs        ip, r2, lsl #29
+        bcc         1f
+        vld1.8      {d0}, [r1]!
+        vst1.8      {d0}, [r0]!
+1:      bge         2f
+        vld4.8      {d0[0], d1[0], d2[0], d3[0]}, [r1]!
+        vst4.8      {d0[0], d1[0], d2[0], d3[0]}, [r0]!
+2:      movs        ip, r2, lsl #31
+        ldrmib      r3, [r1], #1
+        ldrcsb      ip, [r1], #1
+        ldrcsb      lr, [r1], #1
+        strmib      r3, [r0], #1
+        strcsb      ip, [r0], #1
+        strcsb      lr, [r0], #1
+
+        ldmfd       sp!, {r0, lr}
+        bx          lr
+END(memcpy)

libc/arch-arm/krait/bionic/memset.S

@@ -25,50 +25,57 @@
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
-#include <errno.h>
-#include <signal.h>
-#include <string.h>
-#include <time.h>
 
-int __rt_sigtimedwait(const sigset_t *uthese, siginfo_t *uinfo, const struct timespec *uts, size_t sigsetsize);
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
 
-/* ok, this is really subtle: <asm/signal.h> defines sigset_t differently
- * when you're in the kernel or in the C library.
- *
- * in the kernel, this is an array of 2 32-bit unsigned longs
- * in the C library, this is a single 32-bit unsigned long
- *
- * moreover, the kernel implementation of rt_sigtimedwait doesn't
- * accept anything except kernel-sized signal sets (probably a bug !)
- *
- * we thus need to create a fake kernel sigset !!
+/*
+ * This code assumes it is running on a processor that supports all arm v7
+ * instructions, that supports neon instructions, and that supports
+ * unaligned neon instruction accesses to memory.
  */
 
-int sigwait(const sigset_t *set, int *sig)
-{
-    int  ret;
-    /* use a union to get rid of aliasing warnings */
-    union {
-      unsigned long  kernel_sigset[2];
-      sigset_t       dummy_sigset;
-    } u;
+    .fpu    neon
 
-    u.kernel_sigset[0] = *set;
-    u.kernel_sigset[1] = 0;  /* no real-time signals supported ? */
-    for (;;)
-    {
-     /* __rt_sigtimedwait can return EAGAIN or EINTR, we need to loop
-      * around them since sigwait is only allowed to return EINVAL
-      */
-      ret = __rt_sigtimedwait ( &u.dummy_sigset, NULL, NULL, sizeof(u.kernel_sigset));
-      if (ret >= 0)
-        break;
+ENTRY(bzero)
+        mov     r2, r1
+        mov     r1, #0
+END(bzero)
 
-      if (errno != EAGAIN && errno != EINTR)
-        return errno;
-    }
+/* memset() returns its first argument.  */
+ENTRY(memset)
+        .save       {r0}
+        stmfd       sp!, {r0}
 
-    *sig = ret;
-    return 0;
-}
+        vdup.8      q0, r1
 
+        /* make sure we have at least 32 bytes to write */
+        subs        r2, r2, #32
+        blo         2f
+        vmov        q1, q0
+
+1:      /* The main loop writes 32 bytes at a time */
+        subs        r2, r2, #32
+        vst1.8      {d0 - d3}, [r0]!
+        bhs         1b
+
+2:      /* less than 32 left */
+        add         r2, r2, #32
+        tst         r2, #0x10
+        beq         3f
+
+        // writes 16 bytes, 128-bits aligned
+        vst1.8      {d0, d1}, [r0]!
+3:      /* write up to 15-bytes (count in r2) */
+        movs        ip, r2, lsl #29
+        bcc         1f
+        vst1.8      {d0}, [r0]!
+1:      bge         2f
+        vst1.32     {d0[0]}, [r0]!
+2:      movs        ip, r2, lsl #31
+        strmib      r1, [r0], #1
+        strcsb      r1, [r0], #1
+        strcsb      r1, [r0], #1
+        ldmfd       sp!, {r0}
+        bx          lr
+END(memset)

libc/arch-arm/krait/bionic/strcmp.S

@@ -0,0 +1,477 @@
+/*
+ * Copyright (c) 2013 ARM Ltd
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the company may not be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/cpu-features.h>
+#include <machine/asm.h>
+
+#ifdef __ARMEB__
+#define S2LOMEM lsl
+#define S2LOMEMEQ lsleq
+#define S2HIMEM lsr
+#define MSB 0x000000ff
+#define LSB 0xff000000
+#define BYTE0_OFFSET 24
+#define BYTE1_OFFSET 16
+#define BYTE2_OFFSET 8
+#define BYTE3_OFFSET 0
+#else /* not  __ARMEB__ */
+#define S2LOMEM lsr
+#define S2LOMEMEQ lsreq
+#define S2HIMEM lsl
+#define BYTE0_OFFSET 0
+#define BYTE1_OFFSET 8
+#define BYTE2_OFFSET 16
+#define BYTE3_OFFSET 24
+#define MSB 0xff000000
+#define LSB 0x000000ff
+#endif /* not  __ARMEB__ */
+
+.syntax         unified
+
+#if defined (__thumb__)
+        .thumb
+        .thumb_func
+#endif
+
+ENTRY(strcmp)
+      /* Use LDRD whenever possible.  */
+
+/* The main thing to look out for when comparing large blocks is that
+   the loads do not cross a page boundary when loading past the index
+   of the byte with the first difference or the first string-terminator.
+
+   For example, if the strings are identical and the string-terminator
+   is at index k, byte by byte comparison will not load beyond address
+   s1+k and s2+k; word by word comparison may load up to 3 bytes beyond
+   k; double word - up to 7 bytes.  If the load of these bytes crosses
+   a page boundary, it might cause a memory fault (if the page is not mapped)
+   that would not have happened in byte by byte comparison.
+
+   If an address is (double) word aligned, then a load of a (double) word
+   from that address will not cross a page boundary.
+   Therefore, the algorithm below considers word and double-word alignment
+   of strings separately.  */
+
+/* High-level description of the algorithm.
+
+   * The fast path: if both strings are double-word aligned,
+     use LDRD to load two words from each string in every loop iteration.
+   * If the strings have the same offset from a word boundary,
+     use LDRB to load and compare byte by byte until
+     the first string is aligned to a word boundary (at most 3 bytes).
+     This is optimized for quick return on short unaligned strings.
+   * If the strings have the same offset from a double-word boundary,
+     use LDRD to load two words from each string in every loop iteration, as in the fast path.
+   * If the strings do not have the same offset from a double-word boundary,
+     load a word from the second string before the loop to initialize the queue.
+     Use LDRD to load two words from every string in every loop iteration.
+     Inside the loop, load the second word from the second string only after comparing
+     the first word, using the queued value, to guarantee safety across page boundaries.
+   * If the strings do not have the same offset from a word boundary,
+     use LDR and a shift queue. Order of loads and comparisons matters,
+     similarly to the previous case.
+
+   * Use UADD8 and SEL to compare words, and use REV and CLZ to compute the return value.
+   * The only difference between ARM and Thumb modes is the use of CBZ instruction.
+   * The only difference between big and little endian is the use of REV in little endian
+     to compute the return value, instead of MOV.
+*/
+
+        .macro m_cbz reg label
+#ifdef __thumb2__
+        cbz     \reg, \label
+#else   /* not defined __thumb2__ */
+        cmp     \reg, #0
+        beq     \label
+#endif /* not defined __thumb2__ */
+        .endm /* m_cbz */
+
+        .macro m_cbnz reg label
+#ifdef __thumb2__
+        cbnz    \reg, \label
+#else   /* not defined __thumb2__ */
+        cmp     \reg, #0
+        bne     \label
+#endif /* not defined __thumb2__ */
+        .endm /* m_cbnz */
+
+        .macro  init
+        /* Macro to save temporary registers and prepare magic values.  */
+        subs    sp, sp, #16
+        strd    r4, r5, [sp, #8]
+        strd    r6, r7, [sp]
+        mvn     r6, #0  /* all F */
+        mov     r7, #0  /* all 0 */
+        .endm   /* init */
+
+        .macro  magic_compare_and_branch w1 w2 label
+        /* Macro to compare registers w1 and w2 and conditionally branch to label.  */
+        cmp     \w1, \w2        /* Are w1 and w2 the same?  */
+        magic_find_zero_bytes \w1
+        it      eq
+        cmpeq   ip, #0          /* Is there a zero byte in w1?  */
+        bne     \label
+        .endm /* magic_compare_and_branch */
+
+        .macro  magic_find_zero_bytes w1
+        /* Macro to find all-zero bytes in w1, result is in ip.  */
+#if (defined (__ARM_FEATURE_DSP))
+        uadd8   ip, \w1, r6
+        sel     ip, r7, r6
+#else /* not defined (__ARM_FEATURE_DSP) */
+        /* __ARM_FEATURE_DSP is not defined for some Cortex-M processors.
+        Coincidently, these processors only have Thumb-2 mode, where we can use the
+        the (large) magic constant available directly as an immediate in instructions.
+        Note that we cannot use the magic constant in ARM mode, where we need
+        to create the constant in a register.  */
+        sub     ip, \w1, #0x01010101
+        bic     ip, ip, \w1
+        and     ip, ip, #0x80808080
+#endif /* not defined (__ARM_FEATURE_DSP) */
+        .endm /* magic_find_zero_bytes */
+
+        .macro  setup_return w1 w2
+#ifdef __ARMEB__
+        mov     r1, \w1
+        mov     r2, \w2
+#else /* not  __ARMEB__ */
+        rev     r1, \w1
+        rev     r2, \w2
+#endif /* not  __ARMEB__ */
+        .endm /* setup_return */
+
+        pld [r0, #0]
+        pld [r1, #0]
+
+        /* Are both strings double-word aligned?  */
+        orr     ip, r0, r1
+        tst     ip, #7
+        bne     do_align
+
+        /* Fast path.  */
+        init
+
+doubleword_aligned:
+
+        /* Get here when the strings to compare are double-word aligned.  */
+        /* Compare two words in every iteration.  */
+        .p2align        2
+2:
+        pld [r0, #16]
+        pld [r1, #16]
+
+        /* Load the next double-word from each string.  */
+        ldrd    r2, r3, [r0], #8
+        ldrd    r4, r5, [r1], #8
+
+        magic_compare_and_branch w1=r2, w2=r4, label=return_24
+        magic_compare_and_branch w1=r3, w2=r5, label=return_35
+        b       2b
+
+do_align:
+        /* Is the first string word-aligned?  */
+        ands    ip, r0, #3
+        beq     word_aligned_r0
+
+        /* Fast compare byte by byte until the first string is word-aligned.  */
+        /* The offset of r0 from a word boundary is in ip. Thus, the number of bytes
+        to read until the next word boundary is 4-ip.  */
+        bic     r0, r0, #3
+        ldr     r2, [r0], #4
+        lsls    ip, ip, #31
+        beq     byte2
+        bcs     byte3
+
+byte1:
+        ldrb    ip, [r1], #1
+        uxtb    r3, r2, ror #BYTE1_OFFSET
+        subs    ip, r3, ip
+        bne     fast_return
+        m_cbz   reg=r3, label=fast_return
+
+byte2:
+        ldrb    ip, [r1], #1
+        uxtb    r3, r2, ror #BYTE2_OFFSET
+        subs    ip, r3, ip
+        bne     fast_return
+        m_cbz   reg=r3, label=fast_return
+
+byte3:
+        ldrb    ip, [r1], #1
+        uxtb    r3, r2, ror #BYTE3_OFFSET
+        subs    ip, r3, ip
+        bne     fast_return
+        m_cbnz  reg=r3, label=word_aligned_r0
+
+fast_return:
+        mov     r0, ip
+        bx      lr
+
+word_aligned_r0:
+        init
+        /* The first string is word-aligned.  */
+        /* Is the second string word-aligned?  */
+        ands    ip, r1, #3
+        bne     strcmp_unaligned
+
+word_aligned:
+        /* The strings are word-aligned. */
+        /* Is the first string double-word aligned?  */
+        tst     r0, #4
+        beq     doubleword_aligned_r0
+
+        /* If r0 is not double-word aligned yet, align it by loading
+        and comparing the next word from each string.  */
+        ldr     r2, [r0], #4
+        ldr     r4, [r1], #4
+        magic_compare_and_branch w1=r2 w2=r4 label=return_24
+
+doubleword_aligned_r0:
+        /* Get here when r0 is double-word aligned.  */
+        /* Is r1 doubleword_aligned?  */
+        tst     r1, #4
+        beq     doubleword_aligned
+
+        /* Get here when the strings to compare are word-aligned,
+        r0 is double-word aligned, but r1 is not double-word aligned.  */
+
+        /* Initialize the queue.  */
+        ldr     r5, [r1], #4
+
+        /* Compare two words in every iteration.  */
+        .p2align        2
+3:
+        pld [r0, #16]
+        pld [r1, #16]
+
+        /* Load the next double-word from each string and compare.  */
+        ldrd    r2, r3, [r0], #8
+        magic_compare_and_branch w1=r2 w2=r5 label=return_25
+        ldrd    r4, r5, [r1], #8
+        magic_compare_and_branch w1=r3 w2=r4 label=return_34
+        b       3b
+
+        .macro miscmp_word offsetlo offsethi
+        /* Macro to compare misaligned strings.  */
+        /* r0, r1 are word-aligned, and at least one of the strings
+        is not double-word aligned.  */
+        /* Compare one word in every loop iteration.  */
+        /* OFFSETLO is the original bit-offset of r1 from a word-boundary,
+        OFFSETHI is 32 - OFFSETLO (i.e., offset from the next word).  */
+
+        /* Initialize the shift queue.  */
+        ldr     r5, [r1], #4
+
+        /* Compare one word from each string in every loop iteration.  */
+        .p2align        2
+7:
+        ldr     r3, [r0], #4
+        S2LOMEM r5, r5, #\offsetlo
+        magic_find_zero_bytes w1=r3
+        cmp     r7, ip, S2HIMEM #\offsetlo
+        and     r2, r3, r6, S2LOMEM #\offsetlo
+        it      eq
+        cmpeq   r2, r5
+        bne     return_25
+        ldr     r5, [r1], #4
+        cmp     ip, #0
+        eor r3, r2, r3
+        S2HIMEM r2, r5, #\offsethi
+        it      eq
+        cmpeq   r3, r2
+        bne     return_32
+        b       7b
+        .endm /* miscmp_word */
+
+strcmp_unaligned:
+        /* r0 is word-aligned, r1 is at offset ip from a word.  */
+        /* Align r1 to the (previous) word-boundary.  */
+        bic     r1, r1, #3
+
+        /* Unaligned comparison word by word using LDRs. */
+        cmp     ip, #2
+        beq     miscmp_word_16                    /* If ip == 2.  */
+        bge     miscmp_word_24                    /* If ip == 3.  */
+        miscmp_word offsetlo=8 offsethi=24        /* If ip == 1.  */
+miscmp_word_24:  miscmp_word offsetlo=24 offsethi=8
+
+
+return_32:
+        setup_return w1=r3, w2=r2
+        b       do_return
+return_34:
+        setup_return w1=r3, w2=r4
+        b       do_return
+return_25:
+        setup_return w1=r2, w2=r5
+        b       do_return
+return_35:
+        setup_return w1=r3, w2=r5
+        b       do_return
+return_24:
+        setup_return w1=r2, w2=r4
+
+do_return:
+
+#ifdef __ARMEB__
+        mov     r0, ip
+#else /* not  __ARMEB__ */
+        rev     r0, ip
+#endif /* not  __ARMEB__ */
+
+        /* Restore temporaries early, before computing the return value.  */
+        ldrd    r6, r7, [sp]
+        ldrd    r4, r5, [sp, #8]
+        adds    sp, sp, #16
+
+        /* There is a zero or a different byte between r1 and r2.  */
+        /* r0 contains a mask of all-zero bytes in r1.  */
+        /* Using r0 and not ip here because cbz requires low register.  */
+        m_cbz   reg=r0, label=compute_return_value
+        clz     r0, r0
+        /* r0 contains the number of bits on the left of the first all-zero byte in r1.  */
+        rsb     r0, r0, #24
+        /* Here, r0 contains the number of bits on the right of the first all-zero byte in r1.  */
+        lsr     r1, r1, r0
+        lsr     r2, r2, r0
+
+compute_return_value:
+        movs    r0, #1
+        cmp     r1, r2
+        /* The return value is computed as follows.
+        If r1>r2 then (C==1 and Z==0) and LS doesn't hold and r0 is #1 at return.
+        If r1<r2 then (C==0 and Z==0) and we execute SBC with carry_in=0,
+        which means r0:=r0-r0-1 and r0 is #-1 at return.
+        If r1=r2 then (C==1 and Z==1) and we execute SBC with carry_in=1,
+        which means r0:=r0-r0 and r0 is #0 at return.
+        (C==0 and Z==1) cannot happen because the carry bit is "not borrow".  */
+        it      ls
+        sbcls   r0, r0, r0
+        bx      lr
+
+    /* The code from the previous version of strcmp.S handles this
+     * particular case (the second string is 2 bytes off a word alignment)
+     * faster than any current version. In this very specific case, use the
+     * previous version. See bionic/libc/arch-arm/cortex-a15/bionic/strcmp.S
+     * for the unedited version of this code.
+     */
+miscmp_word_16:
+	wp1 .req r0
+	wp2 .req r1
+	b1  .req r2
+	w1  .req r4
+	w2  .req r5
+	t1  .req ip
+	@ r3 is scratch
+
+    /* At this point, wp1 (r0) has already been word-aligned. */
+2:
+	mov	b1, #1
+	orr	b1, b1, b1, lsl #8
+	orr	b1, b1, b1, lsl #16
+
+	and	t1, wp2, #3
+	bic	wp2, wp2, #3
+	ldr	w1, [wp1], #4
+	ldr	w2, [wp2], #4
+
+	/* Critical inner Loop: Block with 2 bytes initial overlap */
+	.p2align	2
+2:
+	S2HIMEM	t1, w1, #16
+	sub	r3, w1, b1
+	S2LOMEM	t1, t1, #16
+	bic	r3, r3, w1
+	cmp	t1, w2, S2LOMEM #16
+	bne	4f
+	ands	r3, r3, b1, lsl #7
+	it	eq
+	ldreq	w2, [wp2], #4
+	bne	5f
+	eor	t1, t1, w1
+	cmp	t1, w2, S2HIMEM #16
+	bne	6f
+	ldr	w1, [wp1], #4
+	b	2b
+
+5:
+#ifdef __ARMEB__
+	/* The syndrome value may contain false ones if the string ends
+	 * with the bytes 0x01 0x00
+	 */
+	tst	w1, #0xff000000
+	it	ne
+	tstne	w1, #0x00ff0000
+	beq	7f
+#else
+	lsls	r3, r3, #16
+	bne	7f
+#endif
+	ldrh	w2, [wp2]
+	S2LOMEM	t1, w1, #16
+#ifdef __ARMEB__
+	lsl	w2, w2, #16
+#endif
+	b	8f
+
+6:
+	S2HIMEM	w2, w2, #16
+	S2LOMEM	t1, w1, #16
+4:
+	S2LOMEM	w2, w2, #16
+	b	8f
+
+7:
+	mov	r0, #0
+
+    /* Restore registers and stack. */
+    ldrd    r6, r7, [sp]
+    ldrd    r4, r5, [sp, #8]
+    adds    sp, sp, #16
+
+	bx	lr
+
+8:
+	and	r2, t1, #LSB
+	and	r0, w2, #LSB
+	cmp	r0, #1
+	it	cs
+	cmpcs	r0, r2
+	itt	eq
+	S2LOMEMEQ	t1, t1, #8
+	S2LOMEMEQ	w2, w2, #8
+	beq	8b
+	sub	r0, r2, r0
+
+    /* Restore registers and stack. */
+    ldrd    r6, r7, [sp]
+    ldrd    r4, r5, [sp, #8]
+    adds    sp, sp, #16
+
+	bx	lr
+END(strcmp)

libc/arch-arm/krait/krait.mk

@@ -0,0 +1,5 @@
+$(call libc-add-cpu-variant-src,MEMCPY,arch-arm/krait/bionic/memcpy.S)
+$(call libc-add-cpu-variant-src,MEMSET,arch-arm/krait/bionic/memset.S)
+$(call libc-add-cpu-variant-src,STRCMP,arch-arm/krait/bionic/strcmp.S)
+
+include bionic/libc/arch-arm/generic/generic.mk

libc/arch-arm/syscalls.mk

@@ -4,6 +4,7 @@ syscall_src += arch-arm/syscalls/_exit.S
 syscall_src += arch-arm/syscalls/_exit_thread.S
 syscall_src += arch-arm/syscalls/__fork.S
 syscall_src += arch-arm/syscalls/__waitid.S
+syscall_src += arch-arm/syscalls/wait4.S
 syscall_src += arch-arm/syscalls/__sys_clone.S
 syscall_src += arch-arm/syscalls/execve.S
 syscall_src += arch-arm/syscalls/__setuid.S
@@ -14,9 +15,11 @@ syscall_src += arch-arm/syscalls/getegid.S
 syscall_src += arch-arm/syscalls/getresuid.S
 syscall_src += arch-arm/syscalls/getresgid.S
 syscall_src += arch-arm/syscalls/gettid.S
+syscall_src += arch-arm/syscalls/readahead.S
 syscall_src += arch-arm/syscalls/getgroups.S
 syscall_src += arch-arm/syscalls/getpgid.S
 syscall_src += arch-arm/syscalls/getppid.S
+syscall_src += arch-arm/syscalls/getsid.S
 syscall_src += arch-arm/syscalls/setsid.S
 syscall_src += arch-arm/syscalls/setgid.S
 syscall_src += arch-arm/syscalls/__setreuid.S
@@ -41,8 +44,8 @@ syscall_src += arch-arm/syscalls/sigaltstack.S
 syscall_src += arch-arm/syscalls/acct.S
 syscall_src += arch-arm/syscalls/read.S
 syscall_src += arch-arm/syscalls/write.S
-syscall_src += arch-arm/syscalls/__pread64.S
-syscall_src += arch-arm/syscalls/__pwrite64.S
+syscall_src += arch-arm/syscalls/pread64.S
+syscall_src += arch-arm/syscalls/pwrite64.S
 syscall_src += arch-arm/syscalls/__open.S
 syscall_src += arch-arm/syscalls/__openat.S
 syscall_src += arch-arm/syscalls/close.S
@@ -57,6 +60,8 @@ syscall_src += arch-arm/syscalls/mprotect.S
 syscall_src += arch-arm/syscalls/madvise.S
 syscall_src += arch-arm/syscalls/mlock.S
 syscall_src += arch-arm/syscalls/munlock.S
+syscall_src += arch-arm/syscalls/mlockall.S
+syscall_src += arch-arm/syscalls/munlockall.S
 syscall_src += arch-arm/syscalls/mincore.S
 syscall_src += arch-arm/syscalls/__ioctl.S
 syscall_src += arch-arm/syscalls/readv.S
@@ -70,6 +75,7 @@ syscall_src += arch-arm/syscalls/pipe2.S
 syscall_src += arch-arm/syscalls/dup2.S
 syscall_src += arch-arm/syscalls/select.S
 syscall_src += arch-arm/syscalls/ftruncate.S
+syscall_src += arch-arm/syscalls/ftruncate64.S
 syscall_src += arch-arm/syscalls/getdents.S
 syscall_src += arch-arm/syscalls/fsync.S
 syscall_src += arch-arm/syscalls/fdatasync.S
@@ -83,6 +89,10 @@ syscall_src += arch-arm/syscalls/mkdirat.S
 syscall_src += arch-arm/syscalls/fchownat.S
 syscall_src += arch-arm/syscalls/fchmodat.S
 syscall_src += arch-arm/syscalls/renameat.S
+syscall_src += arch-arm/syscalls/fsetxattr.S
+syscall_src += arch-arm/syscalls/fgetxattr.S
+syscall_src += arch-arm/syscalls/flistxattr.S
+syscall_src += arch-arm/syscalls/fremovexattr.S
 syscall_src += arch-arm/syscalls/link.S
 syscall_src += arch-arm/syscalls/unlink.S
 syscall_src += arch-arm/syscalls/unlinkat.S
@@ -102,10 +112,20 @@ syscall_src += arch-arm/syscalls/rmdir.S
 syscall_src += arch-arm/syscalls/rename.S
 syscall_src += arch-arm/syscalls/__getcwd.S
 syscall_src += arch-arm/syscalls/access.S
+syscall_src += arch-arm/syscalls/faccessat.S
 syscall_src += arch-arm/syscalls/symlink.S
 syscall_src += arch-arm/syscalls/fchdir.S
 syscall_src += arch-arm/syscalls/truncate.S
+syscall_src += arch-arm/syscalls/setxattr.S
+syscall_src += arch-arm/syscalls/lsetxattr.S
+syscall_src += arch-arm/syscalls/getxattr.S
+syscall_src += arch-arm/syscalls/lgetxattr.S
+syscall_src += arch-arm/syscalls/listxattr.S
+syscall_src += arch-arm/syscalls/llistxattr.S
+syscall_src += arch-arm/syscalls/removexattr.S
+syscall_src += arch-arm/syscalls/lremovexattr.S
 syscall_src += arch-arm/syscalls/__statfs64.S
+syscall_src += arch-arm/syscalls/unshare.S
 syscall_src += arch-arm/syscalls/pause.S
 syscall_src += arch-arm/syscalls/gettimeofday.S
 syscall_src += arch-arm/syscalls/settimeofday.S
@@ -123,6 +143,7 @@ syscall_src += arch-arm/syscalls/__timer_gettime.S
 syscall_src += arch-arm/syscalls/__timer_getoverrun.S
 syscall_src += arch-arm/syscalls/__timer_delete.S
 syscall_src += arch-arm/syscalls/utimes.S
+syscall_src += arch-arm/syscalls/utimensat.S
 syscall_src += arch-arm/syscalls/sigaction.S
 syscall_src += arch-arm/syscalls/sigprocmask.S
 syscall_src += arch-arm/syscalls/__sigsuspend.S
@@ -130,6 +151,7 @@ syscall_src += arch-arm/syscalls/__rt_sigaction.S
 syscall_src += arch-arm/syscalls/__rt_sigprocmask.S
 syscall_src += arch-arm/syscalls/__rt_sigtimedwait.S
 syscall_src += arch-arm/syscalls/sigpending.S
+syscall_src += arch-arm/syscalls/signalfd4.S
 syscall_src += arch-arm/syscalls/socket.S
 syscall_src += arch-arm/syscalls/socketpair.S
 syscall_src += arch-arm/syscalls/bind.S
@@ -153,10 +175,12 @@ syscall_src += arch-arm/syscalls/sched_getparam.S
 syscall_src += arch-arm/syscalls/sched_get_priority_max.S
 syscall_src += arch-arm/syscalls/sched_get_priority_min.S
 syscall_src += arch-arm/syscalls/sched_rr_get_interval.S
+syscall_src += arch-arm/syscalls/sched_setaffinity.S
+syscall_src += arch-arm/syscalls/__sched_getaffinity.S
+syscall_src += arch-arm/syscalls/__getcpu.S
 syscall_src += arch-arm/syscalls/ioprio_set.S
 syscall_src += arch-arm/syscalls/ioprio_get.S
 syscall_src += arch-arm/syscalls/uname.S
-syscall_src += arch-arm/syscalls/__wait4.S
 syscall_src += arch-arm/syscalls/umask.S
 syscall_src += arch-arm/syscalls/__reboot.S
 syscall_src += arch-arm/syscalls/__syslog.S
@@ -164,6 +188,8 @@ syscall_src += arch-arm/syscalls/init_module.S
 syscall_src += arch-arm/syscalls/delete_module.S
 syscall_src += arch-arm/syscalls/klogctl.S
 syscall_src += arch-arm/syscalls/sysinfo.S
+syscall_src += arch-arm/syscalls/personality.S
+syscall_src += arch-arm/syscalls/perf_event_open.S
 syscall_src += arch-arm/syscalls/futex.S
 syscall_src += arch-arm/syscalls/epoll_create.S
 syscall_src += arch-arm/syscalls/epoll_ctl.S

libc/arch-arm/syscalls/__brk.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __brk, #function
-    .globl __brk
-    .align 4
-    .fnstart
-
-__brk:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__brk)
+    mov     ip, r7
     ldr     r7, =__NR_brk
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__brk)

libc/arch-arm/syscalls/__fcntl.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __fcntl, #function
-    .globl __fcntl
-    .align 4
-    .fnstart
-
-__fcntl:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__fcntl)
+    mov     ip, r7
     ldr     r7, =__NR_fcntl
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__fcntl)

libc/arch-arm/syscalls/__fcntl64.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __fcntl64, #function
-    .globl __fcntl64
-    .align 4
-    .fnstart
-
-__fcntl64:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__fcntl64)
+    mov     ip, r7
     ldr     r7, =__NR_fcntl64
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__fcntl64)

libc/arch-arm/syscalls/__fork.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __fork, #function
-    .globl __fork
-    .align 4
-    .fnstart
-
-__fork:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__fork)
+    mov     ip, r7
     ldr     r7, =__NR_fork
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__fork)

libc/arch-arm/syscalls/__fstatfs64.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __fstatfs64, #function
-    .globl __fstatfs64
-    .align 4
-    .fnstart
-
-__fstatfs64:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__fstatfs64)
+    mov     ip, r7
     ldr     r7, =__NR_fstatfs64
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__fstatfs64)

libc/arch-arm/syscalls/__getcpu.S

@@ -0,0 +1,15 @@
+/* autogenerated by gensyscalls.py */
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
+
+ENTRY(__getcpu)
+    mov     ip, r7
+    ldr     r7, =__NR_getcpu
+    swi     #0
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__getcpu)

libc/arch-arm/syscalls/__getcwd.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __getcwd, #function
-    .globl __getcwd
-    .align 4
-    .fnstart
-
-__getcwd:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__getcwd)
+    mov     ip, r7
     ldr     r7, =__NR_getcwd
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__getcwd)

libc/arch-arm/syscalls/__getpriority.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __getpriority, #function
-    .globl __getpriority
-    .align 4
-    .fnstart
-
-__getpriority:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__getpriority)
+    mov     ip, r7
     ldr     r7, =__NR_getpriority
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__getpriority)

libc/arch-arm/syscalls/__ioctl.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __ioctl, #function
-    .globl __ioctl
-    .align 4
-    .fnstart
-
-__ioctl:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__ioctl)
+    mov     ip, r7
     ldr     r7, =__NR_ioctl
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__ioctl)

libc/arch-arm/syscalls/__llseek.S

@@ -1,13 +1,9 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __llseek, #function
-    .globl __llseek
-    .align 4
-    .fnstart
-
-__llseek:
+ENTRY(__llseek)
     mov     ip, sp
     .save   {r4, r5, r6, r7}
     stmfd   sp!, {r4, r5, r6, r7}
@@ -15,7 +11,8 @@ __llseek:
     ldr     r7, =__NR__llseek
     swi     #0
     ldmfd   sp!, {r4, r5, r6, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__llseek)

libc/arch-arm/syscalls/__mmap2.S

@@ -1,13 +1,9 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __mmap2, #function
-    .globl __mmap2
-    .align 4
-    .fnstart
-
-__mmap2:
+ENTRY(__mmap2)
     mov     ip, sp
     .save   {r4, r5, r6, r7}
     stmfd   sp!, {r4, r5, r6, r7}
@@ -15,7 +11,8 @@ __mmap2:
     ldr     r7, =__NR_mmap2
     swi     #0
     ldmfd   sp!, {r4, r5, r6, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__mmap2)

libc/arch-arm/syscalls/__open.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __open, #function
-    .globl __open
-    .align 4
-    .fnstart
-
-__open:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__open)
+    mov     ip, r7
     ldr     r7, =__NR_open
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__open)

libc/arch-arm/syscalls/__openat.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __openat, #function
-    .globl __openat
-    .align 4
-    .fnstart
-
-__openat:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__openat)
+    mov     ip, r7
     ldr     r7, =__NR_openat
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__openat)

libc/arch-arm/syscalls/__ptrace.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __ptrace, #function
-    .globl __ptrace
-    .align 4
-    .fnstart
-
-__ptrace:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__ptrace)
+    mov     ip, r7
     ldr     r7, =__NR_ptrace
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__ptrace)

libc/arch-arm/syscalls/__reboot.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __reboot, #function
-    .globl __reboot
-    .align 4
-    .fnstart
-
-__reboot:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__reboot)
+    mov     ip, r7
     ldr     r7, =__NR_reboot
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__reboot)

libc/arch-arm/syscalls/__rt_sigaction.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __rt_sigaction, #function
-    .globl __rt_sigaction
-    .align 4
-    .fnstart
-
-__rt_sigaction:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__rt_sigaction)
+    mov     ip, r7
     ldr     r7, =__NR_rt_sigaction
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__rt_sigaction)

libc/arch-arm/syscalls/__rt_sigprocmask.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __rt_sigprocmask, #function
-    .globl __rt_sigprocmask
-    .align 4
-    .fnstart
-
-__rt_sigprocmask:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__rt_sigprocmask)
+    mov     ip, r7
     ldr     r7, =__NR_rt_sigprocmask
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__rt_sigprocmask)

libc/arch-arm/syscalls/__rt_sigtimedwait.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __rt_sigtimedwait, #function
-    .globl __rt_sigtimedwait
-    .align 4
-    .fnstart
-
-__rt_sigtimedwait:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__rt_sigtimedwait)
+    mov     ip, r7
     ldr     r7, =__NR_rt_sigtimedwait
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__rt_sigtimedwait)

libc/arch-arm/syscalls/__sched_getaffinity.S

@@ -0,0 +1,15 @@
+/* autogenerated by gensyscalls.py */
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
+
+ENTRY(__sched_getaffinity)
+    mov     ip, r7
+    ldr     r7, =__NR_sched_getaffinity
+    swi     #0
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__sched_getaffinity)

libc/arch-arm/syscalls/__set_tls.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __set_tls, #function
-    .globl __set_tls
-    .align 4
-    .fnstart
-
-__set_tls:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
-    ldr     r7, =__NR_ARM_set_tls
+ENTRY(__set_tls)
+    mov     ip, r7
+    ldr     r7, =__ARM_NR_set_tls
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__set_tls)

libc/arch-arm/syscalls/__setresuid.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __setresuid, #function
-    .globl __setresuid
-    .align 4
-    .fnstart
-
-__setresuid:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__setresuid)
+    mov     ip, r7
     ldr     r7, =__NR_setresuid32
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__setresuid)

libc/arch-arm/syscalls/__setreuid.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __setreuid, #function
-    .globl __setreuid
-    .align 4
-    .fnstart
-
-__setreuid:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__setreuid)
+    mov     ip, r7
     ldr     r7, =__NR_setreuid32
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__setreuid)

libc/arch-arm/syscalls/__setuid.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __setuid, #function
-    .globl __setuid
-    .align 4
-    .fnstart
-
-__setuid:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__setuid)
+    mov     ip, r7
     ldr     r7, =__NR_setuid32
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__setuid)

libc/arch-arm/syscalls/__sigsuspend.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __sigsuspend, #function
-    .globl __sigsuspend
-    .align 4
-    .fnstart
-
-__sigsuspend:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__sigsuspend)
+    mov     ip, r7
     ldr     r7, =__NR_sigsuspend
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__sigsuspend)

libc/arch-arm/syscalls/__statfs64.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __statfs64, #function
-    .globl __statfs64
-    .align 4
-    .fnstart
-
-__statfs64:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__statfs64)
+    mov     ip, r7
     ldr     r7, =__NR_statfs64
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__statfs64)

libc/arch-arm/syscalls/__sys_clone.S

@@ -1,13 +1,9 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __sys_clone, #function
-    .globl __sys_clone
-    .align 4
-    .fnstart
-
-__sys_clone:
+ENTRY(__sys_clone)
     mov     ip, sp
     .save   {r4, r5, r6, r7}
     stmfd   sp!, {r4, r5, r6, r7}
@@ -15,7 +11,8 @@ __sys_clone:
     ldr     r7, =__NR_clone
     swi     #0
     ldmfd   sp!, {r4, r5, r6, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__sys_clone)

libc/arch-arm/syscalls/__syslog.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __syslog, #function
-    .globl __syslog
-    .align 4
-    .fnstart
-
-__syslog:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__syslog)
+    mov     ip, r7
     ldr     r7, =__NR_syslog
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__syslog)

libc/arch-arm/syscalls/__timer_create.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __timer_create, #function
-    .globl __timer_create
-    .align 4
-    .fnstart
-
-__timer_create:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__timer_create)
+    mov     ip, r7
     ldr     r7, =__NR_timer_create
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__timer_create)

libc/arch-arm/syscalls/__timer_delete.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __timer_delete, #function
-    .globl __timer_delete
-    .align 4
-    .fnstart
-
-__timer_delete:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__timer_delete)
+    mov     ip, r7
     ldr     r7, =__NR_timer_delete
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__timer_delete)

libc/arch-arm/syscalls/__timer_getoverrun.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __timer_getoverrun, #function
-    .globl __timer_getoverrun
-    .align 4
-    .fnstart
-
-__timer_getoverrun:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__timer_getoverrun)
+    mov     ip, r7
     ldr     r7, =__NR_timer_getoverrun
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__timer_getoverrun)

libc/arch-arm/syscalls/__timer_gettime.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __timer_gettime, #function
-    .globl __timer_gettime
-    .align 4
-    .fnstart
-
-__timer_gettime:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__timer_gettime)
+    mov     ip, r7
     ldr     r7, =__NR_timer_gettime
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__timer_gettime)

libc/arch-arm/syscalls/__timer_settime.S

@@ -1,19 +1,15 @@
 /* autogenerated by gensyscalls.py */
-#include <sys/linux-syscalls.h>
+#include <asm/unistd.h>
+#include <linux/err.h>
+#include <machine/asm.h>
 
-    .text
-    .type __timer_settime, #function
-    .globl __timer_settime
-    .align 4
-    .fnstart
-
-__timer_settime:
-    .save   {r4, r7}
-    stmfd   sp!, {r4, r7}
+ENTRY(__timer_settime)
+    mov     ip, r7
     ldr     r7, =__NR_timer_settime
     swi     #0
-    ldmfd   sp!, {r4, r7}
-    movs    r0, r0
-    bxpl    lr
-    b       __set_syscall_errno
-    .fnend
+    mov     r7, ip
+    cmn     r0, #(MAX_ERRNO + 1)
+    bxls    lr
+    neg     r0, r0
+    b       __set_errno
+END(__timer_settime)