bionic: Add ARM optimized strcpy()
Reference results of the experiments on Qualcomm MSM7x25 (524MHz):
[original C code]
prc thr usecs/call samples errors cnt/samp
size
strcpy_1k 1 1 14.56159 99 0 1000
1024
[ARM optimized code]
prc thr usecs/call samples errors cnt/samp
size
strcpy_1k 1 1 3.46653 99 0 1000
1024
The work was derived from ARM Ltd.
Change-Id: I906ac53bb7a7285e14693c77d3ce8d4ed6f98bfd
This commit is contained in:
Jim Huang
Jean-Baptiste Queru
parent
ea0fe8563d
commit
73c04b3269
@ -186,7 +186,6 @@ libc_common_src_files := \
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string/strcat.c \
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string/strchr.c \
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string/strcoll.c \
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string/strcpy.c \
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string/strcspn.c \
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string/strdup.c \
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string/strerror.c \
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@ -309,6 +308,7 @@ libc_common_src_files += \
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arch-arm/bionic/setjmp.S \
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arch-arm/bionic/sigsetjmp.S \
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arch-arm/bionic/strlen.c.arm \
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arch-arm/bionic/strcpy.S \
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arch-arm/bionic/syscall.S \
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arch-arm/bionic/sigaction.c \
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arch-arm/bionic/__sig_restorer.S \
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@ -357,6 +357,7 @@ libc_common_src_files += \
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arch-x86/string/strcmp_wrapper.S \
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arch-x86/string/strncmp_wrapper.S \
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arch-x86/string/strlen_wrapper.S \
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string/strcpy.c \
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bionic/pthread.c \
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bionic/pthread-atfork.c \
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bionic/pthread-timers.c \
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@ -394,6 +395,7 @@ libc_common_src_files += \
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string/strncmp.c \
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string/memcmp.c \
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string/strlen.c \
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string/strcpy.c \
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bionic/pthread.c \
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bionic/pthread-atfork.c \
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bionic/pthread-timers.c \
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138
libc/arch-arm/bionic/strcpy.S
Normal file
138
libc/arch-arm/bionic/strcpy.S
Normal file
@ -0,0 +1,138 @@
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/*
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* Copyright (C) 2010 The Android Open Source Project
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* Copyright (c) 2008 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Android adaptation and tweak by Jim Huang <jserv@0xlab.org>.
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*/
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#include <machine/cpu-features.h>
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.text
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.global strcpy
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.type strcpy, %function
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.align 4
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strcpy:
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.fnstart
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PLD(r1, #0)
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eor r2, r0, r1
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mov ip, r0
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tst r2, #3
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bne 4f
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tst r1, #3
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bne 3f
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5:
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str r5, [sp, #-4]!
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mov r5, #0x01
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orr r5, r5, r5, lsl #8
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orr r5, r5, r5, lsl #16
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str r4, [sp, #-4]!
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tst r1, #4
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ldr r3, [r1], #4
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beq 2f
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sub r2, r3, r5
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bics r2, r2, r3
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tst r2, r5, lsl #7
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itt eq
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streq r3, [ip], #4
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ldreq r3, [r1], #4
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bne 1f
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/* Inner loop. We now know that r1 is 64-bit aligned, so we
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can safely fetch up to two words. This allows us to avoid
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load stalls. */
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.p2align 2
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2:
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PLD(r1, #8)
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ldr r4, [r1], #4
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sub r2, r3, r5
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bics r2, r2, r3
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tst r2, r5, lsl #7
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sub r2, r4, r5
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bne 1f
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str r3, [ip], #4
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bics r2, r2, r4
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tst r2, r5, lsl #7
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itt eq
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ldreq r3, [r1], #4
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streq r4, [ip], #4
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beq 2b
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mov r3, r4
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1:
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#ifdef __ARMEB__
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rors r3, r3, #24
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#endif
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strb r3, [ip], #1
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tst r3, #0xff
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#ifdef __ARMEL__
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ror r3, r3, #8
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#endif
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bne 1b
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ldr r4, [sp], #4
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ldr r5, [sp], #4
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bx lr
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/* Strings have the same offset from word alignment, but it's
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not zero. */
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3:
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tst r1, #1
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beq 1f
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ldrb r2, [r1], #1
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strb r2, [ip], #1
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cmp r2, #0
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it eq
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bxeq lr
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1:
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tst r1, #2
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beq 5b
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ldrh r2, [r1], #2
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#ifdef __ARMEB__
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tst r2, #0xff00
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iteet ne
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strneh r2, [ip], #2
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lsreq r2, r2, #8
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streqb r2, [ip]
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tstne r2, #0xff
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#else
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tst r2, #0xff
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itet ne
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strneh r2, [ip], #2
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streqb r2, [ip]
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tstne r2, #0xff00
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#endif
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bne 5b
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bx lr
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/* src and dst do not have a common word-alignement. Fall back to
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byte copying. */
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4:
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ldrb r2, [r1], #1
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strb r2, [ip], #1
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cmp r2, #0
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bne 4b
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bx lr
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