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am 4e882503: am a990cf5b: Merge "Clean up trailing whitespace in the kernel headers."

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# Via Android Git Automerger (1) and others
* commit '4e8825038e08762dcc973fa435b531f10290ffa8':
  Clean up trailing whitespace in the kernel headers.
This commit is contained in:
Elliott Hughes 2013-01-30 10:31:24 -08:00 committed by Android Git Automerger
commit 9d43c07987
341 changed files with 6527 additions and 6635 deletions
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7
libc/kernel/README.TXT
View File

@ -60,13 +60,6 @@ the tools you can use are:
'external/kernel-headers/original'. this is the script you're likely going to
run whenever you update the original headers.
NOTE:
if ANDROID_PRODUCT_OUT is defined in your environment, both 'clean_header.py'
and 'update_all.py' will automatically issue "p4 add/edit/delete" commands
appropriately to reflect the changes being made.
you will need to "p4 submit" manually though...
HOW TO BUILD BIONIC AND OTHER PROGRAMS WITH THE CLEAN HEADERS:
==============================================================

126
libc/kernel/arch-arm/asm/arch/dma.h
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@ -64,7 +64,7 @@
#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c)
#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70)
#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74)
#define OMAP_LOGICAL_DMA_CH_COUNT 32
#define OMAP_LOGICAL_DMA_CH_COUNT 32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
@ -171,83 +171,83 @@
#define OMAP_DMA_CRYPTO_DES_OUT 56
#define OMAP24XX_DMA_NO_DEVICE 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_XTI_DMA 1
#define OMAP24XX_DMA_EXT_DMAREQ0 2
#define OMAP24XX_DMA_EXT_DMAREQ1 3
#define OMAP24XX_DMA_GPMC 4
#define OMAP24XX_DMA_XTI_DMA 1
#define OMAP24XX_DMA_EXT_DMAREQ0 2
#define OMAP24XX_DMA_EXT_DMAREQ1 3
#define OMAP24XX_DMA_GPMC 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_GFX 5
#define OMAP24XX_DMA_DSS 6
#define OMAP24XX_DMA_VLYNQ_TX 7
#define OMAP24XX_DMA_CWT 8
#define OMAP24XX_DMA_GFX 5
#define OMAP24XX_DMA_DSS 6
#define OMAP24XX_DMA_VLYNQ_TX 7
#define OMAP24XX_DMA_CWT 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_AES_TX 9
#define OMAP24XX_DMA_AES_RX 10
#define OMAP24XX_DMA_DES_TX 11
#define OMAP24XX_DMA_DES_RX 12
#define OMAP24XX_DMA_AES_TX 9
#define OMAP24XX_DMA_AES_RX 10
#define OMAP24XX_DMA_DES_TX 11
#define OMAP24XX_DMA_DES_RX 12
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_SHA1MD5_RX 13
#define OMAP24XX_DMA_EXT_DMAREQ2 14
#define OMAP24XX_DMA_EXT_DMAREQ3 15
#define OMAP24XX_DMA_EXT_DMAREQ4 16
#define OMAP24XX_DMA_SHA1MD5_RX 13
#define OMAP24XX_DMA_EXT_DMAREQ2 14
#define OMAP24XX_DMA_EXT_DMAREQ3 15
#define OMAP24XX_DMA_EXT_DMAREQ4 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_EAC_AC_RD 17
#define OMAP24XX_DMA_EAC_AC_WR 18
#define OMAP24XX_DMA_EAC_MD_UL_RD 19
#define OMAP24XX_DMA_EAC_MD_UL_WR 20
#define OMAP24XX_DMA_EAC_AC_RD 17
#define OMAP24XX_DMA_EAC_AC_WR 18
#define OMAP24XX_DMA_EAC_MD_UL_RD 19
#define OMAP24XX_DMA_EAC_MD_UL_WR 20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_EAC_MD_DL_RD 21
#define OMAP24XX_DMA_EAC_MD_DL_WR 22
#define OMAP24XX_DMA_EAC_BT_UL_RD 23
#define OMAP24XX_DMA_EAC_BT_UL_WR 24
#define OMAP24XX_DMA_EAC_MD_DL_RD 21
#define OMAP24XX_DMA_EAC_MD_DL_WR 22
#define OMAP24XX_DMA_EAC_BT_UL_RD 23
#define OMAP24XX_DMA_EAC_BT_UL_WR 24
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_EAC_BT_DL_RD 25
#define OMAP24XX_DMA_EAC_BT_DL_WR 26
#define OMAP24XX_DMA_I2C1_TX 27
#define OMAP24XX_DMA_I2C1_RX 28
#define OMAP24XX_DMA_EAC_BT_DL_RD 25
#define OMAP24XX_DMA_EAC_BT_DL_WR 26
#define OMAP24XX_DMA_I2C1_TX 27
#define OMAP24XX_DMA_I2C1_RX 28
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_I2C2_TX 29
#define OMAP24XX_DMA_I2C2_RX 30
#define OMAP24XX_DMA_MCBSP1_TX 31
#define OMAP24XX_DMA_MCBSP1_RX 32
#define OMAP24XX_DMA_I2C2_TX 29
#define OMAP24XX_DMA_I2C2_RX 30
#define OMAP24XX_DMA_MCBSP1_TX 31
#define OMAP24XX_DMA_MCBSP1_RX 32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_MCBSP2_TX 33
#define OMAP24XX_DMA_MCBSP2_RX 34
#define OMAP24XX_DMA_SPI1_TX0 35
#define OMAP24XX_DMA_SPI1_RX0 36
#define OMAP24XX_DMA_MCBSP2_TX 33
#define OMAP24XX_DMA_MCBSP2_RX 34
#define OMAP24XX_DMA_SPI1_TX0 35
#define OMAP24XX_DMA_SPI1_RX0 36
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_SPI1_TX1 37
#define OMAP24XX_DMA_SPI1_RX1 38
#define OMAP24XX_DMA_SPI1_TX2 39
#define OMAP24XX_DMA_SPI1_RX2 40
#define OMAP24XX_DMA_SPI1_TX1 37
#define OMAP24XX_DMA_SPI1_RX1 38
#define OMAP24XX_DMA_SPI1_TX2 39
#define OMAP24XX_DMA_SPI1_RX2 40
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_SPI1_TX3 41
#define OMAP24XX_DMA_SPI1_RX3 42
#define OMAP24XX_DMA_SPI2_TX0 43
#define OMAP24XX_DMA_SPI2_RX0 44
#define OMAP24XX_DMA_SPI1_TX3 41
#define OMAP24XX_DMA_SPI1_RX3 42
#define OMAP24XX_DMA_SPI2_TX0 43
#define OMAP24XX_DMA_SPI2_RX0 44
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_SPI2_TX1 45
#define OMAP24XX_DMA_SPI2_RX1 46
#define OMAP24XX_DMA_UART1_TX 49
#define OMAP24XX_DMA_UART1_RX 50
#define OMAP24XX_DMA_SPI2_TX1 45
#define OMAP24XX_DMA_SPI2_RX1 46
#define OMAP24XX_DMA_UART1_TX 49
#define OMAP24XX_DMA_UART1_RX 50
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_UART2_TX 51
#define OMAP24XX_DMA_UART2_RX 52
#define OMAP24XX_DMA_UART3_TX 53
#define OMAP24XX_DMA_UART3_RX 54
#define OMAP24XX_DMA_UART2_TX 51
#define OMAP24XX_DMA_UART2_RX 52
#define OMAP24XX_DMA_UART3_TX 53
#define OMAP24XX_DMA_UART3_RX 54
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_USB_W2FC_TX0 55
#define OMAP24XX_DMA_USB_W2FC_RX0 56
#define OMAP24XX_DMA_USB_W2FC_TX1 57
#define OMAP24XX_DMA_USB_W2FC_RX1 58
#define OMAP24XX_DMA_USB_W2FC_TX0 55
#define OMAP24XX_DMA_USB_W2FC_RX0 56
#define OMAP24XX_DMA_USB_W2FC_TX1 57
#define OMAP24XX_DMA_USB_W2FC_RX1 58
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_USB_W2FC_TX2 59
#define OMAP24XX_DMA_USB_W2FC_RX2 60
#define OMAP24XX_DMA_MMC1_TX 61
#define OMAP24XX_DMA_MMC1_RX 62
#define OMAP24XX_DMA_USB_W2FC_TX2 59
#define OMAP24XX_DMA_USB_W2FC_RX2 60
#define OMAP24XX_DMA_MMC1_TX 61
#define OMAP24XX_DMA_MMC1_RX 62
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP24XX_DMA_MS 63
#define OMAP24XX_DMA_EXT_DMAREQ5 64
#define OMAP24XX_DMA_MS 63
#define OMAP24XX_DMA_EXT_DMAREQ5 64
#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

40
libc/kernel/arch-arm/asm/arch/fpga.h
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@ -22,19 +22,19 @@
#define fpga_read(reg) __raw_readb(reg)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fpga_write(val, reg) __raw_writeb(val, reg)
#define H2P2_DBG_FPGA_BASE 0xE8000000
#define H2P2_DBG_FPGA_SIZE SZ_4K
#define H2P2_DBG_FPGA_START 0x04000000
#define H2P2_DBG_FPGA_BASE 0xE8000000
#define H2P2_DBG_FPGA_SIZE SZ_4K
#define H2P2_DBG_FPGA_START 0x04000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10)
#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12)
#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14)
#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10)
#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12)
#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16)
#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18)
#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A)
#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C)
#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16)
#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18)
#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A)
#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct h2p2_dbg_fpga {
u16 smc91x[8];
@ -57,16 +57,16 @@ struct h2p2_dbg_fpga {
#define H2P2_DBG_FPGA_LED_RED (1 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
#define H2P2_DBG_FPGA_LOAD_METER (1 << 0)
#define H2P2_DBG_FPGA_LOAD_METER (1 << 0)
#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
#define OMAP1510_FPGA_BASE 0xE8000000
#define OMAP1510_FPGA_BASE 0xE8000000
#define OMAP1510_FPGA_SIZE SZ_4K
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP1510_FPGA_START 0x08000000
#define OMAP1510_FPGA_START 0x08000000
#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
@ -122,16 +122,16 @@ struct h2p2_dbg_fpga {
#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
#define OMAP1510_FPGA_HID_SCLK (1<<0)
#define OMAP1510_FPGA_HID_MOSI (1<<1)
#define OMAP1510_FPGA_HID_nSS (1<<2)
#define OMAP1510_FPGA_HID_SCLK (1<<0)
#define OMAP1510_FPGA_HID_MOSI (1<<1)
#define OMAP1510_FPGA_HID_nSS (1<<2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP1510_FPGA_HID_nHSUS (1<<3)
#define OMAP1510_FPGA_HID_MISO (1<<4)
#define OMAP1510_FPGA_HID_ATN (1<<5)
#define OMAP1510_FPGA_HID_nHSUS (1<<3)
#define OMAP1510_FPGA_HID_MISO (1<<4)
#define OMAP1510_FPGA_HID_ATN (1<<5)
#define OMAP1510_FPGA_HID_rsrvd (1<<6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OMAP1510_FPGA_HID_RESETn (1<<7)
#define OMAP1510_FPGA_HID_RESETn (1<<7)
#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE
#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0)

4
libc/kernel/arch-arm/asm/arch/hardware.h
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@ -66,8 +66,8 @@
#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DIS_USB_PVCI_CLK (1 << 5)
#define USB_MCLK_EN (1 << 4)
#define DIS_USB_PVCI_CLK (1 << 5)
#define USB_MCLK_EN (1 << 4)
#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
#define SOFT_UDC_REQ (1 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

52
libc/kernel/arch-arm/asm/arch/mcbsp.h
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@ -39,12 +39,12 @@
#define RRDY 0x0002
#define RFULL 0x0004
#define RSYNC_ERR 0x0008
#define RINTM(value) ((value)<<4)
#define RINTM(value) ((value)<<4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ABIS 0x0040
#define DXENA 0x0080
#define CLKSTP(value) ((value)<<11)
#define RJUST(value) ((value)<<13)
#define CLKSTP(value) ((value)<<11)
#define RJUST(value) ((value)<<13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DLB 0x8000
#define XRST 0x0001
@ -52,7 +52,7 @@
#define XEMPTY 0x0004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XSYNC_ERR 0x0008
#define XINTM(value) ((value)<<4)
#define XINTM(value) ((value)<<4)
#define GRST 0x0040
#define FRST 0x0080
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -77,29 +77,29 @@
#define XIOEN 0x2000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IDLE_EN 0x4000
#define RWDLEN1(value) ((value)<<5)
#define RFRLEN1(value) ((value)<<8)
#define XWDLEN1(value) ((value)<<5)
#define RWDLEN1(value) ((value)<<5)
#define RFRLEN1(value) ((value)<<8)
#define XWDLEN1(value) ((value)<<5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XFRLEN1(value) ((value)<<8)
#define RDATDLY(value) (value)
#define XFRLEN1(value) ((value)<<8)
#define RDATDLY(value) (value)
#define RFIG 0x0004
#define RCOMPAND(value) ((value)<<3)
#define RCOMPAND(value) ((value)<<3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RWDLEN2(value) ((value)<<5)
#define RFRLEN2(value) ((value)<<8)
#define RWDLEN2(value) ((value)<<5)
#define RFRLEN2(value) ((value)<<8)
#define RPHASE 0x8000
#define XDATDLY(value) (value)
#define XDATDLY(value) (value)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XFIG 0x0004
#define XCOMPAND(value) ((value)<<3)
#define XWDLEN2(value) ((value)<<5)
#define XFRLEN2(value) ((value)<<8)
#define XCOMPAND(value) ((value)<<3)
#define XWDLEN2(value) ((value)<<5)
#define XFRLEN2(value) ((value)<<8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XPHASE 0x8000
#define CLKGDV(value) (value)
#define FWID(value) ((value)<<8)
#define FPER(value) (value)
#define CLKGDV(value) (value)
#define FWID(value) ((value)<<8)
#define FPER(value) (value)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FSGM 0x1000
#define CLKSM 0x2000
@ -107,14 +107,14 @@
#define GSYNC 0x8000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RMCM 0x0001
#define RCBLK(value) ((value)<<2)
#define RPABLK(value) ((value)<<5)
#define RPBBLK(value) ((value)<<7)
#define RCBLK(value) ((value)<<2)
#define RPABLK(value) ((value)<<5)
#define RPBBLK(value) ((value)<<7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XMCM(value) (value)
#define XCBLK(value) ((value)<<2)
#define XPABLK(value) ((value)<<5)
#define XPBBLK(value) ((value)<<7)
#define XMCM(value) (value)
#define XCBLK(value) ((value)<<2)
#define XPABLK(value) ((value)<<5)
#define XPBBLK(value) ((value)<<7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct omap_mcbsp_reg_cfg {
u16 spcr2;

4
libc/kernel/arch-arm/asm/arch/mux.h
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@ -18,8 +18,8 @@
****************************************************************************/
#ifndef __ASM_ARCH_MUX_H
#define __ASM_ARCH_MUX_H
#define PU_PD_SEL_NA 0
#define PULL_DWN_CTRL_NA 0
#define PU_PD_SEL_NA 0
#define PULL_DWN_CTRL_NA 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, .mask_offset = mode_offset, .mask = mode,
#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, .pull_bit = bit, .pull_val = status,

2
libc/kernel/arch-arm/asm/delay.h
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@ -18,7 +18,7 @@
****************************************************************************/
#ifndef __ASM_ARM_DELAY_H
#define __ASM_ARM_DELAY_H
#include <asm/param.h>
#include <asm/param.h>
#define MAX_UDELAY_MS 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define udelay(n) (__builtin_constant_p(n) ? ((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() : __const_udelay((n) * ((2199023U*HZ)>>11))) : __udelay(n))

6
libc/kernel/arch-arm/asm/fcntl.h
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@ -18,10 +18,10 @@
****************************************************************************/
#ifndef _ARM_FCNTL_H
#define _ARM_FCNTL_H
#define O_DIRECTORY 040000
#define O_NOFOLLOW 0100000
#define O_DIRECTORY 040000
#define O_NOFOLLOW 0100000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define O_DIRECT 0200000
#define O_DIRECT 0200000
#define O_LARGEFILE 0400000
#include <asm-generic/fcntl.h>
#endif

2
libc/kernel/arch-arm/asm/hardirq.h
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@ -27,7 +27,7 @@ typedef struct {
unsigned int local_timer_irqs;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h>
#include <linux/irq_cpustat.h>
#if NR_IRQS > 256
#define HARDIRQ_BITS 9
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

28
libc/kernel/arch-arm/asm/ioctls.h
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@ -66,14 +66,14 @@
#define TIOCSETD 0x5423
#define TIOCGETD 0x5424
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSBRKP 0x5425
#define TIOCSBRK 0x5427
#define TIOCCBRK 0x5428
#define TIOCGSID 0x5429
#define TCSBRKP 0x5425
#define TIOCSBRK 0x5427
#define TIOCCBRK 0x5428
#define TIOCGSID 0x5429
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGPTN _IOR('T',0x30, unsigned int)
#define TIOCSPTLCK _IOW('T',0x31, int)
#define FIONCLEX 0x5450
#define TIOCGPTN _IOR('T',0x30, unsigned int)
#define TIOCSPTLCK _IOW('T',0x31, int)
#define FIONCLEX 0x5450
#define FIOCLEX 0x5451
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FIOASYNC 0x5452
@ -83,13 +83,13 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGLCKTRMIOS 0x5456
#define TIOCSLCKTRMIOS 0x5457
#define TIOCSERGSTRUCT 0x5458
#define TIOCSERGETLSR 0x5459
#define TIOCSERGSTRUCT 0x5458
#define TIOCSERGETLSR 0x5459
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCSERGETMULTI 0x545A
#define TIOCSERSETMULTI 0x545B
#define TIOCMIWAIT 0x545C
#define TIOCGICOUNT 0x545D
#define TIOCSERGETMULTI 0x545A
#define TIOCSERSETMULTI 0x545B
#define TIOCMIWAIT 0x545C
#define TIOCGICOUNT 0x545D
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FIOQSIZE 0x545E
#define TIOCPKT_DATA 0
@ -101,5 +101,5 @@
#define TIOCPKT_NOSTOP 16
#define TIOCPKT_DOSTOP 32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCSER_TEMT 0x01
#define TIOCSER_TEMT 0x01
#endif

2
libc/kernel/arch-arm/asm/mc146818rtc.h
View File

@ -23,7 +23,7 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef RTC_PORT
#define RTC_PORT(x) (0x70 + (x))
#define RTC_ALWAYS_BCD 1
#define RTC_ALWAYS_BCD 1
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CMOS_READ(addr) ({ outb_p((addr),RTC_PORT(0)); inb_p(RTC_PORT(1)); })

18
libc/kernel/arch-arm/asm/mman.h
View File

@ -19,16 +19,16 @@
#ifndef __ARM_MMAN_H__
#define __ARM_MMAN_H__
#include <asm-generic/mman.h>
#define MAP_GROWSDOWN 0x0100
#define MAP_GROWSDOWN 0x0100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAP_DENYWRITE 0x0800
#define MAP_EXECUTABLE 0x1000
#define MAP_LOCKED 0x2000
#define MAP_NORESERVE 0x4000
#define MAP_DENYWRITE 0x0800
#define MAP_EXECUTABLE 0x1000
#define MAP_LOCKED 0x2000
#define MAP_NORESERVE 0x4000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAP_POPULATE 0x8000
#define MAP_NONBLOCK 0x10000
#define MCL_CURRENT 1
#define MCL_FUTURE 2
#define MAP_POPULATE 0x8000
#define MAP_NONBLOCK 0x10000
#define MCL_CURRENT 1
#define MCL_FUTURE 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

28
libc/kernel/arch-arm/asm/pgtable-hwdef.h
View File

@ -26,19 +26,19 @@
#define PMD_BIT4 (1 << 4)
#define PMD_DOMAIN(x) ((x) << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PMD_PROTECTION (1 << 9)
#define PMD_PROTECTION (1 << 9)
#define PMD_SECT_BUFFERABLE (1 << 2)
#define PMD_SECT_CACHEABLE (1 << 3)
#define PMD_SECT_XN (1 << 4)
#define PMD_SECT_XN (1 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PMD_SECT_AP_WRITE (1 << 10)
#define PMD_SECT_AP_READ (1 << 11)
#define PMD_SECT_TEX(x) ((x) << 12)
#define PMD_SECT_APX (1 << 15)
#define PMD_SECT_TEX(x) ((x) << 12)
#define PMD_SECT_APX (1 << 15)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PMD_SECT_S (1 << 16)
#define PMD_SECT_nG (1 << 17)
#define PMD_SECT_SUPER (1 << 18)
#define PMD_SECT_S (1 << 16)
#define PMD_SECT_nG (1 << 17)
#define PMD_SECT_SUPER (1 << 18)
#define PMD_SECT_UNCACHED (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
@ -53,11 +53,11 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTE_TYPE_LARGE (1 << 0)
#define PTE_TYPE_SMALL (2 << 0)
#define PTE_TYPE_EXT (3 << 0)
#define PTE_TYPE_EXT (3 << 0)
#define PTE_BUFFERABLE (1 << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTE_CACHEABLE (1 << 3)
#define PTE_EXT_XN (1 << 0)
#define PTE_EXT_XN (1 << 0)
#define PTE_EXT_AP_MASK (3 << 4)
#define PTE_EXT_AP0 (1 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -67,12 +67,12 @@
#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
#define PTE_EXT_TEX(x) ((x) << 6)
#define PTE_EXT_APX (1 << 9)
#define PTE_EXT_COHERENT (1 << 9)
#define PTE_EXT_TEX(x) ((x) << 6)
#define PTE_EXT_APX (1 << 9)
#define PTE_EXT_COHERENT (1 << 9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PTE_EXT_SHARED (1 << 10)
#define PTE_EXT_NG (1 << 11)
#define PTE_EXT_SHARED (1 << 10)
#define PTE_EXT_NG (1 << 11)
#define PTE_SMALL_AP_MASK (0xff << 4)
#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

2
libc/kernel/arch-arm/asm/procinfo.h
View File

@ -48,7 +48,7 @@ struct proc_info_list {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HWCAP_HALF 2
#define HWCAP_THUMB 4
#define HWCAP_26BIT 8
#define HWCAP_26BIT 8
#define HWCAP_FAST_MULT 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HWCAP_FPA 32

8
libc/kernel/arch-arm/asm/ptrace.h
View File

@ -63,11 +63,11 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSR_N_BIT 0x80000000
#define PCMASK 0
#define PSR_f 0xff000000
#define PSR_s 0x00ff0000
#define PSR_f 0xff000000
#define PSR_s 0x00ff0000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PSR_x 0x0000ff00
#define PSR_c 0x000000ff
#define PSR_x 0x0000ff00
#define PSR_c 0x000000ff
#ifndef __ASSEMBLY__
struct pt_regs {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

2
libc/kernel/arch-arm/asm/shmparam.h
View File

@ -18,7 +18,7 @@
****************************************************************************/
#ifndef _ASMARM_SHMPARAM_H
#define _ASMARM_SHMPARAM_H
#define SHMLBA (4 * PAGE_SIZE)
#define SHMLBA (4 * PAGE_SIZE)
#define __ARCH_FORCE_SHMLBA
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

2
libc/kernel/arch-arm/asm/sockios.h
View File

@ -24,6 +24,6 @@
#define FIOGETOWN 0x8903
#define SIOCGPGRP 0x8904
#define SIOCATMARK 0x8905
#define SIOCGSTAMP 0x8906
#define SIOCGSTAMP 0x8906
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

2
libc/kernel/arch-arm/asm/stat.h
View File

@ -34,7 +34,7 @@ struct __old_kernel_stat {
unsigned long st_mtime;
unsigned long st_ctime;
};
#define STAT_HAVE_NSEC
#define STAT_HAVE_NSEC
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct stat {
#ifdef __ARMEB__

8
libc/kernel/arch-arm/asm/termbits.h
View File

@ -113,7 +113,7 @@ struct termios {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FF1 0100000
#define CBAUD 0010017
#define B0 0000000
#define B0 0000000
#define B50 0000001
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define B75 0000002
@ -169,10 +169,10 @@ struct termios {
#define B3000000 0010015
#define B3500000 0010016
#define B4000000 0010017
#define CIBAUD 002003600000
#define CIBAUD 002003600000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CMSPAR 010000000000
#define CRTSCTS 020000000000
#define CMSPAR 010000000000
#define CRTSCTS 020000000000
#define ISIG 0000001
#define ICANON 0000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

16
libc/kernel/arch-arm/asm/termios.h
View File

@ -64,17 +64,17 @@ struct termio {
#define N_PPP 3
#define N_STRIP 4
#define N_AX25 5
#define N_X25 6
#define N_X25 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define N_6PACK 7
#define N_MASC 8
#define N_R3964 9
#define N_PROFIBUS_FDL 10
#define N_MASC 8
#define N_R3964 9
#define N_PROFIBUS_FDL 10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define N_IRDA 11
#define N_SMSBLOCK 12
#define N_HDLC 13
#define N_IRDA 11
#define N_SMSBLOCK 12
#define N_HDLC 13
#define N_SYNC_PPP 14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define N_HCI 15
#define N_HCI 15
#endif

6
libc/kernel/arch-arm/asm/unistd.h
View File

@ -102,7 +102,7 @@
#define __NR_sethostname (__NR_SYSCALL_BASE+ 74)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __NR_setrlimit (__NR_SYSCALL_BASE+ 75)
#define __NR_getrlimit (__NR_SYSCALL_BASE+ 76)
#define __NR_getrlimit (__NR_SYSCALL_BASE+ 76)
#define __NR_getrusage (__NR_SYSCALL_BASE+ 77)
#define __NR_gettimeofday (__NR_SYSCALL_BASE+ 78)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -141,7 +141,7 @@
#define __NR_fstat (__NR_SYSCALL_BASE+108)
#define __NR_vhangup (__NR_SYSCALL_BASE+111)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __NR_syscall (__NR_SYSCALL_BASE+113)
#define __NR_syscall (__NR_SYSCALL_BASE+113)
#define __NR_wait4 (__NR_SYSCALL_BASE+114)
#define __NR_swapoff (__NR_SYSCALL_BASE+115)
#define __NR_sysinfo (__NR_SYSCALL_BASE+116)
@ -228,7 +228,7 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __NR_sendfile (__NR_SYSCALL_BASE+187)
#define __NR_vfork (__NR_SYSCALL_BASE+190)
#define __NR_ugetrlimit (__NR_SYSCALL_BASE+191)
#define __NR_ugetrlimit (__NR_SYSCALL_BASE+191)
#define __NR_mmap2 (__NR_SYSCALL_BASE+192)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __NR_truncate64 (__NR_SYSCALL_BASE+193)

8
libc/kernel/arch-mips/asm/addrspace.h
View File

@ -38,8 +38,8 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _ACAST64_
#else
#define _ACAST32_ (_ATYPE_)(_ATYPE32_)
#define _ACAST64_ (_ATYPE64_)
#define _ACAST32_ (_ATYPE_)(_ATYPE32_)
#define _ACAST64_ (_ATYPE64_)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
@ -83,10 +83,10 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | (_CONST64_(cm) << 59) | (a))
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff)
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff)
#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32)
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32)
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
#endif

2
libc/kernel/arch-mips/asm/bitops.h
View File

@ -28,7 +28,7 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/barrier.h>
#include <asm/bug.h>
#include <asm/byteorder.h>
#include <asm/byteorder.h>
#include <asm/cpu-features.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/sgidefs.h>

40
libc/kernel/arch-mips/asm/bootinfo.h
View File

@ -21,32 +21,32 @@
#include <linux/types.h>
#include <asm/setup.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACH_UNKNOWN 0
#define MACH_UNKNOWN 0
#define MACH_DSUNKNOWN 0
#define MACH_DS23100 1
#define MACH_DS5100 2
#define MACH_DS23100 1
#define MACH_DS5100 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACH_DS5000_200 3
#define MACH_DS5000_1XX 4
#define MACH_DS5000_XX 5
#define MACH_DS5000_2X0 6
#define MACH_DS5000_200 3
#define MACH_DS5000_1XX 4
#define MACH_DS5000_XX 5
#define MACH_DS5000_2X0 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACH_DS5400 7
#define MACH_DS5500 8
#define MACH_DS5800 9
#define MACH_DS5900 10
#define MACH_DS5400 7
#define MACH_DS5500 8
#define MACH_DS5800 9
#define MACH_DS5900 10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACH_MSP4200_EVAL 0
#define MACH_MSP4200_GW 1
#define MACH_MSP4200_FPGA 2
#define MACH_MSP7120_EVAL 3
#define MACH_MSP4200_EVAL 0
#define MACH_MSP4200_GW 1
#define MACH_MSP4200_FPGA 2
#define MACH_MSP7120_EVAL 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACH_MSP7120_GW 4
#define MACH_MSP7120_FPGA 5
#define MACH_MSP_OTHER 255
#define MACH_MIKROTIK_RB532 0
#define MACH_MSP7120_GW 4
#define MACH_MSP7120_FPGA 5
#define MACH_MSP_OTHER 255
#define MACH_MIKROTIK_RB532 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACH_MIKROTIK_RB532A 1
#define MACH_MIKROTIK_RB532A 1
#define CL_SIZE COMMAND_LINE_SIZE
#define BOOT_MEM_MAP_MAX 32
#define BOOT_MEM_RAM 1

10
libc/kernel/arch-mips/asm/cachectl.h
View File

@ -18,11 +18,11 @@
****************************************************************************/
#ifndef _ASM_CACHECTL
#define _ASM_CACHECTL
#define ICACHE (1<<0)
#define DCACHE (1<<1)
#define ICACHE (1<<0)
#define DCACHE (1<<1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BCACHE (ICACHE|DCACHE)
#define CACHEABLE 0
#define UNCACHEABLE 1
#define BCACHE (ICACHE|DCACHE)
#define CACHEABLE 0
#define UNCACHEABLE 1
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

10
libc/kernel/arch-mips/asm/cpu-info.h
View File

@ -31,12 +31,12 @@ struct cache_desc {
};
#define MIPS_CACHE_NOT_PRESENT 0x00000001
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CACHE_VTAG 0x00000002
#define MIPS_CACHE_ALIASES 0x00000004
#define MIPS_CACHE_IC_F_DC 0x00000008
#define MIPS_IC_SNOOPS_REMOTE 0x00000010
#define MIPS_CACHE_VTAG 0x00000002
#define MIPS_CACHE_ALIASES 0x00000004
#define MIPS_CACHE_IC_F_DC 0x00000008
#define MIPS_IC_SNOOPS_REMOTE 0x00000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CACHE_PINDEX 0x00000020
#define MIPS_CACHE_PINDEX 0x00000020
struct cpuinfo_mips {
unsigned long udelay_val;
unsigned long asid_cache;

68
libc/kernel/arch-mips/asm/cpu.h
View File

@ -34,9 +34,9 @@
#define PRID_IMP_R2000 0x0100
#define PRID_IMP_AU1_REV1 0x0100
#define PRID_IMP_AU1_REV2 0x0200
#define PRID_IMP_R3000 0x0200
#define PRID_IMP_R3000 0x0200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_R6000 0x0300
#define PRID_IMP_R6000 0x0300
#define PRID_IMP_R4000 0x0400
#define PRID_IMP_R6000A 0x0600
#define PRID_IMP_R10000 0x0900
@ -53,7 +53,7 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_TX39 0x2200
#define PRID_IMP_R4640 0x2200
#define PRID_IMP_R4650 0x2200
#define PRID_IMP_R4650 0x2200
#define PRID_IMP_R5000 0x2300
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_TX49 0x2d00
@ -61,7 +61,7 @@
#define PRID_IMP_MAGIC 0x2500
#define PRID_IMP_RM7000 0x2700
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_IMP_NEVADA 0x2800
#define PRID_IMP_NEVADA 0x2800
#define PRID_IMP_RM9000 0x3400
#define PRID_IMP_LOONGSON1 0x4200
#define PRID_IMP_R5432 0x5400
@ -108,11 +108,11 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_REV_TX3927 0x0040
#define PRID_REV_VR4111 0x0050
#define PRID_REV_VR4181 0x0050
#define PRID_REV_VR4181 0x0050
#define PRID_REV_VR4121 0x0060
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PRID_REV_VR4122 0x0070
#define PRID_REV_VR4181A 0x0070
#define PRID_REV_VR4181A 0x0070
#define PRID_REV_VR4130 0x0080
#define PRID_REV_34K_V1_0_2 0x0022
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -157,39 +157,39 @@ enum cpu_type_enum {
#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
#define MIPS_CPU_TLB 0x00000001
#define MIPS_CPU_4KEX 0x00000002
#define MIPS_CPU_3K_CACHE 0x00000004
#define MIPS_CPU_TLB 0x00000001
#define MIPS_CPU_4KEX 0x00000002
#define MIPS_CPU_3K_CACHE 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_4K_CACHE 0x00000008
#define MIPS_CPU_TX39_CACHE 0x00000010
#define MIPS_CPU_FPU 0x00000020
#define MIPS_CPU_32FPR 0x00000040
#define MIPS_CPU_4K_CACHE 0x00000008
#define MIPS_CPU_TX39_CACHE 0x00000010
#define MIPS_CPU_FPU 0x00000020
#define MIPS_CPU_32FPR 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_COUNTER 0x00000080
#define MIPS_CPU_WATCH 0x00000100
#define MIPS_CPU_DIVEC 0x00000200
#define MIPS_CPU_VCE 0x00000400
#define MIPS_CPU_COUNTER 0x00000080
#define MIPS_CPU_WATCH 0x00000100
#define MIPS_CPU_DIVEC 0x00000200
#define MIPS_CPU_VCE 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_CACHE_CDEX_P 0x00000800
#define MIPS_CPU_CACHE_CDEX_S 0x00001000
#define MIPS_CPU_MCHECK 0x00002000
#define MIPS_CPU_EJTAG 0x00004000
#define MIPS_CPU_CACHE_CDEX_P 0x00000800
#define MIPS_CPU_CACHE_CDEX_S 0x00001000
#define MIPS_CPU_MCHECK 0x00002000
#define MIPS_CPU_EJTAG 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_NOFPUEX 0x00008000
#define MIPS_CPU_LLSC 0x00010000
#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000
#define MIPS_CPU_PREFETCH 0x00040000
#define MIPS_CPU_NOFPUEX 0x00008000
#define MIPS_CPU_LLSC 0x00010000
#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000
#define MIPS_CPU_PREFETCH 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_CPU_VINT 0x00080000
#define MIPS_CPU_VEIC 0x00100000
#define MIPS_CPU_ULRI 0x00200000
#define MIPS_ASE_MIPS16 0x00000001
#define MIPS_CPU_VINT 0x00080000
#define MIPS_CPU_VEIC 0x00100000
#define MIPS_CPU_ULRI 0x00200000
#define MIPS_ASE_MIPS16 0x00000001
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_ASE_MDMX 0x00000002
#define MIPS_ASE_MIPS3D 0x00000004
#define MIPS_ASE_SMARTMIPS 0x00000008
#define MIPS_ASE_DSP 0x00000010
#define MIPS_ASE_MDMX 0x00000002
#define MIPS_ASE_MIPS3D 0x00000004
#define MIPS_ASE_SMARTMIPS 0x00000008
#define MIPS_ASE_DSP 0x00000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_ASE_MIPSMT 0x00000020
#define MIPS_ASE_MIPSMT 0x00000020
#endif

28
libc/kernel/arch-mips/asm/dec/ecc.h
View File

@ -18,23 +18,23 @@
****************************************************************************/
#ifndef __ASM_MIPS_DEC_ECC_H
#define __ASM_MIPS_DEC_ECC_H
#define KN0X_EAR_VALID (1<<31)
#define KN0X_EAR_CPU (1<<30)
#define KN0X_EAR_VALID (1<<31)
#define KN0X_EAR_CPU (1<<30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN0X_EAR_WRITE (1<<29)
#define KN0X_EAR_ECCERR (1<<28)
#define KN0X_EAR_RES_27 (1<<27)
#define KN0X_EAR_ADDRESS (0x7ffffff<<0)
#define KN0X_EAR_WRITE (1<<29)
#define KN0X_EAR_ECCERR (1<<28)
#define KN0X_EAR_RES_27 (1<<27)
#define KN0X_EAR_ADDRESS (0x7ffffff<<0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN0X_ESR_VLDHI (1<<31)
#define KN0X_ESR_CHKHI (0x7f<<24)
#define KN0X_ESR_SNGHI (1<<23)
#define KN0X_ESR_SYNHI (0x7f<<16)
#define KN0X_ESR_VLDHI (1<<31)
#define KN0X_ESR_CHKHI (0x7f<<24)
#define KN0X_ESR_SNGHI (1<<23)
#define KN0X_ESR_SYNHI (0x7f<<16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN0X_ESR_VLDLO (1<<15)
#define KN0X_ESR_CHKLO (0x7f<<8)
#define KN0X_ESR_SNGLO (1<<7)
#define KN0X_ESR_SYNLO (0x7f<<0)
#define KN0X_ESR_VLDLO (1<<15)
#define KN0X_ESR_CHKLO (0x7f<<8)
#define KN0X_ESR_SNGLO (1<<7)
#define KN0X_ESR_SYNLO (0x7f<<0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef __ASSEMBLY__
#include <linux/interrupt.h>

162
libc/kernel/arch-mips/asm/dec/ioasic_addrs.h
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@ -19,106 +19,106 @@
#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
#define __ASM_MIPS_DEC_IOASIC_ADDRS_H
#define IOASIC_SLOT_SIZE 0x00040000
#define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE)
#define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE)
#define IOASIC_ESAR (2*IOASIC_SLOT_SIZE)
#define IOASIC_LANCE (3*IOASIC_SLOT_SIZE)
#define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE)
#define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE)
#define IOASIC_ESAR (2*IOASIC_SLOT_SIZE)
#define IOASIC_LANCE (3*IOASIC_SLOT_SIZE)
#define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE)
#define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE)
#define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE)
#define IOASIC_TOY (8*IOASIC_SLOT_SIZE)
#define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE)
#define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE)
#define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE)
#define IOASIC_TOY (8*IOASIC_SLOT_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOASIC_ISDN (9*IOASIC_SLOT_SIZE)
#define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE)
#define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE)
#define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE)
#define IOASIC_ISDN (9*IOASIC_SLOT_SIZE)
#define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE)
#define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE)
#define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOASIC_MCR (11*IOASIC_SLOT_SIZE)
#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE)
#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE)
#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE)
#define IOASIC_MCR (11*IOASIC_SLOT_SIZE)
#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE)
#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE)
#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE)
#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE)
#define IO_REG_SCSI_DMA_P 0x00
#define IO_REG_SCSI_DMA_BP 0x10
#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE)
#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE)
#define IO_REG_SCSI_DMA_P 0x00
#define IO_REG_SCSI_DMA_BP 0x10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_LANCE_DMA_P 0x20
#define IO_REG_SCC0A_T_DMA_P 0x30
#define IO_REG_SCC0A_R_DMA_P 0x40
#define IO_REG_SCC1A_T_DMA_P 0x50
#define IO_REG_LANCE_DMA_P 0x20
#define IO_REG_SCC0A_T_DMA_P 0x30
#define IO_REG_SCC0A_R_DMA_P 0x40
#define IO_REG_SCC1A_T_DMA_P 0x50
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_SCC1A_R_DMA_P 0x60
#define IO_REG_AB_T_DMA_P 0x50
#define IO_REG_AB_R_DMA_P 0x60
#define IO_REG_FLOPPY_DMA_P 0x70
#define IO_REG_SCC1A_R_DMA_P 0x60
#define IO_REG_AB_T_DMA_P 0x50
#define IO_REG_AB_R_DMA_P 0x60
#define IO_REG_FLOPPY_DMA_P 0x70
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_ISDN_T_DMA_P 0x80
#define IO_REG_ISDN_T_DMA_BP 0x90
#define IO_REG_ISDN_R_DMA_P 0xa0
#define IO_REG_ISDN_R_DMA_BP 0xb0
#define IO_REG_ISDN_T_DMA_P 0x80
#define IO_REG_ISDN_T_DMA_BP 0x90
#define IO_REG_ISDN_R_DMA_P 0xa0
#define IO_REG_ISDN_R_DMA_BP 0xb0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_DATA_0 0xc0
#define IO_REG_DATA_1 0xd0
#define IO_REG_DATA_2 0xe0
#define IO_REG_DATA_3 0xf0
#define IO_REG_DATA_0 0xc0
#define IO_REG_DATA_1 0xd0
#define IO_REG_DATA_2 0xe0
#define IO_REG_DATA_3 0xf0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_SSR 0x100
#define IO_REG_SIR 0x110
#define IO_REG_SIMR 0x120
#define IO_REG_SAR 0x130
#define IO_REG_SSR 0x100
#define IO_REG_SIR 0x110
#define IO_REG_SIMR 0x120
#define IO_REG_SAR 0x130
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_ISDN_T_DATA 0x140
#define IO_REG_ISDN_R_DATA 0x150
#define IO_REG_LANCE_SLOT 0x160
#define IO_REG_SCSI_SLOT 0x170
#define IO_REG_ISDN_T_DATA 0x140
#define IO_REG_ISDN_R_DATA 0x150
#define IO_REG_LANCE_SLOT 0x160
#define IO_REG_SCSI_SLOT 0x170
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_SCC0A_SLOT 0x180
#define IO_REG_SCC1A_SLOT 0x190
#define IO_REG_AB_SLOT 0x190
#define IO_REG_FLOPPY_SLOT 0x1a0
#define IO_REG_SCC0A_SLOT 0x180
#define IO_REG_SCC1A_SLOT 0x190
#define IO_REG_AB_SLOT 0x190
#define IO_REG_FLOPPY_SLOT 0x1a0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_SCSI_SCR 0x1b0
#define IO_REG_SCSI_SDR0 0x1c0
#define IO_REG_SCSI_SDR1 0x1d0
#define IO_REG_FCTR 0x1e0
#define IO_REG_SCSI_SCR 0x1b0
#define IO_REG_SCSI_SDR0 0x1c0
#define IO_REG_SCSI_SDR1 0x1d0
#define IO_REG_FCTR 0x1e0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_REG_RES_31 0x1f0
#define IO_SSR_SCC0A_TX_DMA_EN (1<<31)
#define IO_SSR_SCC0A_RX_DMA_EN (1<<30)
#define IO_SSR_RES_27 (1<<27)
#define IO_REG_RES_31 0x1f0
#define IO_SSR_SCC0A_TX_DMA_EN (1<<31)
#define IO_SSR_SCC0A_RX_DMA_EN (1<<30)
#define IO_SSR_RES_27 (1<<27)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_SSR_RES_26 (1<<26)
#define IO_SSR_RES_25 (1<<25)
#define IO_SSR_RES_24 (1<<24)
#define IO_SSR_RES_23 (1<<23)
#define IO_SSR_RES_26 (1<<26)
#define IO_SSR_RES_25 (1<<25)
#define IO_SSR_RES_24 (1<<24)
#define IO_SSR_RES_23 (1<<23)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_SSR_SCSI_DMA_DIR (1<<18)
#define IO_SSR_SCSI_DMA_EN (1<<17)
#define IO_SSR_LANCE_DMA_EN (1<<16)
#define IO_SSR_SCC1A_TX_DMA_EN (1<<29)
#define IO_SSR_SCSI_DMA_DIR (1<<18)
#define IO_SSR_SCSI_DMA_EN (1<<17)
#define IO_SSR_LANCE_DMA_EN (1<<16)
#define IO_SSR_SCC1A_TX_DMA_EN (1<<29)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_SSR_SCC1A_RX_DMA_EN (1<<28)
#define IO_SSR_RES_22 (1<<22)
#define IO_SSR_RES_21 (1<<21)
#define IO_SSR_RES_20 (1<<20)
#define IO_SSR_SCC1A_RX_DMA_EN (1<<28)
#define IO_SSR_RES_22 (1<<22)
#define IO_SSR_RES_21 (1<<21)
#define IO_SSR_RES_20 (1<<20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_SSR_RES_19 (1<<19)
#define IO_SSR_AB_TX_DMA_EN (1<<29)
#define IO_SSR_AB_RX_DMA_EN (1<<28)
#define IO_SSR_FLOPPY_DMA_DIR (1<<22)
#define IO_SSR_RES_19 (1<<19)
#define IO_SSR_AB_TX_DMA_EN (1<<29)
#define IO_SSR_AB_RX_DMA_EN (1<<28)
#define IO_SSR_FLOPPY_DMA_DIR (1<<22)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_SSR_FLOPPY_DMA_EN (1<<21)
#define IO_SSR_ISDN_TX_DMA_EN (1<<20)
#define IO_SSR_ISDN_RX_DMA_EN (1<<19)
#define KN0X_IO_SSR_DIAGDN (1<<15)
#define IO_SSR_FLOPPY_DMA_EN (1<<21)
#define IO_SSR_ISDN_TX_DMA_EN (1<<20)
#define IO_SSR_ISDN_RX_DMA_EN (1<<19)
#define KN0X_IO_SSR_DIAGDN (1<<15)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN0X_IO_SSR_SCC_RST (1<<11)
#define KN0X_IO_SSR_RTC_RST (1<<10)
#define KN0X_IO_SSR_ASC_RST (1<<9)
#define KN0X_IO_SSR_LANCE_RST (1<<8)
#define KN0X_IO_SSR_SCC_RST (1<<11)
#define KN0X_IO_SSR_RTC_RST (1<<10)
#define KN0X_IO_SSR_ASC_RST (1<<9)
#define KN0X_IO_SSR_LANCE_RST (1<<8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

52
libc/kernel/arch-mips/asm/dec/kn02xa.h
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@ -21,38 +21,38 @@
#include <asm/dec/ioasic_addrs.h>
#define KN02XA_SLOT_BASE 0x1c000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_MER 0x0c400000
#define KN02XA_MSR 0x0c800000
#define KN02XA_MEM_CONF 0x0e000000
#define KN02XA_EAR 0x0e000004
#define KN02XA_MER 0x0c400000
#define KN02XA_MSR 0x0c800000
#define KN02XA_MEM_CONF 0x0e000000
#define KN02XA_EAR 0x0e000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_BOOT0 0x0e000008
#define KN02XA_MEM_INTR 0x0e00000c
#define KN02XA_MER_RES_28 (0xf<<28)
#define KN02XA_MER_RES_17 (0x3ff<<17)
#define KN02XA_BOOT0 0x0e000008
#define KN02XA_MEM_INTR 0x0e00000c
#define KN02XA_MER_RES_28 (0xf<<28)
#define KN02XA_MER_RES_17 (0x3ff<<17)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_MER_PAGERR (1<<16)
#define KN02XA_MER_TRANSERR (1<<15)
#define KN02XA_MER_PARDIS (1<<14)
#define KN02XA_MER_SIZE (1<<13)
#define KN02XA_MER_PAGERR (1<<16)
#define KN02XA_MER_TRANSERR (1<<15)
#define KN02XA_MER_PARDIS (1<<14)
#define KN02XA_MER_SIZE (1<<13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_MER_RES_12 (1<<12)
#define KN02XA_MER_BYTERR (0xf<<8)
#define KN02XA_MER_BYTERR_3 (0x8<<8)
#define KN02XA_MER_BYTERR_2 (0x4<<8)
#define KN02XA_MER_RES_12 (1<<12)
#define KN02XA_MER_BYTERR (0xf<<8)
#define KN02XA_MER_BYTERR_3 (0x8<<8)
#define KN02XA_MER_BYTERR_2 (0x4<<8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_MER_BYTERR_1 (0x2<<8)
#define KN02XA_MER_BYTERR_0 (0x1<<8)
#define KN02XA_MER_RES_0 (0xff<<0)
#define KN02XA_MSR_RES_27 (0x1f<<27)
#define KN02XA_MER_BYTERR_1 (0x2<<8)
#define KN02XA_MER_BYTERR_0 (0x1<<8)
#define KN02XA_MER_RES_0 (0xff<<0)
#define KN02XA_MSR_RES_27 (0x1f<<27)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_MSR_RES_14 (0x7<<14)
#define KN02XA_MSR_SIZE (1<<13)
#define KN02XA_MSR_RES_0 (0x1fff<<0)
#define KN02XA_EAR_RES_29 (0x7<<29)
#define KN02XA_MSR_RES_14 (0x7<<14)
#define KN02XA_MSR_SIZE (1<<13)
#define KN02XA_MSR_RES_0 (0x1fff<<0)
#define KN02XA_EAR_RES_29 (0x7<<29)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KN02XA_EAR_ADDRESS (0x7ffffff<<2)
#define KN02XA_EAR_RES_0 (0x3<<0)
#define KN02XA_EAR_ADDRESS (0x7ffffff<<2)
#define KN02XA_EAR_RES_0 (0x3<<0)
#ifndef __ASSEMBLY__
#include <linux/interrupt.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

60
libc/kernel/arch-mips/asm/dma.h
View File

@ -18,8 +18,8 @@
****************************************************************************/
#ifndef _ASM_DMA_H
#define _ASM_DMA_H
#include <asm/io.h>
#include <linux/spinlock.h>
#include <asm/io.h>
#include <linux/spinlock.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <linux/delay.h>
#include <asm/system.h>
@ -36,34 +36,34 @@
#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_DMA1_BASE 0x00
#define IO_DMA2_BASE 0xC0
#define DMA1_CMD_REG 0x08
#define DMA1_STAT_REG 0x08
#define IO_DMA1_BASE 0x00
#define IO_DMA2_BASE 0xC0
#define DMA1_CMD_REG 0x08
#define DMA1_STAT_REG 0x08
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA1_REQ_REG 0x09
#define DMA1_MASK_REG 0x0A
#define DMA1_MODE_REG 0x0B
#define DMA1_CLEAR_FF_REG 0x0C
#define DMA1_REQ_REG 0x09
#define DMA1_MASK_REG 0x0A
#define DMA1_MODE_REG 0x0B
#define DMA1_CLEAR_FF_REG 0x0C
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA1_TEMP_REG 0x0D
#define DMA1_RESET_REG 0x0D
#define DMA1_CLR_MASK_REG 0x0E
#define DMA1_MASK_ALL_REG 0x0F
#define DMA1_TEMP_REG 0x0D
#define DMA1_RESET_REG 0x0D
#define DMA1_CLR_MASK_REG 0x0E
#define DMA1_MASK_ALL_REG 0x0F
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA2_CMD_REG 0xD0
#define DMA2_STAT_REG 0xD0
#define DMA2_REQ_REG 0xD2
#define DMA2_MASK_REG 0xD4
#define DMA2_CMD_REG 0xD0
#define DMA2_STAT_REG 0xD0
#define DMA2_REQ_REG 0xD2
#define DMA2_MASK_REG 0xD4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA2_MODE_REG 0xD6
#define DMA2_CLEAR_FF_REG 0xD8
#define DMA2_TEMP_REG 0xDA
#define DMA2_RESET_REG 0xDA
#define DMA2_MODE_REG 0xD6
#define DMA2_CLEAR_FF_REG 0xD8
#define DMA2_TEMP_REG 0xDA
#define DMA2_RESET_REG 0xDA
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA2_CLR_MASK_REG 0xDC
#define DMA2_MASK_ALL_REG 0xDE
#define DMA_ADDR_0 0x00
#define DMA2_CLR_MASK_REG 0xDC
#define DMA2_MASK_ALL_REG 0xDE
#define DMA_ADDR_0 0x00
#define DMA_ADDR_1 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_ADDR_2 0x04
@ -73,7 +73,7 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_ADDR_6 0xC8
#define DMA_ADDR_7 0xCC
#define DMA_CNT_0 0x01
#define DMA_CNT_0 0x01
#define DMA_CNT_1 0x03
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_CNT_2 0x05
@ -83,7 +83,7 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_CNT_6 0xCA
#define DMA_CNT_7 0xCE
#define DMA_PAGE_0 0x87
#define DMA_PAGE_0 0x87
#define DMA_PAGE_1 0x83
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_PAGE_2 0x81
@ -92,9 +92,9 @@
#define DMA_PAGE_6 0x89
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_PAGE_7 0x8A
#define DMA_MODE_READ 0x44
#define DMA_MODE_WRITE 0x48
#define DMA_MODE_CASCADE 0xC0
#define DMA_MODE_READ 0x44
#define DMA_MODE_WRITE 0x48
#define DMA_MODE_CASCADE 0xC0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_AUTOINIT 0x10
#define isa_dma_bridge_buggy (0)

198
libc/kernel/arch-mips/asm/errno.h
View File

@ -19,128 +19,128 @@
#ifndef _ASM_ERRNO_H
#define _ASM_ERRNO_H
#include <asm-generic/errno-base.h>
#define ENOMSG 35
#define ENOMSG 35
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EIDRM 36
#define ECHRNG 37
#define EL2NSYNC 38
#define EL3HLT 39
#define EIDRM 36
#define ECHRNG 37
#define EL2NSYNC 38
#define EL3HLT 39
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EL3RST 40
#define ELNRNG 41
#define EUNATCH 42
#define ENOCSI 43
#define EL3RST 40
#define ELNRNG 41
#define EUNATCH 42
#define ENOCSI 43
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EL2HLT 44
#define EDEADLK 45
#define ENOLCK 46
#define EBADE 50
#define EL2HLT 44
#define EDEADLK 45
#define ENOLCK 46
#define EBADE 50
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EBADR 51
#define EXFULL 52
#define ENOANO 53
#define EBADRQC 54
#define EBADR 51
#define EXFULL 52
#define ENOANO 53
#define EBADRQC 54
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EBADSLT 55
#define EDEADLOCK 56
#define EBFONT 59
#define ENOSTR 60
#define EBADSLT 55
#define EDEADLOCK 56
#define EBFONT 59
#define ENOSTR 60
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENODATA 61
#define ETIME 62
#define ENOSR 63
#define ENONET 64
#define ENODATA 61
#define ETIME 62
#define ENOSR 63
#define ENONET 64
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENOPKG 65
#define EREMOTE 66
#define ENOLINK 67
#define EADV 68
#define ENOPKG 65
#define EREMOTE 66
#define ENOLINK 67
#define EADV 68
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ESRMNT 69
#define ECOMM 70
#define EPROTO 71
#define EDOTDOT 73
#define ESRMNT 69
#define ECOMM 70
#define EPROTO 71
#define EDOTDOT 73
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EMULTIHOP 74
#define EBADMSG 77
#define ENAMETOOLONG 78
#define EOVERFLOW 79
#define EMULTIHOP 74
#define EBADMSG 77
#define ENAMETOOLONG 78
#define EOVERFLOW 79
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENOTUNIQ 80
#define EBADFD 81
#define EREMCHG 82
#define ELIBACC 83
#define ENOTUNIQ 80
#define EBADFD 81
#define EREMCHG 82
#define ELIBACC 83
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ELIBBAD 84
#define ELIBSCN 85
#define ELIBMAX 86
#define ELIBEXEC 87
#define ELIBBAD 84
#define ELIBSCN 85
#define ELIBMAX 86
#define ELIBEXEC 87
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EILSEQ 88
#define ENOSYS 89
#define ELOOP 90
#define ERESTART 91
#define EILSEQ 88
#define ENOSYS 89
#define ELOOP 90
#define ERESTART 91
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ESTRPIPE 92
#define ENOTEMPTY 93
#define EUSERS 94
#define ENOTSOCK 95
#define ESTRPIPE 92
#define ENOTEMPTY 93
#define EUSERS 94
#define ENOTSOCK 95
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EDESTADDRREQ 96
#define EMSGSIZE 97
#define EPROTOTYPE 98
#define ENOPROTOOPT 99
#define EDESTADDRREQ 96
#define EMSGSIZE 97
#define EPROTOTYPE 98
#define ENOPROTOOPT 99
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EPROTONOSUPPORT 120
#define ESOCKTNOSUPPORT 121
#define EOPNOTSUPP 122
#define EPFNOSUPPORT 123
#define EPROTONOSUPPORT 120
#define ESOCKTNOSUPPORT 121
#define EOPNOTSUPP 122
#define EPFNOSUPPORT 123
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EAFNOSUPPORT 124
#define EADDRINUSE 125
#define EADDRNOTAVAIL 126
#define ENETDOWN 127
#define EAFNOSUPPORT 124
#define EADDRINUSE 125
#define EADDRNOTAVAIL 126
#define ENETDOWN 127
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENETUNREACH 128
#define ENETRESET 129
#define ECONNABORTED 130
#define ECONNRESET 131
#define ENETUNREACH 128
#define ENETRESET 129
#define ECONNABORTED 130
#define ECONNRESET 131
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENOBUFS 132
#define EISCONN 133
#define ENOTCONN 134
#define EUCLEAN 135
#define ENOBUFS 132
#define EISCONN 133
#define ENOTCONN 134
#define EUCLEAN 135
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENOTNAM 137
#define ENAVAIL 138
#define EISNAM 139
#define EREMOTEIO 140
#define ENOTNAM 137
#define ENAVAIL 138
#define EISNAM 139
#define EREMOTEIO 140
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EINIT 141
#define EREMDEV 142
#define ESHUTDOWN 143
#define ETOOMANYREFS 144
#define EINIT 141
#define EREMDEV 142
#define ESHUTDOWN 143
#define ETOOMANYREFS 144
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ETIMEDOUT 145
#define ECONNREFUSED 146
#define EHOSTDOWN 147
#define EHOSTUNREACH 148
#define ETIMEDOUT 145
#define ECONNREFUSED 146
#define EHOSTDOWN 147
#define EHOSTUNREACH 148
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EWOULDBLOCK EAGAIN
#define EALREADY 149
#define EINPROGRESS 150
#define ESTALE 151
#define EWOULDBLOCK EAGAIN
#define EALREADY 149
#define EINPROGRESS 150
#define ESTALE 151
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ECANCELED 158
#define ENOMEDIUM 159
#define EMEDIUMTYPE 160
#define ENOKEY 161
#define ECANCELED 158
#define ENOMEDIUM 159
#define EMEDIUMTYPE 160
#define ENOKEY 161
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EKEYEXPIRED 162
#define EKEYREVOKED 163
#define EKEYREJECTED 164
#define EOWNERDEAD 165
#define EKEYEXPIRED 162
#define EKEYREVOKED 163
#define EKEYREJECTED 164
#define EOWNERDEAD 165
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ENOTRECOVERABLE 166
#define EDQUOT 1133
#define ENOTRECOVERABLE 166
#define EDQUOT 1133
#endif

20
libc/kernel/arch-mips/asm/fcntl.h
View File

@ -22,23 +22,23 @@
#define O_SYNC 0x0010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define O_NONBLOCK 0x0080
#define O_CREAT 0x0100
#define O_TRUNC 0x0200
#define O_EXCL 0x0400
#define O_CREAT 0x0100
#define O_TRUNC 0x0200
#define O_EXCL 0x0400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define O_NOCTTY 0x0800
#define FASYNC 0x1000
#define O_LARGEFILE 0x2000
#define O_DIRECT 0x8000
#define O_NOCTTY 0x0800
#define FASYNC 0x1000
#define O_LARGEFILE 0x2000
#define O_DIRECT 0x8000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define F_GETLK 14
#define F_SETLK 6
#define F_SETLKW 7
#define F_SETOWN 24
#define F_SETOWN 24
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define F_GETOWN 23
#define F_GETOWN 23
#ifndef __mips64
#define F_GETLK64 33
#define F_GETLK64 33
#define F_SETLK64 34
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define F_SETLKW64 35

2
libc/kernel/arch-mips/asm/floppy.h
View File

@ -24,7 +24,7 @@
#define FLOPPY0_TYPE fd_drive_type(0)
#define FLOPPY1_TYPE fd_drive_type(1)
#define FDC1 fd_getfdaddr1();
#define N_FDC 1
#define N_FDC 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define N_DRIVE 8
#define CROSS_64KB(a, s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)

18
libc/kernel/arch-mips/asm/fpregdef.h
View File

@ -21,17 +21,17 @@
#include <asm/sgidefs.h>
#if _MIPS_SIM == _MIPS_SIM_ABI32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fv0 $f0
#define fv0 $f0
#define fv0f $f1
#define fv1 $f2
#define fv1f $f3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fa0 $f12
#define fa0 $f12
#define fa0f $f13
#define fa1 $f14
#define fa1f $f15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ft0 $f4
#define ft0 $f4
#define ft0f $f5
#define ft1 $f6
#define ft1f $f7
@ -46,7 +46,7 @@
#define ft5 $f18
#define ft5f $f19
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fs0 $f20
#define fs0 $f20
#define fs0f $f21
#define fs1 $f22
#define fs1f $f23
@ -61,13 +61,13 @@
#define fs5 $f30
#define fs5f $f31
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fcr31 $31
#define fcr31 $31
#endif
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
#define fv0 $f0
#define fv0 $f0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fv1 $f2
#define fa0 $f12
#define fa0 $f12
#define fa1 $f13
#define fa2 $f14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -77,7 +77,7 @@
#define fa6 $f18
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fa7 $f19
#define ft0 $f4
#define ft0 $f4
#define ft1 $f5
#define ft2 $f6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -94,7 +94,7 @@
#define ft11 $f23
#define ft12 $f1
#define ft13 $f3
#define fs0 $f24
#define fs0 $f24
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define fs1 $f25
#define fs2 $f26

20
libc/kernel/arch-mips/asm/gt64120.h
View File

@ -69,10 +69,10 @@
#define GT_PCI1M1REMAP_OFS 0x118
#define GT_CPUERR_ADDRLO_OFS 0x070
#define GT_CPUERR_ADDRHI_OFS 0x078
#define GT_CPUERR_DATALO_OFS 0x128
#define GT_CPUERR_DATALO_OFS 0x128
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_CPUERR_DATAHI_OFS 0x130
#define GT_CPUERR_PARITY_OFS 0x138
#define GT_CPUERR_DATAHI_OFS 0x130
#define GT_CPUERR_PARITY_OFS 0x138
#define GT_PCI0SYNC_OFS 0x0c0
#define GT_PCI1SYNC_OFS 0x0c8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -116,12 +116,12 @@
#define GT_DEV_B3_OFS 0x468
#define GT_DEV_BOOT_OFS 0x46c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_ECC_ERRDATALO 0x480
#define GT_ECC_ERRDATAHI 0x484
#define GT_ECC_MEM 0x488
#define GT_ECC_CALC 0x48c
#define GT_ECC_ERRDATALO 0x480
#define GT_ECC_ERRDATAHI 0x484
#define GT_ECC_MEM 0x488
#define GT_ECC_CALC 0x48c
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_ECC_ERRADDR 0x490
#define GT_ECC_ERRADDR 0x490
#define GT_DMA0_CNT_OFS 0x800
#define GT_DMA1_CNT_OFS 0x804
#define GT_DMA2_CNT_OFS 0x808
@ -518,8 +518,8 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL
#define GT_DEF_BASE 0x14000000UL
#define GT_MAX_BANKSIZE (256 * 1024 * 1024)
#define GT_LATTIM_MIN 6
#define GT_MAX_BANKSIZE (256 * 1024 * 1024)
#define GT_LATTIM_MIN 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <mach-gt64120.h>
#define __GT_READ(ofs) (*(volatile u32 *)(GT64120_BASE+(ofs)))

2
libc/kernel/arch-mips/asm/hardirq.h
View File

@ -24,6 +24,6 @@
typedef struct {
unsigned int __softirq_pending;
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h>
#include <linux/irq_cpustat.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

2
libc/kernel/arch-mips/asm/io.h
View File

@ -77,7 +77,7 @@
#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) static inline void pfx##out##bwlq##p(type val, unsigned long port) { volatile type *__addr; type __val; __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); __val = pfx##ioswab##bwlq(__addr, val); BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); *__addr = __val; slow; } static inline type pfx##in##bwlq##p(unsigned long port) { volatile type *__addr; type __val; __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); __val = *__addr; slow; return pfx##ioswab##bwlq(__addr, __val); }
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __BUILD_MEMORY_PFX(bus, bwlq, type) __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
#define BUILDIO_MEM(bwlq, type) __BUILD_MEMORY_PFX(__raw_, bwlq, type) __BUILD_MEMORY_PFX(, bwlq, type) __BUILD_MEMORY_PFX(__mem_, bwlq, type)
#define BUILDIO_MEM(bwlq, type) __BUILD_MEMORY_PFX(__raw_, bwlq, type) __BUILD_MEMORY_PFX(, bwlq, type) __BUILD_MEMORY_PFX(__mem_, bwlq, type)
#define __BUILD_IOPORT_PFX(bus, bwlq, type) __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
#define BUILDIO_IOPORT(bwlq, type) __BUILD_IOPORT_PFX(, bwlq, type) __BUILD_IOPORT_PFX(__mem_, bwlq, type)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

82
libc/kernel/arch-mips/asm/ioctls.h
View File

@ -21,7 +21,7 @@
#include <asm/ioctl.h>
#define TCGETA 0x5401
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSETA 0x5402
#define TCSETA 0x5402
#define TCSETAW 0x5403
#define TCSETAF 0x5404
#define TCSBRK 0x5405
@ -33,30 +33,30 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSETSW 0x540f
#define TCSETSF 0x5410
#define TIOCEXCL 0x740d
#define TIOCNXCL 0x740e
#define TIOCEXCL 0x740d
#define TIOCNXCL 0x740e
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCOUTQ 0x7472
#define TIOCSTI 0x5472
#define TIOCMGET 0x741d
#define TIOCMBIS 0x741b
#define TIOCOUTQ 0x7472
#define TIOCSTI 0x5472
#define TIOCMGET 0x741d
#define TIOCMBIS 0x741b
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCMBIC 0x741c
#define TIOCMSET 0x741a
#define TIOCPKT 0x5470
#define TIOCPKT_DATA 0x00
#define TIOCMBIC 0x741c
#define TIOCMSET 0x741a
#define TIOCPKT 0x5470
#define TIOCPKT_DATA 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCPKT_FLUSHREAD 0x01
#define TIOCPKT_FLUSHWRITE 0x02
#define TIOCPKT_STOP 0x04
#define TIOCPKT_START 0x08
#define TIOCPKT_FLUSHREAD 0x01
#define TIOCPKT_FLUSHWRITE 0x02
#define TIOCPKT_STOP 0x04
#define TIOCPKT_START 0x08
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCPKT_NOSTOP 0x10
#define TIOCPKT_DOSTOP 0x20
#define TIOCSWINSZ _IOW('t', 103, struct winsize)
#define TIOCGWINSZ _IOR('t', 104, struct winsize)
#define TIOCPKT_NOSTOP 0x10
#define TIOCPKT_DOSTOP 0x20
#define TIOCSWINSZ _IOW('t', 103, struct winsize)
#define TIOCGWINSZ _IOR('t', 104, struct winsize)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCNOTTY 0x5471
#define TIOCNOTTY 0x5471
#define TIOCSETD 0x7401
#define TIOCGETD 0x7400
#define FIOCLEX 0x6601
@ -66,30 +66,30 @@
#define FIONBIO 0x667e
#define FIOQSIZE 0x667f
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGLTC 0x7474
#define TIOCSLTC 0x7475
#define TIOCSPGRP _IOW('t', 118, int)
#define TIOCGPGRP _IOR('t', 119, int)
#define TIOCGLTC 0x7474
#define TIOCSLTC 0x7475
#define TIOCSPGRP _IOW('t', 118, int)
#define TIOCGPGRP _IOR('t', 119, int)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCCONS _IOW('t', 120, int)
#define TIOCCONS _IOW('t', 120, int)
#define FIONREAD 0x467f
#define TIOCINQ FIONREAD
#define TIOCGETP 0x7408
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCSETP 0x7409
#define TIOCSETN 0x740a
#define TIOCSBRK 0x5427
#define TIOCCBRK 0x5428
#define TIOCSETN 0x740a
#define TIOCSBRK 0x5427
#define TIOCCBRK 0x5428
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGSID 0x7416
#define TIOCGSID 0x7416
#define TCGETS2 _IOR('T', 0x2A, struct termios2)
#define TCSETS2 _IOW('T', 0x2B, struct termios2)
#define TCSETSW2 _IOW('T', 0x2C, struct termios2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSETSF2 _IOW('T', 0x2D, struct termios2)
#define TIOCGPTN _IOR('T', 0x30, unsigned int)
#define TIOCSPTLCK _IOW('T', 0x31, int)
#define TIOCSCTTY 0x5480
#define TIOCGPTN _IOR('T', 0x30, unsigned int)
#define TIOCSPTLCK _IOW('T', 0x31, int)
#define TIOCSCTTY 0x5480
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGSOFTCAR 0x5481
#define TIOCSSOFTCAR 0x5482
@ -97,22 +97,22 @@
#define TIOCGSERIAL 0x5484
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCSSERIAL 0x5485
#define TCSBRKP 0x5486
#define TCSBRKP 0x5486
#define TIOCSERCONFIG 0x5488
#define TIOCSERGWILD 0x5489
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCSERSWILD 0x548a
#define TIOCGLCKTRMIOS 0x548b
#define TIOCSLCKTRMIOS 0x548c
#define TIOCSERGSTRUCT 0x548d
#define TIOCSERGSTRUCT 0x548d
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCSERGETLSR 0x548e
#define TIOCSERGETMULTI 0x548f
#define TIOCSERSETMULTI 0x5490
#define TIOCMIWAIT 0x5491
#define TIOCSERGETLSR 0x548e
#define TIOCSERGETMULTI 0x548f
#define TIOCSERSETMULTI 0x5490
#define TIOCMIWAIT 0x5491
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGICOUNT 0x5492
#define TIOCGHAYESESP 0x5493
#define TIOCSHAYESESP 0x5494
#define TIOCGICOUNT 0x5492
#define TIOCGHAYESESP 0x5493
#define TIOCSHAYESESP 0x5494
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

16
libc/kernel/arch-mips/asm/ip32/crime.h
View File

@ -18,7 +18,7 @@
****************************************************************************/
#ifndef __ASM_CRIME_H__
#define __ASM_CRIME_H__
#define CRIME_BASE 0x14000000
#define CRIME_BASE 0x14000000
struct sgi_crime {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long id;
@ -108,13 +108,13 @@ struct sgi_crime {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_DOG_VALUE 0x00007fff
volatile unsigned long timer;
#define CRIME_MASTER_FREQ 66666500
#define CRIME_NS_PER_TICK 15
#define CRIME_MASTER_FREQ 66666500
#define CRIME_NS_PER_TICK 15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long cpu_error_addr;
#define CRIME_CPU_ERROR_ADDR_MASK 0x3ffffffff
volatile unsigned long cpu_error_stat;
#define CRIME_CPU_ERROR_MASK 0x7
#define CRIME_CPU_ERROR_MASK 0x7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4
#define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2
@ -123,16 +123,16 @@ struct sgi_crime {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long mc_ctrl;
volatile unsigned long bank_ctrl[8];
#define CRIME_MEM_BANK_CONTROL_MASK 0x11f
#define CRIME_MEM_BANK_CONTROL_MASK 0x11f
#define CRIME_MEM_BANK_CONTROL_ADDR 0x01f
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100
#define CRIME_MAXBANKS 8
volatile unsigned long mem_ref_counter;
#define CRIME_MEM_REF_COUNTER_MASK 0x3ff
#define CRIME_MEM_REF_COUNTER_MASK 0x3ff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long mem_error_stat;
#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff
#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff
#define CRIME_MEM_ERROR_MACE_ID 0x0000007f
#define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -167,5 +167,5 @@ struct sgi_crime {
#define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
#define CRIME_HI_MEM_BASE 0x40000000
#define CRIME_HI_MEM_BASE 0x40000000
#endif

10
libc/kernel/arch-mips/asm/ip32/mace.h
View File

@ -18,7 +18,7 @@
****************************************************************************/
#ifndef __ASM_MACE_H__
#define __ASM_MACE_H__
#define MACE_BASE 0x1f000000
#define MACE_BASE 0x1f000000
struct mace_pci {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned int error_addr;
@ -182,13 +182,13 @@ struct mace_isactrl {
#define MACEISA_RINGBUFFERS_SIZE (8 * 4096)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long misc;
#define MACEISA_FLASH_WE BIT(0)
#define MACEISA_PWD_CLEAR BIT(1)
#define MACEISA_FLASH_WE BIT(0)
#define MACEISA_PWD_CLEAR BIT(1)
#define MACEISA_NIC_DEASSERT BIT(2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MACEISA_NIC_DATA BIT(3)
#define MACEISA_LED_RED BIT(4)
#define MACEISA_LED_GREEN BIT(5)
#define MACEISA_LED_RED BIT(4)
#define MACEISA_LED_GREEN BIT(5)
#define MACEISA_DP_RAM_ENABLE BIT(6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile unsigned long istat;

2
libc/kernel/arch-mips/asm/irq.h
View File

@ -22,7 +22,7 @@
#include <asm/mipsmtregs.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <irq.h>
#define irq_canonicalize(irq) (irq)
#define irq_canonicalize(irq) (irq)
#define IRQ_AFFINITY_HOOK(irq) do { } while (0)
#define __DO_IRQ_SMTC_HOOK(irq) do { IRQ_AFFINITY_HOOK(irq); } while (0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

46
libc/kernel/arch-mips/asm/jazz.h
View File

@ -128,35 +128,35 @@ typedef struct {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_SERIAL2_IRQ (JAZZ_IRQ_START + 9)
#define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6)
#define JAZZ_SCSI_DMA 0
#define JAZZ_FLOPPY_DMA 1
#define JAZZ_SCSI_DMA 0
#define JAZZ_FLOPPY_DMA 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_AUDIOL_DMA 2
#define JAZZ_AUDIOR_DMA 3
#define JAZZ_R4030_CONFIG 0xE0000000
#define JAZZ_R4030_REVISION 0xE0000008
#define JAZZ_AUDIOL_DMA 2
#define JAZZ_AUDIOR_DMA 3
#define JAZZ_R4030_CONFIG 0xE0000000
#define JAZZ_R4030_REVISION 0xE0000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_R4030_INV_ADDR 0xE0000010
#define JAZZ_R4030_TRSTBL_BASE 0xE0000018
#define JAZZ_R4030_TRSTBL_LIM 0xE0000020
#define JAZZ_R4030_TRSTBL_INV 0xE0000028
#define JAZZ_R4030_INV_ADDR 0xE0000010
#define JAZZ_R4030_TRSTBL_BASE 0xE0000018
#define JAZZ_R4030_TRSTBL_LIM 0xE0000020
#define JAZZ_R4030_TRSTBL_INV 0xE0000028
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_R4030_CACHE_MTNC 0xE0000030
#define JAZZ_R4030_R_FAIL_ADDR 0xE0000038
#define JAZZ_R4030_M_FAIL_ADDR 0xE0000040
#define JAZZ_R4030_CACHE_PTAG 0xE0000048
#define JAZZ_R4030_CACHE_MTNC 0xE0000030
#define JAZZ_R4030_R_FAIL_ADDR 0xE0000038
#define JAZZ_R4030_M_FAIL_ADDR 0xE0000040
#define JAZZ_R4030_CACHE_PTAG 0xE0000048
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_R4030_CACHE_LTAG 0xE0000050
#define JAZZ_R4030_CACHE_BMASK 0xE0000058
#define JAZZ_R4030_CACHE_BWIN 0xE0000060
#define JAZZ_R4030_REM_SPEED 0xE0000070
#define JAZZ_R4030_CACHE_LTAG 0xE0000050
#define JAZZ_R4030_CACHE_BMASK 0xE0000058
#define JAZZ_R4030_CACHE_BWIN 0xE0000060
#define JAZZ_R4030_REM_SPEED 0xE0000070
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_R4030_IRQ_ENABLE 0xE00000E8
#define JAZZ_R4030_INVAL_ADDR 0xE0000010
#define JAZZ_R4030_IRQ_SOURCE 0xE0000200
#define JAZZ_R4030_I386_ERROR 0xE0000208
#define JAZZ_R4030_IRQ_ENABLE 0xE00000E8
#define JAZZ_R4030_INVAL_ADDR 0xE0000010
#define JAZZ_R4030_IRQ_SOURCE 0xE0000200
#define JAZZ_R4030_I386_ERROR 0xE0000208
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_EISA_IRQ_ACK 0xE0000238
#define JAZZ_EISA_IRQ_ACK 0xE0000238
#ifndef __ASSEMBLY__
#endif
#define JAZZ_FDC_BASE 0xe0003000

16
libc/kernel/arch-mips/asm/jazzdma.h
View File

@ -32,18 +32,18 @@ typedef volatile struct VDMA_PGTBL_ENTRY {
unsigned int owner;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} VDMA_PGTBL_ENTRY;
#define JAZZ_R4030_CHNL_MODE 0xE0000100
#define JAZZ_R4030_CHNL_ENABLE 0xE0000108
#define JAZZ_R4030_CHNL_COUNT 0xE0000110
#define JAZZ_R4030_CHNL_MODE 0xE0000100
#define JAZZ_R4030_CHNL_ENABLE 0xE0000108
#define JAZZ_R4030_CHNL_COUNT 0xE0000110
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define JAZZ_R4030_CHNL_ADDR 0xE0000118
#define JAZZ_R4030_CHNL_ADDR 0xE0000118
#define R4030_CHNL_ENABLE (1<<0)
#define R4030_CHNL_WRITE (1<<1)
#define R4030_TC_INTR (1<<8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R4030_MEM_INTR (1<<9)
#define R4030_ADDR_INTR (1<<10)
#define R4030_MODE_ATIME_40 (0)
#define R4030_MODE_ATIME_40 (0)
#define R4030_MODE_ATIME_80 (1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R4030_MODE_ATIME_120 (2)
@ -53,12 +53,12 @@ typedef volatile struct VDMA_PGTBL_ENTRY {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R4030_MODE_ATIME_280 (6)
#define R4030_MODE_ATIME_320 (7)
#define R4030_MODE_WIDTH_8 (1<<3)
#define R4030_MODE_WIDTH_8 (1<<3)
#define R4030_MODE_WIDTH_16 (2<<3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define R4030_MODE_WIDTH_32 (3<<3)
#define R4030_MODE_INTR_EN (1<<5)
#define R4030_MODE_BURST (1<<6)
#define R4030_MODE_FAST_ACK (1<<7)
#define R4030_MODE_BURST (1<<6)
#define R4030_MODE_FAST_ACK (1<<7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

2
libc/kernel/arch-mips/asm/lasat/lasat.h
View File

@ -131,7 +131,7 @@ struct lasat_eeprom_struct_pre7 {
#define LASAT_BMID_SAFEPIPE1000 7
#define LASAT_BMID_UNKNOWN 0xf
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define LASAT_MAX_BMID_NAMES 9
#define LASAT_MAX_BMID_NAMES 9
#define LASAT_HAS_EDHAC (1 << 0)
#define LASAT_EDHAC_FAST (1 << 1)
#define LASAT_HAS_EADI (1 << 2)

2
libc/kernel/arch-mips/asm/local.h
View File

@ -57,7 +57,7 @@ typedef struct
#define __local_sub(i, l) ((l)->a.counter-=(i))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_local_wrap_v(l) ({ local_t res__; preempt_disable(); res__ = (l); preempt_enable(); res__; })
#define cpu_local_wrap(l) ({ preempt_disable(); l; preempt_enable(); })
#define cpu_local_wrap(l) ({ preempt_disable(); l; preempt_enable(); })
#define cpu_local_read(l) cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
#define cpu_local_set(l, i) cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

170
libc/kernel/arch-mips/asm/mach-au1x00/au1000.h
View File

@ -132,7 +132,7 @@ struct au1xxx_irqmap {
#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
#define INTX 0xFF
#define INTX 0xFF
#define SYS_BASE 0xB1900000
#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -403,86 +403,86 @@ struct au1xxx_irqmap {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_BASE UART0_ADDR
#define UART_DEBUG_BASE UART3_ADDR
#define UART_RX 0
#define UART_TX 4
#define UART_RX 0
#define UART_TX 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_IER 8
#define UART_IIR 0xC
#define UART_FCR 0x10
#define UART_LCR 0x14
#define UART_IER 8
#define UART_IIR 0xC
#define UART_FCR 0x10
#define UART_LCR 0x14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_MCR 0x18
#define UART_LSR 0x1C
#define UART_MSR 0x20
#define UART_CLK 0x28
#define UART_MCR 0x18
#define UART_LSR 0x1C
#define UART_MSR 0x20
#define UART_CLK 0x28
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_MOD_CNTRL 0x100
#define UART_FCR_ENABLE_FIFO 0x01
#define UART_FCR_CLEAR_RCVR 0x02
#define UART_FCR_CLEAR_XMIT 0x04
#define UART_MOD_CNTRL 0x100
#define UART_FCR_ENABLE_FIFO 0x01
#define UART_FCR_CLEAR_RCVR 0x02
#define UART_FCR_CLEAR_XMIT 0x04
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_FCR_DMA_SELECT 0x08
#define UART_FCR_TRIGGER_MASK 0xF0
#define UART_FCR_R_TRIGGER_1 0x00
#define UART_FCR_R_TRIGGER_4 0x40
#define UART_FCR_DMA_SELECT 0x08
#define UART_FCR_TRIGGER_MASK 0xF0
#define UART_FCR_R_TRIGGER_1 0x00
#define UART_FCR_R_TRIGGER_4 0x40
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_FCR_R_TRIGGER_8 0x80
#define UART_FCR_R_TRIGGER_14 0xA0
#define UART_FCR_T_TRIGGER_0 0x00
#define UART_FCR_T_TRIGGER_4 0x10
#define UART_FCR_R_TRIGGER_8 0x80
#define UART_FCR_R_TRIGGER_14 0xA0
#define UART_FCR_T_TRIGGER_0 0x00
#define UART_FCR_T_TRIGGER_4 0x10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_FCR_T_TRIGGER_8 0x20
#define UART_FCR_T_TRIGGER_12 0x30
#define UART_LCR_SBC 0x40
#define UART_LCR_SPAR 0x20
#define UART_FCR_T_TRIGGER_8 0x20
#define UART_FCR_T_TRIGGER_12 0x30
#define UART_LCR_SBC 0x40
#define UART_LCR_SPAR 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_LCR_EPAR 0x10
#define UART_LCR_PARITY 0x08
#define UART_LCR_STOP 0x04
#define UART_LCR_WLEN5 0x00
#define UART_LCR_EPAR 0x10
#define UART_LCR_PARITY 0x08
#define UART_LCR_STOP 0x04
#define UART_LCR_WLEN5 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_LCR_WLEN6 0x01
#define UART_LCR_WLEN7 0x02
#define UART_LCR_WLEN8 0x03
#define UART_LSR_TEMT 0x40
#define UART_LCR_WLEN6 0x01
#define UART_LCR_WLEN7 0x02
#define UART_LCR_WLEN8 0x03
#define UART_LSR_TEMT 0x40
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_LSR_THRE 0x20
#define UART_LSR_BI 0x10
#define UART_LSR_FE 0x08
#define UART_LSR_PE 0x04
#define UART_LSR_THRE 0x20
#define UART_LSR_BI 0x10
#define UART_LSR_FE 0x08
#define UART_LSR_PE 0x04
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_LSR_OE 0x02
#define UART_LSR_DR 0x01
#define UART_IIR_NO_INT 0x01
#define UART_IIR_ID 0x06
#define UART_LSR_OE 0x02
#define UART_LSR_DR 0x01
#define UART_IIR_NO_INT 0x01
#define UART_IIR_ID 0x06
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_IIR_MSI 0x00
#define UART_IIR_THRI 0x02
#define UART_IIR_RDI 0x04
#define UART_IIR_RLSI 0x06
#define UART_IIR_MSI 0x00
#define UART_IIR_THRI 0x02
#define UART_IIR_RDI 0x04
#define UART_IIR_RLSI 0x06
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_IER_MSI 0x08
#define UART_IER_RLSI 0x04
#define UART_IER_THRI 0x02
#define UART_IER_RDI 0x01
#define UART_IER_MSI 0x08
#define UART_IER_RLSI 0x04
#define UART_IER_THRI 0x02
#define UART_IER_RDI 0x01
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_MCR_LOOP 0x10
#define UART_MCR_OUT2 0x08
#define UART_MCR_OUT1 0x04
#define UART_MCR_RTS 0x02
#define UART_MCR_LOOP 0x10
#define UART_MCR_OUT2 0x08
#define UART_MCR_OUT1 0x04
#define UART_MCR_RTS 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_MCR_DTR 0x01
#define UART_MSR_DCD 0x80
#define UART_MSR_RI 0x40
#define UART_MSR_DSR 0x20
#define UART_MCR_DTR 0x01
#define UART_MSR_DCD 0x80
#define UART_MSR_RI 0x40
#define UART_MSR_DSR 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_MSR_CTS 0x10
#define UART_MSR_DDCD 0x08
#define UART_MSR_TERI 0x04
#define UART_MSR_DDSR 0x02
#define UART_MSR_CTS 0x10
#define UART_MSR_DDCD 0x08
#define UART_MSR_TERI 0x04
#define UART_MSR_DDSR 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define UART_MSR_DCTS 0x01
#define UART_MSR_ANY_DELTA 0x0F
#define UART_MSR_DCTS 0x01
#define UART_MSR_ANY_DELTA 0x0F
#define SSI0_STATUS 0xB1600000
#define SSI_STATUS_BF (1 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -628,31 +628,31 @@ struct au1xxx_irqmap {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
#define SYS_PINFUNC 0xB190002C
#define SYS_PF_USB (1 << 15)
#define SYS_PF_U3 (1 << 14)
#define SYS_PF_USB (1 << 15)
#define SYS_PF_U3 (1 << 14)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_U2 (1 << 13)
#define SYS_PF_U1 (1 << 12)
#define SYS_PF_SRC (1 << 11)
#define SYS_PF_CK5 (1 << 10)
#define SYS_PF_U2 (1 << 13)
#define SYS_PF_U1 (1 << 12)
#define SYS_PF_SRC (1 << 11)
#define SYS_PF_CK5 (1 << 10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_CK4 (1 << 9)
#define SYS_PF_IRF (1 << 8)
#define SYS_PF_UR3 (1 << 7)
#define SYS_PF_I2D (1 << 6)
#define SYS_PF_CK4 (1 << 9)
#define SYS_PF_IRF (1 << 8)
#define SYS_PF_UR3 (1 << 7)
#define SYS_PF_I2D (1 << 6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_I2S (1 << 5)
#define SYS_PF_NI2 (1 << 4)
#define SYS_PF_U0 (1 << 3)
#define SYS_PF_RD (1 << 2)
#define SYS_PF_I2S (1 << 5)
#define SYS_PF_NI2 (1 << 4)
#define SYS_PF_U0 (1 << 3)
#define SYS_PF_RD (1 << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_A97 (1 << 1)
#define SYS_PF_S0 (1 << 0)
#define SYS_PF_PC (1 << 18)
#define SYS_PF_LCD (1 << 17)
#define SYS_PF_A97 (1 << 1)
#define SYS_PF_S0 (1 << 0)
#define SYS_PF_PC (1 << 18)
#define SYS_PF_LCD (1 << 17)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SYS_PF_CS (1 << 16)
#define SYS_PF_EX0 (1 << 9)
#define SYS_PF_CS (1 << 16)
#define SYS_PF_EX0 (1 << 9)
#define SYS_PF_PSC2_MASK (7 << 17)
#define SYS_PF_PSC2_AC97 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

32
libc/kernel/arch-mips/asm/mips-boards/msc01_pci.h
View File

@ -36,25 +36,25 @@
#define MSC01_PCI_CFGDATA_OFS 0x0618
#define MSC01_PCI_IACK_OFS 0x0620
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_HEAD0_OFS 0x2000
#define MSC01_PCI_HEAD1_OFS 0x2008
#define MSC01_PCI_HEAD2_OFS 0x2010
#define MSC01_PCI_HEAD3_OFS 0x2018
#define MSC01_PCI_HEAD0_OFS 0x2000
#define MSC01_PCI_HEAD1_OFS 0x2008
#define MSC01_PCI_HEAD2_OFS 0x2010
#define MSC01_PCI_HEAD3_OFS 0x2018
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_HEAD4_OFS 0x2020
#define MSC01_PCI_HEAD5_OFS 0x2028
#define MSC01_PCI_HEAD6_OFS 0x2030
#define MSC01_PCI_HEAD7_OFS 0x2038
#define MSC01_PCI_HEAD4_OFS 0x2020
#define MSC01_PCI_HEAD5_OFS 0x2028
#define MSC01_PCI_HEAD6_OFS 0x2030
#define MSC01_PCI_HEAD7_OFS 0x2038
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_HEAD8_OFS 0x2040
#define MSC01_PCI_HEAD9_OFS 0x2048
#define MSC01_PCI_HEAD10_OFS 0x2050
#define MSC01_PCI_HEAD11_OFS 0x2058
#define MSC01_PCI_HEAD8_OFS 0x2040
#define MSC01_PCI_HEAD9_OFS 0x2048
#define MSC01_PCI_HEAD10_OFS 0x2050
#define MSC01_PCI_HEAD11_OFS 0x2058
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_HEAD12_OFS 0x2060
#define MSC01_PCI_HEAD13_OFS 0x2068
#define MSC01_PCI_HEAD14_OFS 0x2070
#define MSC01_PCI_HEAD15_OFS 0x2078
#define MSC01_PCI_HEAD12_OFS 0x2060
#define MSC01_PCI_HEAD13_OFS 0x2068
#define MSC01_PCI_HEAD14_OFS 0x2070
#define MSC01_PCI_HEAD15_OFS 0x2078
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSC01_PCI_BAR0_OFS 0x2220
#define MSC01_PCI_CFG_OFS 0x2380

46
libc/kernel/arch-mips/asm/mipsregs.h
View File

@ -89,25 +89,25 @@
#define CP0_S1_DERRADDR0 $26
#define CP0_S1_DERRADDR1 $27
#define CP0_S1_INTCONTROL $20
#define CP0_S2_SRSCTL $12
#define CP0_S2_SRSCTL $12
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CP0_S3_SRSMAP $12
#define CP0_S3_SRSMAP $12
#define CP0_TX39_CACHE $7
#define CP1_REVISION $0
#define CP1_STATUS $31
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_FLUSH 0x01000000
#define FPU_CSR_COND 0x00800000
#define FPU_CSR_COND0 0x00800000
#define FPU_CSR_COND1 0x02000000
#define FPU_CSR_FLUSH 0x01000000
#define FPU_CSR_COND 0x00800000
#define FPU_CSR_COND0 0x00800000
#define FPU_CSR_COND1 0x02000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_COND2 0x04000000
#define FPU_CSR_COND3 0x08000000
#define FPU_CSR_COND4 0x10000000
#define FPU_CSR_COND5 0x20000000
#define FPU_CSR_COND2 0x04000000
#define FPU_CSR_COND3 0x08000000
#define FPU_CSR_COND4 0x10000000
#define FPU_CSR_COND5 0x20000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_COND6 0x40000000
#define FPU_CSR_COND7 0x80000000
#define FPU_CSR_COND6 0x40000000
#define FPU_CSR_COND7 0x80000000
#define FPU_CSR_ALL_X 0x0003f000
#define FPU_CSR_UNI_X 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -132,11 +132,11 @@
#define FPU_CSR_UDF_S 0x00000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_INE_S 0x00000004
#define FPU_CSR_RN 0x0
#define FPU_CSR_RZ 0x1
#define FPU_CSR_RU 0x2
#define FPU_CSR_RN 0x0
#define FPU_CSR_RZ 0x1
#define FPU_CSR_RU 0x2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPU_CSR_RD 0x3
#define FPU_CSR_RD 0x3
#define PM_4K 0x00000000
#define PM_16K 0x00006000
#define PM_64K 0x0001e000
@ -302,7 +302,7 @@
#define ST0_CU2 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ST0_CU3 0x80000000
#define ST0_XX 0x80000000
#define ST0_XX 0x80000000
#define CAUSEB_EXCCODE 2
#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -411,7 +411,7 @@
#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
#define TX49_CONF_DC (_ULCAST_(1) << 16)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TX49_CONF_IC (_ULCAST_(1) << 17)
#define TX49_CONF_IC (_ULCAST_(1) << 17)
#define TX49_CONF_HALT (_ULCAST_(1) << 18)
#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
#define MIPS_CONF_MT (_ULCAST_(7) << 7)
@ -512,27 +512,27 @@
#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define read_c0_info() __read_32bit_c0_register($7, 0)
#define read_c0_cache() __read_32bit_c0_register($7, 0)
#define read_c0_cache() __read_32bit_c0_register($7, 0)
#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
#define read_c0_count() __read_32bit_c0_register($9, 0)
#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
#define read_c0_count2() __read_32bit_c0_register($9, 6)
#define read_c0_count2() __read_32bit_c0_register($9, 6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
#define read_c0_count3() __read_32bit_c0_register($9, 7)
#define read_c0_count3() __read_32bit_c0_register($9, 7)
#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
#define read_c0_compare() __read_32bit_c0_register($11, 0)
#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
#define read_c0_compare2() __read_32bit_c0_register($11, 6)
#define read_c0_compare2() __read_32bit_c0_register($11, 6)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
#define read_c0_compare3() __read_32bit_c0_register($11, 7)
#define read_c0_compare3() __read_32bit_c0_register($11, 7)
#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
#define read_c0_status() __read_32bit_c0_register($12, 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

90
libc/kernel/arch-mips/asm/mman.h
View File

@ -18,62 +18,62 @@
****************************************************************************/
#ifndef _ASM_MMAN_H
#define _ASM_MMAN_H
#define PROT_NONE 0x00
#define PROT_READ 0x01
#define PROT_NONE 0x00
#define PROT_READ 0x01
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PROT_WRITE 0x02
#define PROT_EXEC 0x04
#define PROT_SEM 0x10
#define PROT_GROWSDOWN 0x01000000
#define PROT_WRITE 0x02
#define PROT_EXEC 0x04
#define PROT_SEM 0x10
#define PROT_GROWSDOWN 0x01000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PROT_GROWSUP 0x02000000
#define MAP_SHARED 0x001
#define MAP_PRIVATE 0x002
#define MAP_TYPE 0x00f
#define PROT_GROWSUP 0x02000000
#define MAP_SHARED 0x001
#define MAP_PRIVATE 0x002
#define MAP_TYPE 0x00f
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAP_FIXED 0x010
#define MAP_RENAME 0x020
#define MAP_AUTOGROW 0x040
#define MAP_LOCAL 0x080
#define MAP_FIXED 0x010
#define MAP_RENAME 0x020
#define MAP_AUTOGROW 0x040
#define MAP_LOCAL 0x080
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAP_AUTORSRV 0x100
#define MAP_NORESERVE 0x0400
#define MAP_ANONYMOUS 0x0800
#define MAP_GROWSDOWN 0x1000
#define MAP_AUTORSRV 0x100
#define MAP_NORESERVE 0x0400
#define MAP_ANONYMOUS 0x0800
#define MAP_GROWSDOWN 0x1000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAP_DENYWRITE 0x2000
#define MAP_EXECUTABLE 0x4000
#define MAP_LOCKED 0x8000
#define MAP_POPULATE 0x10000
#define MAP_DENYWRITE 0x2000
#define MAP_EXECUTABLE 0x4000
#define MAP_LOCKED 0x8000
#define MAP_POPULATE 0x10000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAP_NONBLOCK 0x20000
#define MAP_STACK 0x40000
#define MAP_HUGETLB 0x80000
#define MS_ASYNC 0x0001
#define MAP_NONBLOCK 0x20000
#define MAP_STACK 0x40000
#define MAP_HUGETLB 0x80000
#define MS_ASYNC 0x0001
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MS_INVALIDATE 0x0002
#define MS_SYNC 0x0004
#define MCL_CURRENT 1
#define MCL_FUTURE 2
#define MS_INVALIDATE 0x0002
#define MS_SYNC 0x0004
#define MCL_CURRENT 1
#define MCL_FUTURE 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MADV_NORMAL 0
#define MADV_RANDOM 1
#define MADV_SEQUENTIAL 2
#define MADV_WILLNEED 3
#define MADV_NORMAL 0
#define MADV_RANDOM 1
#define MADV_SEQUENTIAL 2
#define MADV_WILLNEED 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MADV_DONTNEED 4
#define MADV_REMOVE 9
#define MADV_DONTFORK 10
#define MADV_DOFORK 11
#define MADV_DONTNEED 4
#define MADV_REMOVE 9
#define MADV_DONTFORK 10
#define MADV_DOFORK 11
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MADV_MERGEABLE 12
#define MADV_UNMERGEABLE 13
#define MADV_HWPOISON 100
#define MADV_HUGEPAGE 14
#define MADV_MERGEABLE 12
#define MADV_UNMERGEABLE 13
#define MADV_HWPOISON 100
#define MADV_HUGEPAGE 14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MADV_NOHUGEPAGE 15
#define MADV_DONTDUMP 16
#define MADV_DODUMP 17
#define MADV_NOHUGEPAGE 15
#define MADV_DONTDUMP 16
#define MADV_DODUMP 17
#define MAP_FILE 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

132
libc/kernel/arch-mips/asm/pci/bridge.h
View File

@ -21,24 +21,24 @@
#include <linux/types.h>
#include <linux/pci.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm/xtalk/xwidget.h>
#include <asm/xtalk/xwidget.h>
#include <asm/sn/types.h>
#define IOPFNSHIFT 12
#define IOPFNSHIFT 12
#define IOPGSIZE (1 << IOPFNSHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOPG(x) ((x) >> IOPFNSHIFT)
#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
#define BRIDGE_ATE_RAM_SIZE 0x00000400
#define BRIDGE_ATE_RAM_SIZE 0x00000400
#define BRIDGE_CONFIG_BASE 0x20000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_CONFIG1_BASE 0x28000
#define BRIDGE_CONFIG_END 0x30000
#define BRIDGE_CONFIG_SLOT_SIZE 0x1000
#define BRIDGE_SSRAM_512K 0x00080000
#define BRIDGE_SSRAM_512K 0x00080000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_SSRAM_128K 0x00020000
#define BRIDGE_SSRAM_64K 0x00010000
#define BRIDGE_SSRAM_0K 0x00000000
#define BRIDGE_SSRAM_128K 0x00020000
#define BRIDGE_SSRAM_64K 0x00010000
#define BRIDGE_SSRAM_0K 0x00000000
#ifndef __ASSEMBLY__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef u32 bridgereg_t;
@ -138,8 +138,8 @@ typedef volatile struct bridge_s {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t reg;
} b_rrb_map[2];
#define b_even_resp b_rrb_map[0].reg
#define b_odd_resp b_rrb_map[1].reg
#define b_even_resp b_rrb_map[0].reg
#define b_odd_resp b_rrb_map[1].reg
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
bridgereg_t _pad_000290;
bridgereg_t b_resp_status;
@ -256,68 +256,68 @@ typedef struct bridge_err_cmdword_s {
#define BRIDGE_WID_LLP WIDGET_LLP_CFG
#define BRIDGE_WID_TFLUSH WIDGET_TFLUSH
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_WID_AUX_ERR 0x00005C
#define BRIDGE_WID_RESP_UPPER 0x000064
#define BRIDGE_WID_RESP_LOWER 0x00006C
#define BRIDGE_WID_TST_PIN_CTRL 0x000074
#define BRIDGE_WID_AUX_ERR 0x00005C
#define BRIDGE_WID_RESP_UPPER 0x000064
#define BRIDGE_WID_RESP_LOWER 0x00006C
#define BRIDGE_WID_TST_PIN_CTRL 0x000074
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DIR_MAP 0x000084
#define BRIDGE_RAM_PERR 0x000094
#define BRIDGE_ARB 0x0000A4
#define BRIDGE_NIC 0x0000B4
#define BRIDGE_DIR_MAP 0x000084
#define BRIDGE_RAM_PERR 0x000094
#define BRIDGE_ARB 0x0000A4
#define BRIDGE_NIC 0x0000B4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_BUS_TIMEOUT 0x0000C4
#define BRIDGE_BUS_TIMEOUT 0x0000C4
#define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT
#define BRIDGE_PCI_CFG 0x0000CC
#define BRIDGE_PCI_ERR_UPPER 0x0000D4
#define BRIDGE_PCI_CFG 0x0000CC
#define BRIDGE_PCI_ERR_UPPER 0x0000D4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_PCI_ERR_LOWER 0x0000DC
#define BRIDGE_INT_STATUS 0x000104
#define BRIDGE_INT_ENABLE 0x00010C
#define BRIDGE_INT_RST_STAT 0x000114
#define BRIDGE_PCI_ERR_LOWER 0x0000DC
#define BRIDGE_INT_STATUS 0x000104
#define BRIDGE_INT_ENABLE 0x00010C
#define BRIDGE_INT_RST_STAT 0x000114
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_INT_MODE 0x00011C
#define BRIDGE_INT_DEVICE 0x000124
#define BRIDGE_INT_HOST_ERR 0x00012C
#define BRIDGE_INT_ADDR0 0x000134
#define BRIDGE_INT_MODE 0x00011C
#define BRIDGE_INT_DEVICE 0x000124
#define BRIDGE_INT_HOST_ERR 0x00012C
#define BRIDGE_INT_ADDR0 0x000134
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_INT_ADDR_OFF 0x000008
#define BRIDGE_INT_ADDR_OFF 0x000008
#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
#define BRIDGE_DEVICE0 0x000204
#define BRIDGE_DEVICE_OFF 0x000008
#define BRIDGE_DEVICE0 0x000204
#define BRIDGE_DEVICE_OFF 0x000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
#define BRIDGE_WR_REQ_BUF0 0x000244
#define BRIDGE_WR_REQ_BUF_OFF 0x000008
#define BRIDGE_WR_REQ_BUF0 0x000244
#define BRIDGE_WR_REQ_BUF_OFF 0x000008
#define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_EVEN_RESP 0x000284
#define BRIDGE_ODD_RESP 0x00028C
#define BRIDGE_RESP_STATUS 0x000294
#define BRIDGE_RESP_CLEAR 0x00029C
#define BRIDGE_EVEN_RESP 0x000284
#define BRIDGE_ODD_RESP 0x00028C
#define BRIDGE_RESP_STATUS 0x000294
#define BRIDGE_RESP_CLEAR 0x00029C
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ATE_RAM 0x00010000
#define BRIDGE_TYPE0_CFG_DEV0 0x00020000
#define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000
#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100
#define BRIDGE_ATE_RAM 0x00010000
#define BRIDGE_TYPE0_CFG_DEV0 0x00020000
#define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000
#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
#define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+ (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+ (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
#define BRIDGE_TYPE1_CFG 0x00028000
#define BRIDGE_PCI_IACK 0x00030000
#define BRIDGE_TYPE1_CFG 0x00028000
#define BRIDGE_PCI_IACK 0x00030000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_EXT_SSRAM 0x00080000
#define BRIDGE_DEV_CNT 8
#define BRIDGE_DEVIO0 0x00200000
#define BRIDGE_DEVIO1 0x00400000
#define BRIDGE_EXT_SSRAM 0x00080000
#define BRIDGE_DEV_CNT 8
#define BRIDGE_DEVIO0 0x00200000
#define BRIDGE_DEVIO1 0x00400000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEVIO2 0x00600000
#define BRIDGE_DEVIO_OFF 0x00100000
#define BRIDGE_DEVIO_2MB 0x00200000
#define BRIDGE_DEVIO_1MB 0x00100000
#define BRIDGE_DEVIO2 0x00600000
#define BRIDGE_DEVIO_OFF 0x00100000
#define BRIDGE_DEVIO_2MB 0x00200000
#define BRIDGE_DEVIO_1MB 0x00100000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
#define BRIDGE_EXTERNAL_FLASH 0x00C00000
#define BRIDGE_EXTERNAL_FLASH 0x00C00000
#define BRIDGE_WIDGET_PART_NUM 0xc002
#define XBRIDGE_WIDGET_PART_NUM 0xd002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -384,7 +384,7 @@ typedef struct bridge_err_cmdword_s {
#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
#define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
#define BRIDGE_DIRMAP_OFF (0x1ffff << 0)
#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31)
#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16)
#define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3)
@ -544,9 +544,9 @@ typedef struct bridge_err_cmdword_s {
#define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_SWAP_PMU)
#define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | BRIDGE_DEV_SWAP_DIR | BRIDGE_DEV_PREF | BRIDGE_DEV_PRECISE | BRIDGE_DEV_COH | BRIDGE_DEV_BARRIER)
#define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | BRIDGE_DEV_SWAP_DIR | BRIDGE_DEV_COH | BRIDGE_DEV_BARRIER)
#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20)
#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19)
#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19)
#define BRIDGE_ERRUPPR_DEVNUM_SHFT (16)
#define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
#define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
@ -554,20 +554,20 @@ typedef struct bridge_err_cmdword_s {
#define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF)
#define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
#define BRIDGE_CREDIT 3
#define BRIDGE_RRB_EN 0x8
#define BRIDGE_RRB_EN 0x8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_RRB_DEV 0x7
#define BRIDGE_RRB_VDEV 0x4
#define BRIDGE_RRB_PDEV 0x3
#define BRIDGE_RRB_DEV 0x7
#define BRIDGE_RRB_VDEV 0x4
#define BRIDGE_RRB_PDEV 0x3
#define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r))
#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
#define XBOX_BRIDGE_WID 8
#define FLASH_PROM1_BASE 0xE00000
#define FLASH_PROM1_BASE 0xE00000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XBOX_RPS_EXISTS 1 << 6
#define XBOX_RPS_FAIL 1 << 4
#define XBOX_RPS_EXISTS 1 << 6
#define XBOX_RPS_FAIL 1 << 4
#define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L
#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -576,9 +576,9 @@ typedef struct bridge_err_cmdword_s {
#define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L
#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000
#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000
#define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff
#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000
#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000
#define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
@ -591,9 +591,9 @@ typedef struct bridge_err_cmdword_s {
#define BRIDGE_LOCAL_BASE 0
#define BRIDGE_DMA_MAPPED_BASE 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BRIDGE_DMA_MAPPED_SIZE 0x40000000
#define BRIDGE_DMA_MAPPED_SIZE 0x40000000
#define BRIDGE_DMA_DIRECT_BASE 0x80000000
#define BRIDGE_DMA_DIRECT_SIZE 0x80000000
#define BRIDGE_DMA_DIRECT_SIZE 0x80000000
#define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE

36
libc/kernel/arch-mips/asm/pgtable-bits.h
View File

@ -18,35 +18,35 @@
****************************************************************************/
#ifndef _ASM_PGTABLE_BITS_H
#define _ASM_PGTABLE_BITS_H
#define _PAGE_PRESENT (1<<0)
#define _PAGE_READ (1<<1)
#define _PAGE_PRESENT (1<<0)
#define _PAGE_READ (1<<1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _PAGE_WRITE (1<<2)
#define _PAGE_ACCESSED (1<<3)
#define _PAGE_MODIFIED (1<<4)
#define _PAGE_FILE (1<<4)
#define _PAGE_WRITE (1<<2)
#define _PAGE_ACCESSED (1<<3)
#define _PAGE_MODIFIED (1<<4)
#define _PAGE_FILE (1<<4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _PAGE_R4KBUG (1<<5)
#define _PAGE_R4KBUG (1<<5)
#define _PAGE_GLOBAL (1<<6)
#define _PAGE_VALID (1<<7)
#define _PAGE_SILENT_READ (1<<7)
#define _PAGE_SILENT_READ (1<<7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _PAGE_DIRTY (1<<8)
#define _PAGE_DIRTY (1<<8)
#define _PAGE_SILENT_WRITE (1<<8)
#define _CACHE_SHIFT 9
#define _CACHE_MASK (7<<9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
#define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT)
#define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)

2
libc/kernel/arch-mips/asm/ptrace.h
View File

@ -28,7 +28,7 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FPC_CSR 69
#define FPC_EIR 70
#define DSP_BASE 71
#define DSP_BASE 71
#define DSP_CONTROL 77
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ACX 78

60
libc/kernel/arch-mips/asm/regdef.h
View File

@ -21,17 +21,17 @@
#include <asm/sgidefs.h>
#if _MIPS_SIM == _MIPS_SIM_ABI32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define zero $0
#define AT $1
#define v0 $2
#define zero $0
#define AT $1
#define v0 $2
#define v1 $3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define a0 $4
#define a0 $4
#define a1 $5
#define a2 $6
#define a3 $7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define t0 $8
#define t0 $8
#define t1 $9
#define t2 $10
#define t3 $11
@ -41,7 +41,7 @@
#define t6 $14
#define t7 $15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define s0 $16
#define s0 $16
#define s1 $17
#define s2 $18
#define s3 $19
@ -51,32 +51,32 @@
#define s6 $22
#define s7 $23
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define t8 $24
#define t8 $24
#define t9 $25
#define jp $25
#define k0 $26
#define jp $25
#define k0 $26
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define k1 $27
#define gp $28
#define sp $29
#define fp $30
#define gp $28
#define sp $29
#define fp $30
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define s8 $30
#define ra $31
#define s8 $30
#define ra $31
#endif
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define zero $0
#define AT $at
#define v0 $2
#define zero $0
#define AT $at
#define v0 $2
#define v1 $3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define a0 $4
#define a0 $4
#define a1 $5
#define a2 $6
#define a3 $7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define a4 $8
#define a4 $8
#define ta0 $8
#define a5 $9
#define ta1 $9
@ -86,12 +86,12 @@
#define a7 $11
#define ta3 $11
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define t0 $12
#define t0 $12
#define t1 $13
#define t2 $14
#define t3 $15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define s0 $16
#define s0 $16
#define s1 $17
#define s2 $18
#define s3 $19
@ -101,18 +101,18 @@
#define s6 $22
#define s7 $23
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define t8 $24
#define t9 $25
#define jp $25
#define k0 $26
#define t8 $24
#define t9 $25
#define jp $25
#define k0 $26
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define k1 $27
#define gp $28
#define sp $29
#define fp $30
#define gp $28
#define sp $29
#define fp $30
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define s8 $30
#define ra $31
#define s8 $30
#define ra $31
#endif
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

10
libc/kernel/arch-mips/asm/resource.h
View File

@ -18,12 +18,12 @@
****************************************************************************/
#ifndef _ASM_RESOURCE_H
#define _ASM_RESOURCE_H
#define RLIMIT_NOFILE 5
#define RLIMIT_AS 6
#define RLIMIT_NOFILE 5
#define RLIMIT_AS 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RLIMIT_RSS 7
#define RLIMIT_NPROC 8
#define RLIMIT_MEMLOCK 9
#define RLIMIT_RSS 7
#define RLIMIT_NPROC 8
#define RLIMIT_MEMLOCK 9
#define RLIM_INFINITY 0x7fffffffUL
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <asm-generic/resource.h>

208
libc/kernel/arch-mips/asm/sgi/hpc3.h
View File

@ -24,19 +24,19 @@
struct hpc_dma_desc {
u32 pbuf;
u32 cntinfo;
#define HPCDMA_EOX 0x80000000
#define HPCDMA_EOX 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPCDMA_EOR 0x80000000
#define HPCDMA_EOXP 0x40000000
#define HPCDMA_EORP 0x40000000
#define HPCDMA_XIE 0x20000000
#define HPCDMA_EOR 0x80000000
#define HPCDMA_EOXP 0x40000000
#define HPCDMA_EORP 0x40000000
#define HPCDMA_XIE 0x20000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPCDMA_XIU 0x01000000
#define HPCDMA_EIPC 0x00ff0000
#define HPCDMA_ETXD 0x00008000
#define HPCDMA_OWN 0x00004000
#define HPCDMA_XIU 0x01000000
#define HPCDMA_EIPC 0x00ff0000
#define HPCDMA_ETXD 0x00008000
#define HPCDMA_OWN 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPCDMA_BCNT 0x00003fff
#define HPCDMA_BCNT 0x00003fff
u32 pnext;
};
struct hpc3_pbus_dmacregs {
@ -46,19 +46,19 @@ struct hpc3_pbus_dmacregs {
u32 _unused0[0x1000/4 - 2];
volatile u32 pbdma_ctrl;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_PDMACTRL_INT 0x00000001
#define HPC3_PDMACTRL_ISACT 0x00000002
#define HPC3_PDMACTRL_SEL 0x00000002
#define HPC3_PDMACTRL_RCV 0x00000004
#define HPC3_PDMACTRL_INT 0x00000001
#define HPC3_PDMACTRL_ISACT 0x00000002
#define HPC3_PDMACTRL_SEL 0x00000002
#define HPC3_PDMACTRL_RCV 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_PDMACTRL_FLSH 0x00000008
#define HPC3_PDMACTRL_ACT 0x00000010
#define HPC3_PDMACTRL_LD 0x00000020
#define HPC3_PDMACTRL_RT 0x00000040
#define HPC3_PDMACTRL_FLSH 0x00000008
#define HPC3_PDMACTRL_ACT 0x00000010
#define HPC3_PDMACTRL_LD 0x00000020
#define HPC3_PDMACTRL_RT 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_PDMACTRL_HW 0x0000ff00
#define HPC3_PDMACTRL_FB 0x003f0000
#define HPC3_PDMACTRL_FE 0x3f000000
#define HPC3_PDMACTRL_HW 0x0000ff00
#define HPC3_PDMACTRL_FB 0x003f0000
#define HPC3_PDMACTRL_FE 0x3f000000
u32 _unused1[0x1000/4 - 1];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
};
@ -68,48 +68,48 @@ struct hpc3_scsiregs {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 _unused0[0x1000/4 - 2];
volatile u32 bcd;
#define HPC3_SBCD_BCNTMSK 0x00003fff
#define HPC3_SBCD_XIE 0x00004000
#define HPC3_SBCD_BCNTMSK 0x00003fff
#define HPC3_SBCD_XIE 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_SBCD_EOX 0x00008000
#define HPC3_SBCD_EOX 0x00008000
volatile u32 ctrl;
#define HPC3_SCTRL_IRQ 0x01
#define HPC3_SCTRL_ENDIAN 0x02
#define HPC3_SCTRL_IRQ 0x01
#define HPC3_SCTRL_ENDIAN 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_SCTRL_DIR 0x04
#define HPC3_SCTRL_FLUSH 0x08
#define HPC3_SCTRL_ACTIVE 0x10
#define HPC3_SCTRL_AMASK 0x20
#define HPC3_SCTRL_DIR 0x04
#define HPC3_SCTRL_FLUSH 0x08
#define HPC3_SCTRL_ACTIVE 0x10
#define HPC3_SCTRL_AMASK 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_SCTRL_CRESET 0x40
#define HPC3_SCTRL_PERR 0x80
#define HPC3_SCTRL_CRESET 0x40
#define HPC3_SCTRL_PERR 0x80
volatile u32 gfptr;
volatile u32 dfptr;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile u32 dconfig;
#define HPC3_SDCFG_HCLK 0x00001
#define HPC3_SDCFG_D1 0x00006
#define HPC3_SDCFG_D2 0x00038
#define HPC3_SDCFG_HCLK 0x00001
#define HPC3_SDCFG_D1 0x00006
#define HPC3_SDCFG_D2 0x00038
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_SDCFG_D3 0x001c0
#define HPC3_SDCFG_HWAT 0x00e00
#define HPC3_SDCFG_HW 0x01000
#define HPC3_SDCFG_SWAP 0x02000
#define HPC3_SDCFG_D3 0x001c0
#define HPC3_SDCFG_HWAT 0x00e00
#define HPC3_SDCFG_HW 0x01000
#define HPC3_SDCFG_SWAP 0x02000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_SDCFG_EPAR 0x04000
#define HPC3_SDCFG_POLL 0x08000
#define HPC3_SDCFG_ERLY 0x30000
#define HPC3_SDCFG_EPAR 0x04000
#define HPC3_SDCFG_POLL 0x08000
#define HPC3_SDCFG_ERLY 0x30000
volatile u32 pconfig;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_SPCFG_P3 0x0003
#define HPC3_SPCFG_P2W 0x001c
#define HPC3_SPCFG_P2R 0x01e0
#define HPC3_SPCFG_P1 0x0e00
#define HPC3_SPCFG_P3 0x0003
#define HPC3_SPCFG_P2W 0x001c
#define HPC3_SPCFG_P2R 0x01e0
#define HPC3_SPCFG_P1 0x0e00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_SPCFG_HW 0x1000
#define HPC3_SPCFG_SWAP 0x2000
#define HPC3_SPCFG_EPAR 0x4000
#define HPC3_SPCFG_FUJI 0x8000
#define HPC3_SPCFG_HW 0x1000
#define HPC3_SPCFG_SWAP 0x2000
#define HPC3_SPCFG_EPAR 0x4000
#define HPC3_SPCFG_FUJI 0x8000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 _unused1[0x1000/4 - 6];
};
@ -119,46 +119,46 @@ struct hpc3_ethregs {
volatile u32 rx_ndptr;
u32 _unused0[0x1000/4 - 2];
volatile u32 rx_bcd;
#define HPC3_ERXBCD_BCNTMSK 0x00003fff
#define HPC3_ERXBCD_BCNTMSK 0x00003fff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_ERXBCD_XIE 0x20000000
#define HPC3_ERXBCD_EOX 0x80000000
#define HPC3_ERXBCD_XIE 0x20000000
#define HPC3_ERXBCD_EOX 0x80000000
volatile u32 rx_ctrl;
#define HPC3_ERXCTRL_STAT50 0x0000003f
#define HPC3_ERXCTRL_STAT50 0x0000003f
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_ERXCTRL_STAT6 0x00000040
#define HPC3_ERXCTRL_STAT7 0x00000080
#define HPC3_ERXCTRL_ENDIAN 0x00000100
#define HPC3_ERXCTRL_ACTIVE 0x00000200
#define HPC3_ERXCTRL_STAT6 0x00000040
#define HPC3_ERXCTRL_STAT7 0x00000080
#define HPC3_ERXCTRL_ENDIAN 0x00000100
#define HPC3_ERXCTRL_ACTIVE 0x00000200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_ERXCTRL_AMASK 0x00000400
#define HPC3_ERXCTRL_RBO 0x00000800
#define HPC3_ERXCTRL_AMASK 0x00000400
#define HPC3_ERXCTRL_RBO 0x00000800
volatile u32 rx_gfptr;
volatile u32 rx_dfptr;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 _unused1;
volatile u32 reset;
#define HPC3_ERST_CRESET 0x1
#define HPC3_ERST_CLRIRQ 0x2
#define HPC3_ERST_CRESET 0x1
#define HPC3_ERST_CLRIRQ 0x2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_ERST_LBACK 0x4
#define HPC3_ERST_LBACK 0x4
volatile u32 dconfig;
#define HPC3_EDCFG_D1 0x0000f
#define HPC3_EDCFG_D2 0x000f0
#define HPC3_EDCFG_D1 0x0000f
#define HPC3_EDCFG_D2 0x000f0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_EDCFG_D3 0x00f00
#define HPC3_EDCFG_WCTRL 0x01000
#define HPC3_EDCFG_FRXDC 0x02000
#define HPC3_EDCFG_FEOP 0x04000
#define HPC3_EDCFG_D3 0x00f00
#define HPC3_EDCFG_WCTRL 0x01000
#define HPC3_EDCFG_FRXDC 0x02000
#define HPC3_EDCFG_FEOP 0x04000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_EDCFG_FIRQ 0x08000
#define HPC3_EDCFG_PTO 0x30000
#define HPC3_EDCFG_FIRQ 0x08000
#define HPC3_EDCFG_PTO 0x30000
volatile u32 pconfig;
#define HPC3_EPCFG_P1 0x000f
#define HPC3_EPCFG_P1 0x000f
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_EPCFG_P2 0x00f0
#define HPC3_EPCFG_P3 0x0f00
#define HPC3_EPCFG_TST 0x1000
#define HPC3_EPCFG_P2 0x00f0
#define HPC3_EPCFG_P3 0x0f00
#define HPC3_EPCFG_TST 0x1000
u32 _unused2[0x1000/4 - 8];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile u32 tx_cbptr;
@ -166,20 +166,20 @@ struct hpc3_ethregs {
u32 _unused3[0x1000/4 - 2];
volatile u32 tx_bcd;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_ETXBCD_BCNTMSK 0x00003fff
#define HPC3_ETXBCD_ESAMP 0x10000000
#define HPC3_ETXBCD_XIE 0x20000000
#define HPC3_ETXBCD_EOP 0x40000000
#define HPC3_ETXBCD_BCNTMSK 0x00003fff
#define HPC3_ETXBCD_ESAMP 0x10000000
#define HPC3_ETXBCD_XIE 0x20000000
#define HPC3_ETXBCD_EOP 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_ETXBCD_EOX 0x80000000
#define HPC3_ETXBCD_EOX 0x80000000
volatile u32 tx_ctrl;
#define HPC3_ETXCTRL_STAT30 0x0000000f
#define HPC3_ETXCTRL_STAT4 0x00000010
#define HPC3_ETXCTRL_STAT30 0x0000000f
#define HPC3_ETXCTRL_STAT4 0x00000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_ETXCTRL_STAT75 0x000000e0
#define HPC3_ETXCTRL_ENDIAN 0x00000100
#define HPC3_ETXCTRL_ACTIVE 0x00000200
#define HPC3_ETXCTRL_AMASK 0x00000400
#define HPC3_ETXCTRL_STAT75 0x000000e0
#define HPC3_ETXCTRL_ENDIAN 0x00000100
#define HPC3_ETXCTRL_ACTIVE 0x00000200
#define HPC3_ETXCTRL_AMASK 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile u32 tx_gfptr;
volatile u32 tx_dfptr;
@ -193,28 +193,28 @@ struct hpc3_regs {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 _unused0[0x18000/4];
volatile u32 istat0;
#define HPC3_ISTAT_PBIMASK 0x0ff
#define HPC3_ISTAT_SC0MASK 0x100
#define HPC3_ISTAT_PBIMASK 0x0ff
#define HPC3_ISTAT_SC0MASK 0x100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_ISTAT_SC1MASK 0x200
#define HPC3_ISTAT_SC1MASK 0x200
volatile u32 gio_misc;
#define HPC3_GIOMISC_ERTIME 0x1
#define HPC3_GIOMISC_DENDIAN 0x2
#define HPC3_GIOMISC_ERTIME 0x1
#define HPC3_GIOMISC_DENDIAN 0x2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 eeprom;
#define HPC3_EEPROM_EPROT 0x01
#define HPC3_EEPROM_CSEL 0x02
#define HPC3_EEPROM_ECLK 0x04
#define HPC3_EEPROM_EPROT 0x01
#define HPC3_EEPROM_CSEL 0x02
#define HPC3_EEPROM_ECLK 0x04
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_EEPROM_DATO 0x08
#define HPC3_EEPROM_DATI 0x10
#define HPC3_EEPROM_DATO 0x08
#define HPC3_EEPROM_DATI 0x10
volatile u32 istat1;
volatile u32 bestat;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_BESTAT_BLMASK 0x000ff
#define HPC3_BESTAT_CTYPE 0x00100
#define HPC3_BESTAT_BLMASK 0x000ff
#define HPC3_BESTAT_CTYPE 0x00100
#define HPC3_BESTAT_PIDSHIFT 9
#define HPC3_BESTAT_PIDMASK 0x3f700
#define HPC3_BESTAT_PIDMASK 0x3f700
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 _unused1[0x14000/4 - 5];
volatile u32 scsi0_ext[256];
@ -269,22 +269,22 @@ struct hpc3_regs {
#define HPC3_PIOCFG_DS16 0x40000
#define HPC3_PIOCFG_EVENHI 0x80000
volatile u32 pbus_promwe;
#define HPC3_PROM_WENAB 0x1
#define HPC3_PROM_WENAB 0x1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 _unused5[0x0800/4 - 1];
volatile u32 pbus_promswap;
#define HPC3_PROM_SWAP 0x1
#define HPC3_PROM_SWAP 0x1
u32 _unused6[0x0800/4 - 1];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile u32 pbus_gout;
#define HPC3_PROM_STAT 0x1
#define HPC3_PROM_STAT 0x1
u32 _unused7[0x1000/4 - 1];
volatile u32 rtcregs[14];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u32 _unused8[50];
volatile u32 bbram[8192-50-14];
};
#define HPC3_CHIP0_BASE 0x1fb80000
#define HPC3_CHIP0_BASE 0x1fb80000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HPC3_CHIP1_BASE 0x1fb00000
#define HPC3_CHIP1_BASE 0x1fb00000
#endif

86
libc/kernel/arch-mips/asm/sgi/ioc.h
View File

@ -98,27 +98,27 @@ struct sgint_regs {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u8 _tcword[3];
volatile u8 tcword;
#define SGINT_TCWORD_BCD 0x01
#define SGINT_TCWORD_MMASK 0x0e
#define SGINT_TCWORD_BCD 0x01
#define SGINT_TCWORD_MMASK 0x0e
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGINT_TCWORD_MITC 0x00
#define SGINT_TCWORD_MOS 0x02
#define SGINT_TCWORD_MRGEN 0x04
#define SGINT_TCWORD_MSWGEN 0x06
#define SGINT_TCWORD_MITC 0x00
#define SGINT_TCWORD_MOS 0x02
#define SGINT_TCWORD_MRGEN 0x04
#define SGINT_TCWORD_MSWGEN 0x06
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGINT_TCWORD_MSWST 0x08
#define SGINT_TCWORD_MHWST 0x0a
#define SGINT_TCWORD_CMASK 0x30
#define SGINT_TCWORD_CLAT 0x00
#define SGINT_TCWORD_MSWST 0x08
#define SGINT_TCWORD_MHWST 0x0a
#define SGINT_TCWORD_CMASK 0x30
#define SGINT_TCWORD_CLAT 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGINT_TCWORD_CLSB 0x10
#define SGINT_TCWORD_CMSB 0x20
#define SGINT_TCWORD_CALL 0x30
#define SGINT_TCWORD_CNT0 0x00
#define SGINT_TCWORD_CLSB 0x10
#define SGINT_TCWORD_CMSB 0x20
#define SGINT_TCWORD_CALL 0x30
#define SGINT_TCWORD_CNT0 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGINT_TCWORD_CNT1 0x40
#define SGINT_TCWORD_CNT2 0x80
#define SGINT_TCWORD_CRBCK 0xc0
#define SGINT_TCWORD_CNT1 0x40
#define SGINT_TCWORD_CNT2 0x80
#define SGINT_TCWORD_CRBCK 0xc0
};
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGINT_TIMER_CLOCK 1000000
@ -159,52 +159,52 @@ struct sgioc_regs {
u32 _unused3;
u8 _dmasel[3];
volatile u8 dmasel;
#define SGIOC_DMASEL_SCLK10MHZ 0x00
#define SGIOC_DMASEL_SCLK10MHZ 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGIOC_DMASEL_ISDNB 0x01
#define SGIOC_DMASEL_ISDNA 0x02
#define SGIOC_DMASEL_PPORT 0x04
#define SGIOC_DMASEL_SCLK667MHZ 0x10
#define SGIOC_DMASEL_ISDNB 0x01
#define SGIOC_DMASEL_ISDNA 0x02
#define SGIOC_DMASEL_PPORT 0x04
#define SGIOC_DMASEL_SCLK667MHZ 0x10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGIOC_DMASEL_SCLKEXT 0x20
#define SGIOC_DMASEL_SCLKEXT 0x20
u32 _unused4;
u8 _reset[3];
volatile u8 reset;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGIOC_RESET_PPORT 0x01
#define SGIOC_RESET_KBDMOUSE 0x02
#define SGIOC_RESET_EISA 0x04
#define SGIOC_RESET_ISDN 0x08
#define SGIOC_RESET_PPORT 0x01
#define SGIOC_RESET_KBDMOUSE 0x02
#define SGIOC_RESET_EISA 0x04
#define SGIOC_RESET_ISDN 0x08
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGIOC_RESET_LC0OFF 0x10
#define SGIOC_RESET_LC1OFF 0x20
#define SGIOC_RESET_LC0OFF 0x10
#define SGIOC_RESET_LC1OFF 0x20
u32 _unused5;
u8 _write[3];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile u8 write;
#define SGIOC_WRITE_NTHRESH 0x01
#define SGIOC_WRITE_TPSPEED 0x02
#define SGIOC_WRITE_EPSEL 0x04
#define SGIOC_WRITE_NTHRESH 0x01
#define SGIOC_WRITE_TPSPEED 0x02
#define SGIOC_WRITE_EPSEL 0x04
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGIOC_WRITE_EASEL 0x08
#define SGIOC_WRITE_U1AMODE 0x10
#define SGIOC_WRITE_U0AMODE 0x20
#define SGIOC_WRITE_MLO 0x40
#define SGIOC_WRITE_EASEL 0x08
#define SGIOC_WRITE_U1AMODE 0x10
#define SGIOC_WRITE_U0AMODE 0x20
#define SGIOC_WRITE_MLO 0x40
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGIOC_WRITE_MHI 0x80
#define SGIOC_WRITE_MHI 0x80
u32 _unused6;
struct sgint_regs int3;
u32 _unused7[16];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile u32 extio;
#define EXTIO_S0_IRQ_3 0x8000
#define EXTIO_S0_IRQ_2 0x4000
#define EXTIO_S0_IRQ_1 0x2000
#define EXTIO_S0_IRQ_3 0x8000
#define EXTIO_S0_IRQ_2 0x4000
#define EXTIO_S0_IRQ_1 0x2000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EXTIO_S0_RETRACE 0x1000
#define EXTIO_SG_IRQ_3 0x0800
#define EXTIO_SG_IRQ_2 0x0400
#define EXTIO_SG_IRQ_1 0x0200
#define EXTIO_SG_IRQ_3 0x0800
#define EXTIO_SG_IRQ_2 0x0400
#define EXTIO_SG_IRQ_1 0x0200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EXTIO_SG_RETRACE 0x0100
#define EXTIO_GIO_33MHZ 0x0080

24
libc/kernel/arch-mips/asm/sgi/pi1.h
View File

@ -36,8 +36,8 @@ struct pi1_regs {
u8 _status[3];
volatile u8 status;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI1_STAT_DEVID 0x03
#define PI1_STAT_NOINK 0x04
#define PI1_STAT_DEVID 0x03
#define PI1_STAT_NOINK 0x04
#define PI1_STAT_ERROR 0x08
#define PI1_STAT_ONLINE 0x10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -47,18 +47,18 @@ struct pi1_regs {
u8 _dmactrl[3];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile u8 dmactrl;
#define PI1_DMACTRL_FIFO_EMPTY 0x01
#define PI1_DMACTRL_ABORT 0x02
#define PI1_DMACTRL_STDMODE 0x00
#define PI1_DMACTRL_FIFO_EMPTY 0x01
#define PI1_DMACTRL_ABORT 0x02
#define PI1_DMACTRL_STDMODE 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI1_DMACTRL_SGIMODE 0x04
#define PI1_DMACTRL_RICOHMODE 0x08
#define PI1_DMACTRL_HPMODE 0x0c
#define PI1_DMACTRL_BLKMODE 0x10
#define PI1_DMACTRL_SGIMODE 0x04
#define PI1_DMACTRL_RICOHMODE 0x08
#define PI1_DMACTRL_HPMODE 0x0c
#define PI1_DMACTRL_BLKMODE 0x10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI1_DMACTRL_FIFO_CLEAR 0x20
#define PI1_DMACTRL_READ 0x40
#define PI1_DMACTRL_RUN 0x80
#define PI1_DMACTRL_FIFO_CLEAR 0x20
#define PI1_DMACTRL_READ 0x40
#define PI1_DMACTRL_RUN 0x80
u8 _intstat[3];
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
volatile u8 intstat;

12
libc/kernel/arch-mips/asm/sgiarcs.h
View File

@ -291,13 +291,13 @@ struct linux_cdata {
#define SGIPROM_STDIN 0
#define SGIPROM_STDOUT 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGIPROM_ROFILE 0x01
#define SGIPROM_HFILE 0x02
#define SGIPROM_SFILE 0x04
#define SGIPROM_AFILE 0x08
#define SGIPROM_ROFILE 0x01
#define SGIPROM_HFILE 0x02
#define SGIPROM_SFILE 0x04
#define SGIPROM_AFILE 0x08
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SGIPROM_DFILE 0x10
#define SGIPROM_DELFILE 0x20
#define SGIPROM_DFILE 0x10
#define SGIPROM_DELFILE 0x20
struct sgi_partition {
unsigned char flag;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

2
libc/kernel/arch-mips/asm/shmparam.h
View File

@ -19,6 +19,6 @@
#ifndef _ASM_SHMPARAM_H
#define _ASM_SHMPARAM_H
#define __ARCH_FORCE_SHMLBA 1
#define SHMLBA 0x40000
#define SHMLBA 0x40000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

6
libc/kernel/arch-mips/asm/sibyte/bcm1480_int.h
View File

@ -244,7 +244,7 @@
#define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
#define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
#define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
#define K_BCM1480_INT_MAP_I0 0
#define K_BCM1480_INT_MAP_I0 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K_BCM1480_INT_MAP_I1 1
#define K_BCM1480_INT_MAP_I2 2
@ -252,8 +252,8 @@
#define K_BCM1480_INT_MAP_I4 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K_BCM1480_INT_MAP_I5 5
#define K_BCM1480_INT_MAP_NMI 6
#define K_BCM1480_INT_MAP_DINT 7
#define K_BCM1480_INT_MAP_NMI 6
#define K_BCM1480_INT_MAP_DINT 7
#define S_BCM1480_INT_HT_INTMSG 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG)

2
libc/kernel/arch-mips/asm/sibyte/bcm1480_scd.h
View File

@ -104,7 +104,7 @@
#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE)
#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE)
#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE)
#define K_BCM1480_SCD_WDOG_RESET_FULL 0
#define K_BCM1480_SCD_WDOG_RESET_FULL 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K_BCM1480_SCD_WDOG_RESET_SOFT 1
#define K_BCM1480_SCD_WDOG_RESET_CPU0 3

6
libc/kernel/arch-mips/asm/sibyte/sb1250_int.h
View File

@ -192,16 +192,16 @@
#define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#define K_INT_MAP_I0 0
#define K_INT_MAP_I0 0
#define K_INT_MAP_I1 1
#define K_INT_MAP_I2 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K_INT_MAP_I3 3
#define K_INT_MAP_I4 4
#define K_INT_MAP_I5 5
#define K_INT_MAP_NMI 6
#define K_INT_MAP_NMI 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K_INT_MAP_DINT 7
#define K_INT_MAP_DINT 7
#define S_INT_LDT_INTMSG 0
#define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG)
#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG)

18
libc/kernel/arch-mips/asm/sibyte/sb1250_scd.h
View File

@ -28,13 +28,13 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K_SYS_REVISION_BCM1250_PASS1 0x01
#define K_SYS_REVISION_BCM1250_PASS2 0x03
#define K_SYS_REVISION_BCM1250_A1 0x03
#define K_SYS_REVISION_BCM1250_A2 0x04
#define K_SYS_REVISION_BCM1250_A1 0x03
#define K_SYS_REVISION_BCM1250_A2 0x04
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K_SYS_REVISION_BCM1250_A3 0x05
#define K_SYS_REVISION_BCM1250_A4 0x06
#define K_SYS_REVISION_BCM1250_A6 0x07
#define K_SYS_REVISION_BCM1250_A8 0x0b
#define K_SYS_REVISION_BCM1250_A3 0x05
#define K_SYS_REVISION_BCM1250_A4 0x06
#define K_SYS_REVISION_BCM1250_A6 0x07
#define K_SYS_REVISION_BCM1250_A8 0x0b
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K_SYS_REVISION_BCM1250_A9 0x08
#define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8
@ -107,11 +107,11 @@
#define K_SYS_SOC_TYPE_BCM1250 0x0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K_SYS_SOC_TYPE_BCM1120 0x1
#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2
#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2
#define K_SYS_SOC_TYPE_BCM1125 0x3
#define K_SYS_SOC_TYPE_BCM1125H 0x4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5
#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5
#define K_SYS_SOC_TYPE_BCM1x80 0x6
#define K_SYS_SOC_TYPE_BCM1x55 0x7
#ifdef __ASSEMBLER__
@ -262,7 +262,7 @@
#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE)
#define K_SCD_WDOG_RESET_FULL 0
#define K_SCD_WDOG_RESET_FULL 0
#define K_SCD_WDOG_RESET_SOFT 1
#define K_SCD_WDOG_RESET_CPU0 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

8
libc/kernel/arch-mips/asm/siginfo.h
View File

@ -19,7 +19,7 @@
#ifndef _ASM_SIGINFO_H
#define _ASM_SIGINFO_H
#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int))
#undef __ARCH_SI_TRAPNO
#undef __ARCH_SI_TRAPNO
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HAVE_ARCH_SIGINFO_T
#define HAVE_ARCH_COPY_SIGINFO
@ -91,8 +91,8 @@ typedef struct siginfo {
#undef SI_TIMER
#undef SI_MESGQ
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SI_ASYNCIO -2
#define SI_TIMER __SI_CODE(__SI_TIMER, -3)
#define SI_MESGQ __SI_CODE(__SI_MESGQ, -4)
#define SI_ASYNCIO -2
#define SI_TIMER __SI_CODE(__SI_TIMER, -3)
#define SI_MESGQ __SI_CODE(__SI_MESGQ, -4)
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

72
libc/kernel/arch-mips/asm/signal.h
View File

@ -29,49 +29,49 @@ typedef struct {
unsigned long sig[_NSIG_WORDS];
} sigset_t;
typedef unsigned long old_sigset_t;
#define SIGHUP 1
#define SIGHUP 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIGINT 2
#define SIGQUIT 3
#define SIGILL 4
#define SIGTRAP 5
#define SIGINT 2
#define SIGQUIT 3
#define SIGILL 4
#define SIGTRAP 5
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIGIOT 6
#define SIGABRT SIGIOT
#define SIGIOT 6
#define SIGABRT SIGIOT
#define SIGEMT 7
#define SIGFPE 8
#define SIGFPE 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIGKILL 9
#define SIGBUS 10
#define SIGSEGV 11
#define SIGKILL 9
#define SIGBUS 10
#define SIGSEGV 11
#define SIGSYS 12
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIGPIPE 13
#define SIGALRM 14
#define SIGTERM 15
#define SIGUSR1 16
#define SIGPIPE 13
#define SIGALRM 14
#define SIGTERM 15
#define SIGUSR1 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIGUSR2 17
#define SIGCHLD 18
#define SIGCLD SIGCHLD
#define SIGPWR 19
#define SIGUSR2 17
#define SIGCHLD 18
#define SIGCLD SIGCHLD
#define SIGPWR 19
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIGWINCH 20
#define SIGURG 21
#define SIGIO 22
#define SIGPOLL SIGIO
#define SIGWINCH 20
#define SIGURG 21
#define SIGIO 22
#define SIGPOLL SIGIO
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIGSTOP 23
#define SIGTSTP 24
#define SIGCONT 25
#define SIGTTIN 26
#define SIGSTOP 23
#define SIGTSTP 24
#define SIGCONT 25
#define SIGTTIN 26
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIGTTOU 27
#define SIGVTALRM 28
#define SIGPROF 29
#define SIGXCPU 30
#define SIGTTOU 27
#define SIGVTALRM 28
#define SIGPROF 29
#define SIGXCPU 30
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIGXFSZ 31
#define SIGXFSZ 31
#define SIGRTMIN 32
#define SIGRTMAX _NSIG
#define SA_ONSTACK 0x08000000
@ -86,17 +86,17 @@ typedef unsigned long old_sigset_t;
#define SA_NOMASK SA_NODEFER
#define SA_ONESHOT SA_RESETHAND
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SA_RESTORER 0x04000000
#define SA_RESTORER 0x04000000
#define SS_ONSTACK 1
#define SS_DISABLE 2
#define MINSIGSTKSZ 2048
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIGSTKSZ 8192
struct siginfo;
#define SIG_BLOCK 1
#define SIG_UNBLOCK 2
#define SIG_BLOCK 1
#define SIG_UNBLOCK 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIG_SETMASK 3
#define SIG_SETMASK 3
#include <asm-generic/signal.h>
struct sigaction {
unsigned int sa_flags;

2
libc/kernel/arch-mips/asm/smp.h
View File

@ -31,7 +31,7 @@
#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
#define NO_PROC_ID (-1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SMP_RESCHEDULE_YOURSELF 0x1
#define SMP_RESCHEDULE_YOURSELF 0x1
#define SMP_CALL_FUNCTION 0x2
#define cpu_possible_map phys_cpu_present_map
#endif

6
libc/kernel/arch-mips/asm/sn/addrs.h
View File

@ -68,12 +68,12 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NODE_SWIN_ADDR(nasid, addr) (((addr) >= NODE_SWIN_BASE(nasid, 0)) && ((addr) < (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE) ))
#define UALIAS_BASE HSPEC_BASE
#define UALIAS_SIZE 0x10000000
#define UALIAS_SIZE 0x10000000
#define UALIAS_LIMIT (UALIAS_BASE + UALIAS_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define HUB_REGISTER_WIDGET 1
#define IALIAS_BASE NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
#define IALIAS_SIZE 0x800000
#define IALIAS_SIZE 0x800000
#define IS_IALIAS(_a) (((_a) >= IALIAS_BASE) && ((_a) < (IALIAS_BASE + IALIAS_SIZE)))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NODE_BDOOR_BASE(_n) (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
@ -116,7 +116,7 @@
#define KLDIR_ADDR(nasid) TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
#define KLDIR_SIZE 0x0400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KLI_LAUNCH 0
#define KLI_LAUNCH 0
#define KLI_KLCONFIG 1
#define KLI_NMI 2
#define KLI_GDA 3

10
libc/kernel/arch-mips/asm/sn/io.h
View File

@ -18,23 +18,23 @@
****************************************************************************/
#ifndef _ASM_SN_IO_H
#define _ASM_SN_IO_H
#define IIO_ITTE_BASE 0x400160
#define IIO_ITTE_BASE 0x400160
#define IIO_ITTE(bigwin) (IIO_ITTE_BASE + 8*(bigwin))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ITTE_OFFSET_BITS 5
#define IIO_ITTE_OFFSET_BITS 5
#define IIO_ITTE_OFFSET_MASK ((1<<IIO_ITTE_OFFSET_BITS)-1)
#define IIO_ITTE_OFFSET_SHIFT 0
#define IIO_ITTE_WIDGET_BITS 4
#define IIO_ITTE_WIDGET_BITS 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ITTE_WIDGET_MASK ((1<<IIO_ITTE_WIDGET_BITS)-1)
#define IIO_ITTE_WIDGET_SHIFT 8
#define IIO_ITTE_IOSP 1
#define IIO_ITTE_IOSP 1
#define IIO_ITTE_IOSP_MASK 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ITTE_IOSP_SHIFT 12
#define HUB_PIO_MAP_TO_MEM 0
#define HUB_PIO_MAP_TO_IO 1
#define IIO_ITTE_INVALID_WIDGET 3
#define IIO_ITTE_INVALID_WIDGET 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), (((((addr) >> BWIN_SIZE_BITS) & IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) | (io_or_mem << IIO_ITTE_IOSP_SHIFT) | (((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT)))
#define IIO_ITTE_DISABLE(nasid, bigwin) IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, (bigwin), IIO_ITTE_INVALID_WIDGET, 0)

402
libc/kernel/arch-mips/asm/sn/ioc3.h
View File

@ -193,21 +193,21 @@ struct ioc3_erxbuf {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ERXBUF_BYTECNT_SHIFT 16
#define ERXBUF_V 0x80000000
#define ERXBUF_CRCERR 0x00000001
#define ERXBUF_FRAMERR 0x00000002
#define ERXBUF_CRCERR 0x00000001
#define ERXBUF_FRAMERR 0x00000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ERXBUF_CODERR 0x00000004
#define ERXBUF_INVPREAMB 0x00000008
#define ERXBUF_LOLEN 0x00007000
#define ERXBUF_HILEN 0x03ff0000
#define ERXBUF_CODERR 0x00000004
#define ERXBUF_INVPREAMB 0x00000008
#define ERXBUF_LOLEN 0x00007000
#define ERXBUF_HILEN 0x03ff0000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ERXBUF_MULTICAST 0x04000000
#define ERXBUF_BROADCAST 0x08000000
#define ERXBUF_LONGEVENT 0x10000000
#define ERXBUF_BADPKT 0x20000000
#define ERXBUF_MULTICAST 0x04000000
#define ERXBUF_BROADCAST 0x08000000
#define ERXBUF_LONGEVENT 0x10000000
#define ERXBUF_BADPKT 0x20000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ERXBUF_GOODPKT 0x40000000
#define ERXBUF_CARRIER 0x80000000
#define ERXBUF_GOODPKT 0x40000000
#define ERXBUF_CARRIER 0x80000000
#define ETXD_DATALEN 104
struct ioc3_etxd {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -218,15 +218,15 @@ struct ioc3_etxd {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
u8 data[ETXD_DATALEN];
};
#define ETXD_BYTECNT_MASK 0x000007ff
#define ETXD_INTWHENDONE 0x00001000
#define ETXD_BYTECNT_MASK 0x000007ff
#define ETXD_INTWHENDONE 0x00001000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ETXD_D0V 0x00010000
#define ETXD_B1V 0x00020000
#define ETXD_B2V 0x00040000
#define ETXD_DOCHECKSUM 0x00080000
#define ETXD_D0V 0x00010000
#define ETXD_B1V 0x00020000
#define ETXD_B2V 0x00040000
#define ETXD_DOCHECKSUM 0x00080000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ETXD_CHKOFF_MASK 0x07f00000
#define ETXD_CHKOFF_MASK 0x07f00000
#define ETXD_CHKOFF_SHIFT 20
#define ETXD_D0CNT_MASK 0x0000007f
#define ETXD_B1CNT_MASK 0x0007ff00
@ -241,22 +241,22 @@ struct ioc3_etxd {
#define IOC3_BYTEBUS_DEV3 0xe0000L
#define IOC3_SIO_BASE 0x20000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141)
#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142)
#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE)
#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168)
#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141)
#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142)
#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE)
#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE)
#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE)
#define IOC3_SSRAM IOC3_RAM_OFF
#define IOC3_SSRAM_LEN 0x40000
#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE)
#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE)
#define IOC3_SSRAM IOC3_RAM_OFF
#define IOC3_SSRAM_LEN 0x40000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOC3_SSRAM_DM 0x0000ffff
#define IOC3_SSRAM_PM 0x00010000
#define PCI_SCR_PAR_RESP_EN 0x00000040
#define PCI_SCR_SERR_EN 0x00000100
#define IOC3_SSRAM_DM 0x0000ffff
#define IOC3_SSRAM_PM 0x00010000
#define PCI_SCR_PAR_RESP_EN 0x00000040
#define PCI_SCR_SERR_EN 0x00000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PCI_SCR_DROP_MODE_EN 0x00008000
#define PCI_SCR_DROP_MODE_EN 0x00008000
#define PCI_SCR_RX_SERR (0x1 << 16)
#define PCI_SCR_DROP_MODE (0x1 << 17)
#define PCI_SCR_SIG_PAR_ERR (0x1 << 24)
@ -267,158 +267,158 @@ struct ioc3_etxd {
#define PCI_SCR_SIG_SERR (0x1 << 30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PCI_SCR_PAR_ERR (0x1 << 31)
#define KM_CSR_K_WRT_PEND 0x00000001
#define KM_CSR_M_WRT_PEND 0x00000002
#define KM_CSR_K_LCB 0x00000004
#define KM_CSR_K_WRT_PEND 0x00000001
#define KM_CSR_M_WRT_PEND 0x00000002
#define KM_CSR_K_LCB 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KM_CSR_M_LCB 0x00000008
#define KM_CSR_K_DATA 0x00000010
#define KM_CSR_K_CLK 0x00000020
#define KM_CSR_K_PULL_DATA 0x00000040
#define KM_CSR_M_LCB 0x00000008
#define KM_CSR_K_DATA 0x00000010
#define KM_CSR_K_CLK 0x00000020
#define KM_CSR_K_PULL_DATA 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KM_CSR_K_PULL_CLK 0x00000080
#define KM_CSR_M_DATA 0x00000100
#define KM_CSR_M_CLK 0x00000200
#define KM_CSR_M_PULL_DATA 0x00000400
#define KM_CSR_K_PULL_CLK 0x00000080
#define KM_CSR_M_DATA 0x00000100
#define KM_CSR_M_CLK 0x00000200
#define KM_CSR_M_PULL_DATA 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KM_CSR_M_PULL_CLK 0x00000800
#define KM_CSR_EMM_MODE 0x00001000
#define KM_CSR_SIM_MODE 0x00002000
#define KM_CSR_K_SM_IDLE 0x00004000
#define KM_CSR_M_PULL_CLK 0x00000800
#define KM_CSR_EMM_MODE 0x00001000
#define KM_CSR_SIM_MODE 0x00002000
#define KM_CSR_K_SM_IDLE 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KM_CSR_M_SM_IDLE 0x00008000
#define KM_CSR_K_TO 0x00010000
#define KM_CSR_M_TO 0x00020000
#define KM_CSR_K_TO_EN 0x00040000
#define KM_CSR_M_SM_IDLE 0x00008000
#define KM_CSR_K_TO 0x00010000
#define KM_CSR_M_TO 0x00020000
#define KM_CSR_K_TO_EN 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KM_CSR_M_TO_EN 0x00080000
#define KM_CSR_K_CLAMP_ONE 0x00100000
#define KM_CSR_M_CLAMP_ONE 0x00200000
#define KM_CSR_K_CLAMP_THREE 0x00400000
#define KM_CSR_M_TO_EN 0x00080000
#define KM_CSR_K_CLAMP_ONE 0x00100000
#define KM_CSR_M_CLAMP_ONE 0x00200000
#define KM_CSR_K_CLAMP_THREE 0x00400000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KM_CSR_M_CLAMP_THREE 0x00800000
#define KM_RD_DATA_2 0x000000ff
#define KM_CSR_M_CLAMP_THREE 0x00800000
#define KM_RD_DATA_2 0x000000ff
#define KM_RD_DATA_2_SHIFT 0
#define KM_RD_DATA_1 0x0000ff00
#define KM_RD_DATA_1 0x0000ff00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KM_RD_DATA_1_SHIFT 8
#define KM_RD_DATA_0 0x00ff0000
#define KM_RD_DATA_0 0x00ff0000
#define KM_RD_DATA_0_SHIFT 16
#define KM_RD_FRAME_ERR_2 0x01000000
#define KM_RD_FRAME_ERR_2 0x01000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KM_RD_FRAME_ERR_1 0x02000000
#define KM_RD_FRAME_ERR_0 0x04000000
#define KM_RD_KBD_MSE 0x08000000
#define KM_RD_OFLO 0x10000000
#define KM_RD_FRAME_ERR_1 0x02000000
#define KM_RD_FRAME_ERR_0 0x04000000
#define KM_RD_KBD_MSE 0x08000000
#define KM_RD_OFLO 0x10000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KM_RD_VALID_2 0x20000000
#define KM_RD_VALID_1 0x40000000
#define KM_RD_VALID_0 0x80000000
#define KM_RD_VALID_2 0x20000000
#define KM_RD_VALID_1 0x40000000
#define KM_RD_VALID_0 0x80000000
#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KM_WD_WRT_DATA 0x000000ff
#define KM_WD_WRT_DATA 0x000000ff
#define KM_WD_WRT_DATA_SHIFT 0
#define RXSB_OVERRUN 0x01
#define RXSB_PAR_ERR 0x02
#define RXSB_OVERRUN 0x01
#define RXSB_PAR_ERR 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RXSB_FRAME_ERR 0x04
#define RXSB_BREAK 0x08
#define RXSB_CTS 0x10
#define RXSB_DCD 0x20
#define RXSB_FRAME_ERR 0x04
#define RXSB_BREAK 0x08
#define RXSB_CTS 0x10
#define RXSB_DCD 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RXSB_MODEM_VALID 0x40
#define RXSB_DATA_VALID 0x80
#define TXCB_INT_WHEN_DONE 0x20
#define TXCB_INVALID 0x00
#define RXSB_MODEM_VALID 0x40
#define RXSB_DATA_VALID 0x80
#define TXCB_INT_WHEN_DONE 0x20
#define TXCB_INVALID 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TXCB_VALID 0x40
#define TXCB_MCR 0x80
#define TXCB_DELAY 0xc0
#define SBBR_L_SIZE 0x00000001
#define TXCB_VALID 0x40
#define TXCB_MCR 0x80
#define TXCB_DELAY 0xc0
#define SBBR_L_SIZE 0x00000001
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SBBR_L_BASE 0xfffff000
#define SSCR_RX_THRESHOLD 0x000001ff
#define SSCR_TX_TIMER_BUSY 0x00010000
#define SSCR_HFC_EN 0x00020000
#define SBBR_L_BASE 0xfffff000
#define SSCR_RX_THRESHOLD 0x000001ff
#define SSCR_TX_TIMER_BUSY 0x00010000
#define SSCR_HFC_EN 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSCR_RX_RING_DCD 0x00040000
#define SSCR_RX_RING_CTS 0x00080000
#define SSCR_HIGH_SPD 0x00100000
#define SSCR_DIAG 0x00200000
#define SSCR_RX_RING_DCD 0x00040000
#define SSCR_RX_RING_CTS 0x00080000
#define SSCR_HIGH_SPD 0x00100000
#define SSCR_DIAG 0x00200000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSCR_RX_DRAIN 0x08000000
#define SSCR_DMA_EN 0x10000000
#define SSCR_DMA_PAUSE 0x20000000
#define SSCR_PAUSE_STATE 0x40000000
#define SSCR_RX_DRAIN 0x08000000
#define SSCR_DMA_EN 0x10000000
#define SSCR_DMA_PAUSE 0x20000000
#define SSCR_PAUSE_STATE 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SSCR_RESET 0x80000000
#define PROD_CONS_PTR_4K 0x00000ff8
#define PROD_CONS_PTR_1K 0x000003f8
#define SSCR_RESET 0x80000000
#define PROD_CONS_PTR_4K 0x00000ff8
#define PROD_CONS_PTR_1K 0x000003f8
#define PROD_CONS_PTR_OFF 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SRCIR_ARM 0x80000000
#define SRPIR_BYTE_CNT 0x07000000
#define SRCIR_ARM 0x80000000
#define SRPIR_BYTE_CNT 0x07000000
#define SRPIR_BYTE_CNT_SHIFT 24
#define STCIR_BYTE_CNT 0x0f000000
#define STCIR_BYTE_CNT 0x0f000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define STCIR_BYTE_CNT_SHIFT 24
#define SHADOW_DR 0x00000001
#define SHADOW_OE 0x00000002
#define SHADOW_PE 0x00000004
#define SHADOW_DR 0x00000001
#define SHADOW_OE 0x00000002
#define SHADOW_PE 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHADOW_FE 0x00000008
#define SHADOW_BI 0x00000010
#define SHADOW_THRE 0x00000020
#define SHADOW_TEMT 0x00000040
#define SHADOW_FE 0x00000008
#define SHADOW_BI 0x00000010
#define SHADOW_THRE 0x00000020
#define SHADOW_TEMT 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHADOW_RFCE 0x00000080
#define SHADOW_DCTS 0x00010000
#define SHADOW_DDCD 0x00080000
#define SHADOW_CTS 0x00100000
#define SHADOW_RFCE 0x00000080
#define SHADOW_DCTS 0x00010000
#define SHADOW_DDCD 0x00080000
#define SHADOW_CTS 0x00100000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHADOW_DCD 0x00800000
#define SHADOW_DTR 0x01000000
#define SHADOW_RTS 0x02000000
#define SHADOW_OUT1 0x04000000
#define SHADOW_DCD 0x00800000
#define SHADOW_DTR 0x01000000
#define SHADOW_RTS 0x02000000
#define SHADOW_OUT1 0x04000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SHADOW_OUT2 0x08000000
#define SHADOW_LOOP 0x10000000
#define SRTR_CNT 0x00000fff
#define SRTR_CNT_VAL 0x0fff0000
#define SHADOW_OUT2 0x08000000
#define SHADOW_LOOP 0x10000000
#define SRTR_CNT 0x00000fff
#define SRTR_CNT_VAL 0x0fff0000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SRTR_CNT_VAL_SHIFT 16
#define SRTR_HZ 16000
#define SIO_IR_SA_TX_MT 0x00000001
#define SIO_IR_SA_RX_FULL 0x00000002
#define SRTR_HZ 16000
#define SIO_IR_SA_TX_MT 0x00000001
#define SIO_IR_SA_RX_FULL 0x00000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_IR_SA_RX_HIGH 0x00000004
#define SIO_IR_SA_RX_TIMER 0x00000008
#define SIO_IR_SA_DELTA_DCD 0x00000010
#define SIO_IR_SA_DELTA_CTS 0x00000020
#define SIO_IR_SA_RX_HIGH 0x00000004
#define SIO_IR_SA_RX_TIMER 0x00000008
#define SIO_IR_SA_DELTA_DCD 0x00000010
#define SIO_IR_SA_DELTA_CTS 0x00000020
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_IR_SA_INT 0x00000040
#define SIO_IR_SA_TX_EXPLICIT 0x00000080
#define SIO_IR_SA_MEMERR 0x00000100
#define SIO_IR_SB_TX_MT 0x00000200
#define SIO_IR_SA_INT 0x00000040
#define SIO_IR_SA_TX_EXPLICIT 0x00000080
#define SIO_IR_SA_MEMERR 0x00000100
#define SIO_IR_SB_TX_MT 0x00000200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_IR_SB_RX_FULL 0x00000400
#define SIO_IR_SB_RX_HIGH 0x00000800
#define SIO_IR_SB_RX_TIMER 0x00001000
#define SIO_IR_SB_DELTA_DCD 0x00002000
#define SIO_IR_SB_RX_FULL 0x00000400
#define SIO_IR_SB_RX_HIGH 0x00000800
#define SIO_IR_SB_RX_TIMER 0x00001000
#define SIO_IR_SB_DELTA_DCD 0x00002000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_IR_SB_DELTA_CTS 0x00004000
#define SIO_IR_SB_INT 0x00008000
#define SIO_IR_SB_TX_EXPLICIT 0x00010000
#define SIO_IR_SB_MEMERR 0x00020000
#define SIO_IR_SB_DELTA_CTS 0x00004000
#define SIO_IR_SB_INT 0x00008000
#define SIO_IR_SB_TX_EXPLICIT 0x00010000
#define SIO_IR_SB_MEMERR 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_IR_PP_INT 0x00040000
#define SIO_IR_PP_INTA 0x00080000
#define SIO_IR_PP_INTB 0x00100000
#define SIO_IR_PP_MEMERR 0x00200000
#define SIO_IR_PP_INT 0x00040000
#define SIO_IR_PP_INTA 0x00080000
#define SIO_IR_PP_INTB 0x00100000
#define SIO_IR_PP_MEMERR 0x00200000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_IR_KBD_INT 0x00400000
#define SIO_IR_RT_INT 0x08000000
#define SIO_IR_GEN_INT1 0x10000000
#define SIO_IR_KBD_INT 0x00400000
#define SIO_IR_RT_INT 0x08000000
#define SIO_IR_GEN_INT1 0x10000000
#define SIO_IR_GEN_INT_SHIFT 28
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | SIO_IR_SA_MEMERR)
@ -427,61 +427,61 @@ struct ioc3_etxd {
#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & PCI_INW(&((mem)->sio_ies_ro)))
#define SIO_CR_SIO_RESET 0x00000001
#define SIO_CR_SER_A_BASE 0x000000fe
#define SIO_CR_SIO_RESET 0x00000001
#define SIO_CR_SER_A_BASE 0x000000fe
#define SIO_CR_SER_A_BASE_SHIFT 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_CR_SER_B_BASE 0x00007f00
#define SIO_CR_SER_B_BASE 0x00007f00
#define SIO_CR_SER_B_BASE_SHIFT 8
#define SIO_SR_CMD_PULSE 0x00078000
#define SIO_SR_CMD_PULSE 0x00078000
#define SIO_CR_CMD_PULSE_SHIFT 15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_CR_ARB_DIAG 0x00380000
#define SIO_CR_ARB_DIAG 0x00380000
#define SIO_CR_ARB_DIAG_TXA 0x00000000
#define SIO_CR_ARB_DIAG_RXA 0x00080000
#define SIO_CR_ARB_DIAG_TXB 0x00100000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIO_CR_ARB_DIAG_RXB 0x00180000
#define SIO_CR_ARB_DIAG_PP 0x00200000
#define SIO_CR_ARB_DIAG_IDLE 0x00400000
#define INT_OUT_COUNT 0x0000ffff
#define SIO_CR_ARB_DIAG_IDLE 0x00400000
#define INT_OUT_COUNT 0x0000ffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INT_OUT_MODE 0x00070000
#define INT_OUT_MODE_0 0x00000000
#define INT_OUT_MODE_1 0x00040000
#define INT_OUT_MODE_1PULSE 0x00050000
#define INT_OUT_MODE 0x00070000
#define INT_OUT_MODE_0 0x00000000
#define INT_OUT_MODE_1 0x00040000
#define INT_OUT_MODE_1PULSE 0x00050000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INT_OUT_MODE_PULSES 0x00060000
#define INT_OUT_MODE_SQW 0x00070000
#define INT_OUT_DIAG 0x40000000
#define INT_OUT_INT_OUT 0x80000000
#define INT_OUT_MODE_PULSES 0x00060000
#define INT_OUT_MODE_SQW 0x00070000
#define INT_OUT_DIAG 0x40000000
#define INT_OUT_INT_OUT 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INT_OUT_NS_PER_TICK (30 * 260)
#define INT_OUT_TICKS_PER_PULSE 3
#define INT_OUT_NS_PER_TICK (30 * 260)
#define INT_OUT_TICKS_PER_PULSE 3
#define INT_OUT_US_TO_COUNT(x) (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * 100 / INT_OUT_NS_PER_TICK - 1)
#define INT_OUT_COUNT_TO_US(x) (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define INT_OUT_MIN_TICKS 3
#define INT_OUT_MAX_TICKS INT_OUT_COUNT
#define GPCR_DIR 0x000000ff
#define GPCR_DIR_PIN(x) (1<<(x))
#define INT_OUT_MIN_TICKS 3
#define INT_OUT_MAX_TICKS INT_OUT_COUNT
#define GPCR_DIR 0x000000ff
#define GPCR_DIR_PIN(x) (1<<(x))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GPCR_EDGE 0x000f0000
#define GPCR_EDGE_PIN(x) (1<<((x)+15))
#define GPCR_INT_OUT_EN 0x00100000
#define GPCR_MLAN_EN 0x00200000
#define GPCR_EDGE 0x000f0000
#define GPCR_EDGE_PIN(x) (1<<((x)+15))
#define GPCR_INT_OUT_EN 0x00100000
#define GPCR_MLAN_EN 0x00200000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GPCR_DIR_SERA_XCVR 0x00000080
#define GPCR_DIR_SERB_XCVR 0x00000040
#define GPCR_DIR_PHY_RST 0x00000020
#define GPCR_PHY_RESET 0x20
#define GPCR_DIR_SERA_XCVR 0x00000080
#define GPCR_DIR_SERB_XCVR 0x00000040
#define GPCR_DIR_PHY_RST 0x00000020
#define GPCR_PHY_RESET 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GPCR_UARTB_MODESEL 0x40
#define GPCR_UARTA_MODESEL 0x80
#define GPPR_PHY_RESET_PIN 5
#define GPPR_UARTB_MODESEL_PIN 6
#define GPCR_UARTB_MODESEL 0x40
#define GPCR_UARTA_MODESEL 0x80
#define GPPR_PHY_RESET_PIN 5
#define GPPR_UARTB_MODESEL_PIN 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GPPR_UARTA_MODESEL_PIN 7
#define GPPR_UARTA_MODESEL_PIN 7
#define EMCR_DUPLEX 0x00000001
#define EMCR_PROMISC 0x00000002
#define EMCR_PADEN 0x00000004
@ -523,10 +523,10 @@ struct ioc3_etxd {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EISR_TXMEMERR 0x02000000
#define EISR_TXPARERR 0x04000000
#define ERCSR_THRESH_MASK 0x000001ff
#define ERCSR_RX_TMR 0x40000000
#define ERCSR_THRESH_MASK 0x000001ff
#define ERCSR_RX_TMR 0x40000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ERCSR_DIAG_OFLO 0x80000000
#define ERCSR_DIAG_OFLO 0x80000000
#define ERBR_ALIGNMENT 4096
#define ERBR_L_RXRINGBASE_MASK 0xfffff000
#define ERBAR_BARRIER_BIT 0x0100
@ -581,29 +581,29 @@ struct ioc3_etxd {
#define ERXBUF_BYTECNT_SHIFT 16
#define ERXBUF_V 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ERXBUF_CRCERR 0x00000001
#define ERXBUF_FRAMERR 0x00000002
#define ERXBUF_CODERR 0x00000004
#define ERXBUF_INVPREAMB 0x00000008
#define ERXBUF_CRCERR 0x00000001
#define ERXBUF_FRAMERR 0x00000002
#define ERXBUF_CODERR 0x00000004
#define ERXBUF_INVPREAMB 0x00000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ERXBUF_LOLEN 0x00007000
#define ERXBUF_HILEN 0x03ff0000
#define ERXBUF_MULTICAST 0x04000000
#define ERXBUF_BROADCAST 0x08000000
#define ERXBUF_LOLEN 0x00007000
#define ERXBUF_HILEN 0x03ff0000
#define ERXBUF_MULTICAST 0x04000000
#define ERXBUF_BROADCAST 0x08000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ERXBUF_LONGEVENT 0x10000000
#define ERXBUF_BADPKT 0x20000000
#define ERXBUF_GOODPKT 0x40000000
#define ERXBUF_CARRIER 0x80000000
#define ERXBUF_LONGEVENT 0x10000000
#define ERXBUF_BADPKT 0x20000000
#define ERXBUF_GOODPKT 0x40000000
#define ERXBUF_CARRIER 0x80000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ETXD_BYTECNT_MASK 0x000007ff
#define ETXD_INTWHENDONE 0x00001000
#define ETXD_D0V 0x00010000
#define ETXD_B1V 0x00020000
#define ETXD_BYTECNT_MASK 0x000007ff
#define ETXD_INTWHENDONE 0x00001000
#define ETXD_D0V 0x00010000
#define ETXD_B1V 0x00020000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ETXD_B2V 0x00040000
#define ETXD_DOCHECKSUM 0x00080000
#define ETXD_CHKOFF_MASK 0x07f00000
#define ETXD_B2V 0x00040000
#define ETXD_DOCHECKSUM 0x00080000
#define ETXD_CHKOFF_MASK 0x07f00000
#define ETXD_CHKOFF_SHIFT 20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ETXD_D0CNT_MASK 0x0000007f

16
libc/kernel/arch-mips/asm/sn/sn0/addrs.h
View File

@ -119,15 +119,15 @@
#define IO6DPROM_SIZE 0x200000
#define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000)
#define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000)
#define IP27PROM_INT_LAUNCH 10
#define IP27PROM_INT_LAUNCH 10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IP27PROM_INT_NETUART 12
#define IP27PROM_INT_NETUART 12
#endif
#define IP27PROM_ELSC_SHFT 10
#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define FREEMEM_BASE PHYS_TO_K0(0x2000000)
#define IO6PROM_STACK_SHFT 14
#define IO6PROM_STACK_SHFT 14
#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT)
#define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -142,11 +142,11 @@
#define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048)
#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0)
#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0)
#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1)
#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0)
#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0)
#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define KL_I2C_REG MD_UREG0_0
#define KL_I2C_REG MD_UREG0_0
#ifndef __ASSEMBLY__
#ifdef HUB_ERR_STS_WAR
#define CACHE_ERR_EFRAME 0x480
@ -156,7 +156,7 @@
#endif
#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CACHE_ERR_SP_PTR (0x1000 - 32)
#define CACHE_ERR_SP_PTR (0x1000 - 32)
#define CACHE_ERR_IBASE_PTR (0x1000 - 40)
#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16)
#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)

308
libc/kernel/arch-mips/asm/sn/sn0/hubio.h
View File

@ -18,41 +18,41 @@
****************************************************************************/
#ifndef _ASM_SGI_SN_SN0_HUBIO_H
#define _ASM_SGI_SN_SN0_HUBIO_H
#define IIO_WIDGET IIO_WID
#define IIO_WIDGET_STAT IIO_WSTAT
#define IIO_WIDGET IIO_WID
#define IIO_WIDGET_STAT IIO_WSTAT
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_WIDGET_CTRL IIO_WCR
#define IIO_WIDGET_TOUT IIO_WRTO
#define IIO_WIDGET_FLUSH IIO_WTFR
#define IIO_PROTECT IIO_ILAPR
#define IIO_WIDGET_CTRL IIO_WCR
#define IIO_WIDGET_TOUT IIO_WRTO
#define IIO_WIDGET_FLUSH IIO_WTFR
#define IIO_PROTECT IIO_ILAPR
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_PROTECT_OVRRD IIO_ILAPO
#define IIO_OUTWIDGET_ACCESS IIO_IOWA
#define IIO_INWIDGET_ACCESS IIO_IIWA
#define IIO_INDEV_ERR_MASK IIO_IIDEM
#define IIO_PROTECT_OVRRD IIO_ILAPO
#define IIO_OUTWIDGET_ACCESS IIO_IOWA
#define IIO_INWIDGET_ACCESS IIO_IIWA
#define IIO_INDEV_ERR_MASK IIO_IIDEM
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_LLP_CSR IIO_ILCSR
#define IIO_LLP_LOG IIO_ILLR
#define IIO_XTALKCC_TOUT IIO_IXCC
#define IIO_XTALKTT_TOUT IIO_IXTT
#define IIO_LLP_CSR IIO_ILCSR
#define IIO_LLP_LOG IIO_ILLR
#define IIO_XTALKCC_TOUT IIO_IXCC
#define IIO_XTALKTT_TOUT IIO_IXTT
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IO_ERR_CLR IIO_IECLR
#define IIO_BTE_CRB_CNT IIO_IBCN
#define IIO_IO_ERR_CLR IIO_IECLR
#define IIO_BTE_CRB_CNT IIO_IBCN
#define IIO_LLP_CSR_IS_UP 0x00002000
#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_LLP_CSR_LLP_STAT_SHFT 12
#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull
#define IIO_BTE_STAT_0 IIO_IBLS_0
#define IIO_BTE_SRC_0 IIO_IBSA_0
#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull
#define IIO_BTE_STAT_0 IIO_IBLS_0
#define IIO_BTE_SRC_0 IIO_IBSA_0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_BTE_DEST_0 IIO_IBDA_0
#define IIO_BTE_CTRL_0 IIO_IBCT_0
#define IIO_BTE_NOTIFY_0 IIO_IBNA_0
#define IIO_BTE_INT_0 IIO_IBIA_0
#define IIO_BTE_DEST_0 IIO_IBDA_0
#define IIO_BTE_CTRL_0 IIO_IBCT_0
#define IIO_BTE_NOTIFY_0 IIO_IBNA_0
#define IIO_BTE_INT_0 IIO_IBIA_0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_BTE_OFF_0 0
#define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0
#define IIO_BTE_OFF_0 0
#define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0
#define BTEOFF_STAT 0
#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -68,27 +68,27 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_PERF_CNT 0x430008
#define IO_PERF_SETS 32
#define IIO_WID 0x400000
#define IIO_WSTAT 0x400008
#define IIO_WID 0x400000
#define IIO_WSTAT 0x400008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_WCR 0x400020
#define IIO_WSTAT_ECRAZY (1ULL << 32)
#define IIO_WSTAT_TXRETRY (1ULL << 9)
#define IIO_WCR 0x400020
#define IIO_WSTAT_ECRAZY (1ULL << 32)
#define IIO_WSTAT_TXRETRY (1ULL << 9)
#define IIO_WSTAT_TXRETRY_MASK (0x7F)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_WSTAT_TXRETRY_SHFT (16)
#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & IIO_WSTAT_TXRETRY_MASK)
#define IIO_ILAPR 0x400100
#define IIO_ILAPO 0x400108
#define IIO_ILAPR 0x400100
#define IIO_ILAPO 0x400108
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IOWA 0x400110
#define IIO_IIWA 0x400118
#define IIO_IIDEM 0x400120
#define IIO_ILCSR 0x400128
#define IIO_IOWA 0x400110
#define IIO_IIWA 0x400118
#define IIO_IIDEM 0x400120
#define IIO_ILCSR 0x400128
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ILLR 0x400130
#define IIO_IIDSR 0x400138
#define IIO_IIBUSERR 0x1400208
#define IIO_ILLR 0x400130
#define IIO_IIDSR 0x400138
#define IIO_IIBUSERR 0x1400208
#define IIO_IIDSR_SENT_SHIFT 28
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IIDSR_SENT_MASK 0x10000000
@ -99,21 +99,21 @@
#define IIO_IIDSR_NODE_MASK 0x0000ff00
#define IIO_IIDSR_LVL_SHIFT 0
#define IIO_IIDSR_LVL_MASK 0x0000003f
#define IIO_IGFX_0 0x400140
#define IIO_IGFX_0 0x400140
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IGFX_1 0x400148
#define IIO_IGFX_W_NUM_BITS 4
#define IIO_IGFX_1 0x400148
#define IIO_IGFX_W_NUM_BITS 4
#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
#define IIO_IGFX_W_NUM_SHIFT 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IGFX_N_NUM_BITS 9
#define IIO_IGFX_N_NUM_BITS 9
#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
#define IIO_IGFX_N_NUM_SHIFT 4
#define IIO_IGFX_P_NUM_BITS 1
#define IIO_IGFX_P_NUM_BITS 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
#define IIO_IGFX_P_NUM_SHIFT 16
#define IIO_IGFX_VLD_BITS 1
#define IIO_IGFX_VLD_BITS 1
#define IIO_IGFX_VLD_MASK ((1<<IIO_IGFX_VLD_BITS)-1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IGFX_VLD_SHIFT 20
@ -136,7 +136,7 @@
#define IIO_SCRATCH_BIT0_9 0x0000000000001000
#define IIO_SCRATCH_BIT0_R 0x0000000000000fff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_NUM_ITTES 7
#define IIO_NUM_ITTES 7
#define HUB_NUM_BIG_WINDOW IIO_NUM_ITTES - 1
#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
#define ILCSR_WARM_RESET 0x100
@ -272,46 +272,46 @@ typedef union io_perf_cnt {
#define IIO_LLP_SN_MAX 0xffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_NUM_IPRBS (9)
#define IIO_IOPRB_0 0x400198
#define IIO_IOPRB_8 0x4001a0
#define IIO_IOPRB_9 0x4001a8
#define IIO_IOPRB_0 0x400198
#define IIO_IOPRB_8 0x4001a0
#define IIO_IOPRB_9 0x4001a8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IOPRB_A 0x4001b0
#define IIO_IOPRB_B 0x4001b8
#define IIO_IOPRB_C 0x4001c0
#define IIO_IOPRB_D 0x4001c8
#define IIO_IOPRB_A 0x4001b0
#define IIO_IOPRB_B 0x4001b8
#define IIO_IOPRB_C 0x4001c0
#define IIO_IOPRB_D 0x4001c8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IOPRB_E 0x4001d0
#define IIO_IOPRB_F 0x4001d8
#define IIO_IXCC 0x4001e0
#define IIO_IOPRB_E 0x4001d0
#define IIO_IOPRB_F 0x4001d8
#define IIO_IXCC 0x4001e0
#define IIO_IXTCC IIO_IXCC
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IMEM 0x4001e8
#define IIO_IXTT 0x4001f0
#define IIO_IECLR 0x4001f8
#define IIO_IBCN 0x400200
#define IIO_IMEM 0x4001e8
#define IIO_IXTT 0x4001f0
#define IIO_IECLR 0x4001f8
#define IIO_IBCN 0x400200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IMEM_W0ESD 0x1
#define IIO_IMEM_B0ESD (1 << 4)
#define IIO_IMEM_B1ESD (1 << 8)
#define IIO_IPCA 0x400300
#define IIO_IMEM_W0ESD 0x1
#define IIO_IMEM_B0ESD (1 << 4)
#define IIO_IMEM_B1ESD (1 << 8)
#define IIO_IPCA 0x400300
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_NUM_PRTES 8
#define IIO_PRTE_0 0x400308
#define IIO_NUM_PRTES 8
#define IIO_PRTE_0 0x400308
#define IIO_PRTE(_x) (IIO_PRTE_0 + (8 * (_x)))
#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8))
#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IPDR 0x400388
#define IIO_ICDR 0x400390
#define IIO_IFDR 0x400398
#define IIO_IIAP 0x4003a0
#define IIO_IPDR 0x400388
#define IIO_ICDR 0x400390
#define IIO_IFDR 0x400398
#define IIO_IIAP 0x4003a0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IMMR IIO_IIAP
#define IIO_ICMR 0x4003a8
#define IIO_ICCR 0x4003b0
#define IIO_ICTO 0x4003b8
#define IIO_ICMR 0x4003a8
#define IIO_ICCR 0x4003b0
#define IIO_ICTO 0x4003b8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICTP 0x4003c0
#define IIO_ICTP 0x4003c0
#define IIO_ICMR_PC_VLD_SHFT 36
#define IIO_ICMR_PC_VLD_MASK (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
#define IIO_ICMR_CRB_VLD_SHFT 20
@ -334,16 +334,16 @@ typedef union io_perf_cnt {
#define IIO_ICCR_PENDING (0x10000)
#define IIO_ICCR_CMD_MASK (0xFF)
#define IIO_ICCR_CMD_SHFT (7)
#define IIO_ICCR_CMD_NOP (0x0)
#define IIO_ICCR_CMD_NOP (0x0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICCR_CMD_WAKE (0x100)
#define IIO_ICCR_CMD_TIMEOUT (0x200)
#define IIO_ICCR_CMD_EJECT (0x400)
#define IIO_ICCR_CMD_WAKE (0x100)
#define IIO_ICCR_CMD_TIMEOUT (0x200)
#define IIO_ICCR_CMD_EJECT (0x400)
#define IIO_ICCR_CMD_FLUSH (0x800)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_NUM_CRBS 15
#define IIO_NUM_NORMAL_CRBS 12
#define IIO_NUM_PC_CRBS 4
#define IIO_NUM_CRBS 15
#define IIO_NUM_NORMAL_CRBS 12
#define IIO_NUM_PC_CRBS 4
#define IIO_ICRB_OFFSET 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_0 0x400400
@ -401,17 +401,17 @@ typedef union h1_icrba_u {
#define ICRBN_A_ERR_MASK 0x3ff
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_ADDR_SHFT 2
#define IIO_ICRB_ECODE_DERR 0
#define IIO_ICRB_ECODE_PERR 1
#define IIO_ICRB_ECODE_WERR 2
#define IIO_ICRB_ADDR_SHFT 2
#define IIO_ICRB_ECODE_DERR 0
#define IIO_ICRB_ECODE_PERR 1
#define IIO_ICRB_ECODE_WERR 2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_ECODE_AERR 3
#define IIO_ICRB_ECODE_PWERR 4
#define IIO_ICRB_ECODE_PRERR 5
#define IIO_ICRB_ECODE_TOUT 6
#define IIO_ICRB_ECODE_AERR 3
#define IIO_ICRB_ECODE_PWERR 4
#define IIO_ICRB_ECODE_PRERR 5
#define IIO_ICRB_ECODE_TOUT 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_ECODE_XTERR 7
#define IIO_ICRB_ECODE_XTERR 7
#ifndef __ASSEMBLY__
typedef union icrbb_u {
u64 reg_value;
@ -496,44 +496,44 @@ typedef union h1_icrbb_u {
#define b_initiator icrbb_field_s.initiator
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_XTSIZE_DW 0
#define IIO_ICRB_XTSIZE_32 1
#define IIO_ICRB_XTSIZE_128 2
#define IIO_ICRB_PROC0 0
#define IIO_ICRB_XTSIZE_DW 0
#define IIO_ICRB_XTSIZE_32 1
#define IIO_ICRB_XTSIZE_128 2
#define IIO_ICRB_PROC0 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_PROC1 1
#define IIO_ICRB_GB_REQ 2
#define IIO_ICRB_IO_REQ 3
#define IIO_ICRB_IMSGT_XTALK 0
#define IIO_ICRB_PROC1 1
#define IIO_ICRB_GB_REQ 2
#define IIO_ICRB_IO_REQ 3
#define IIO_ICRB_IMSGT_XTALK 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_IMSGT_BTE 1
#define IIO_ICRB_IMSGT_SN0NET 2
#define IIO_ICRB_IMSGT_CRB 3
#define IIO_ICRB_INIT_XTALK 0
#define IIO_ICRB_IMSGT_BTE 1
#define IIO_ICRB_IMSGT_SN0NET 2
#define IIO_ICRB_IMSGT_CRB 3
#define IIO_ICRB_INIT_XTALK 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_INIT_BTE0 0x1
#define IIO_ICRB_INIT_SN0NET 0x2
#define IIO_ICRB_INIT_CRB 0x3
#define IIO_ICRB_INIT_BTE1 0x5
#define IIO_ICRB_INIT_BTE0 0x1
#define IIO_ICRB_INIT_SN0NET 0x2
#define IIO_ICRB_INIT_CRB 0x3
#define IIO_ICRB_INIT_BTE1 0x5
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_REQ_DWRD 0
#define IIO_ICRB_REQ_QCLRD 1
#define IIO_ICRB_REQ_BLKRD 2
#define IIO_ICRB_REQ_RSHU 6
#define IIO_ICRB_REQ_DWRD 0
#define IIO_ICRB_REQ_QCLRD 1
#define IIO_ICRB_REQ_BLKRD 2
#define IIO_ICRB_REQ_RSHU 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_REQ_REXU 7
#define IIO_ICRB_REQ_RDEX 8
#define IIO_ICRB_REQ_WINC 9
#define IIO_ICRB_REQ_BWINV 10
#define IIO_ICRB_REQ_REXU 7
#define IIO_ICRB_REQ_RDEX 8
#define IIO_ICRB_REQ_WINC 9
#define IIO_ICRB_REQ_BWINV 10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_REQ_PIORD 11
#define IIO_ICRB_REQ_PIOWR 12
#define IIO_ICRB_REQ_PRDM 13
#define IIO_ICRB_REQ_PWRM 14
#define IIO_ICRB_REQ_PIORD 11
#define IIO_ICRB_REQ_PIOWR 12
#define IIO_ICRB_REQ_PRDM 13
#define IIO_ICRB_REQ_PWRM 14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_ICRB_REQ_PTPWR 15
#define IIO_ICRB_REQ_WB 16
#define IIO_ICRB_REQ_DEX 17
#define IIO_ICRB_REQ_PTPWR 15
#define IIO_ICRB_REQ_WB 16
#define IIO_ICRB_REQ_DEX 17
#ifndef __ASSEMBLY__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef union icrbc_s {
@ -558,8 +558,8 @@ typedef union icrbc_s {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define c_pripsc icrbc_field_s.pripsc
#define c_bteop icrbc_field_s.bteop
#define c_bteaddr icrbc_field_s.push_be
#define c_benable icrbc_field_s.push_be
#define c_bteaddr icrbc_field_s.push_be
#define c_benable icrbc_field_s.push_be
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define c_suppl icrbc_field_s.suppl
#define c_barrop icrbc_field_s.barrop
@ -598,41 +598,41 @@ typedef union hubii_ifdr_u {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
} hubii_ifdr_t;
#endif
#define IIO_IBLS_0 0x410000
#define IIO_IBSA_0 0x410008
#define IIO_IBLS_0 0x410000
#define IIO_IBSA_0 0x410008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IBDA_0 0x410010
#define IIO_IBCT_0 0x410018
#define IIO_IBNA_0 0x410020
#define IIO_IBDA_0 0x410010
#define IIO_IBCT_0 0x410018
#define IIO_IBNA_0 0x410020
#define IIO_IBNR_0 IIO_IBNA_0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IBIA_0 0x410028
#define IIO_IBLS_1 0x420000
#define IIO_IBSA_1 0x420008
#define IIO_IBDA_1 0x420010
#define IIO_IBIA_0 0x410028
#define IIO_IBLS_1 0x420000
#define IIO_IBSA_1 0x420008
#define IIO_IBDA_1 0x420010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IBCT_1 0x420018
#define IIO_IBNA_1 0x420020
#define IIO_IBCT_1 0x420018
#define IIO_IBNA_1 0x420020
#define IIO_IBNR_1 IIO_IBNA_1
#define IIO_IBIA_1 0x420028
#define IIO_IBIA_1 0x420028
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_IPCR 0x430000
#define IIO_IPPR 0x430008
#define IECLR_BTE1 (1 << 18)
#define IECLR_BTE0 (1 << 17)
#define IIO_IPCR 0x430000
#define IIO_IPPR 0x430008
#define IECLR_BTE1 (1 << 18)
#define IECLR_BTE0 (1 << 17)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IECLR_CRAZY (1 << 16)
#define IECLR_PRB_F (1 << 15)
#define IECLR_PRB_E (1 << 14)
#define IECLR_PRB_D (1 << 13)
#define IECLR_CRAZY (1 << 16)
#define IECLR_PRB_F (1 << 15)
#define IECLR_PRB_E (1 << 14)
#define IECLR_PRB_D (1 << 13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IECLR_PRB_C (1 << 12)
#define IECLR_PRB_B (1 << 11)
#define IECLR_PRB_A (1 << 10)
#define IECLR_PRB_9 (1 << 9)
#define IECLR_PRB_C (1 << 12)
#define IECLR_PRB_B (1 << 11)
#define IECLR_PRB_A (1 << 10)
#define IECLR_PRB_9 (1 << 9)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IECLR_PRB_8 (1 << 8)
#define IECLR_PRB_0 (1 << 0)
#define IECLR_PRB_8 (1 << 8)
#define IECLR_PRB_0 (1 << 0)
#ifndef __ASSEMBLY__
typedef union iprte_a {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -692,9 +692,9 @@ typedef union iprb_u {
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IPRB_MODE_NORMAL (0)
#define IPRB_MODE_COLLECT_A (1)
#define IPRB_MODE_SERVICE_A (2)
#define IPRB_MODE_SERVICE_B (3)
#define IPRB_MODE_COLLECT_A (1)
#define IPRB_MODE_SERVICE_A (2)
#define IPRB_MODE_SERVICE_B (3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef __ASSEMBLY__
typedef union icrbp_a {
@ -781,7 +781,7 @@ typedef union hubii_idsr {
#define MAX_HUBS_PER_XBOW 2
#define IIO_WCR_WID_GET(nasid) (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IIO_WST_ERROR_MASK (UINT64_CAST 1 << 32)
#define IIO_WST_ERROR_MASK (UINT64_CAST 1 << 32)
#define HUBII_XBOW_CREDIT 3
#define HUBII_XBOW_REV2_CREDIT 4
#endif

224
libc/kernel/arch-mips/asm/sn/sn0/hubmd.h
View File

@ -18,106 +18,106 @@
****************************************************************************/
#ifndef _ASM_SN_SN0_HUBMD_H
#define _ASM_SN_SN0_HUBMD_H
#define CACHE_SLINE_SIZE 128
#define CACHE_SLINE_SIZE 128
#define MAX_REGIONS 64
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PAGE_SIZE 4096
#define MD_PAGE_NUM_SHFT 12
#define MD_PAGE_SIZE 4096
#define MD_PAGE_NUM_SHFT 12
#define MD_BASE 0x200000
#define MD_BASE_PERF 0x210000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_BASE_JUNK 0x220000
#define MD_IO_PROTECT 0x200000
#define MD_IO_PROT_OVRRD 0x200008
#define MD_HSPEC_PROTECT 0x200010
#define MD_IO_PROTECT 0x200000
#define MD_IO_PROT_OVRRD 0x200008
#define MD_HSPEC_PROTECT 0x200010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_MEMORY_CONFIG 0x200018
#define MD_REFRESH_CONTROL 0x200020
#define MD_FANDOP_CAC_STAT 0x200028
#define MD_MIG_DIFF_THRESH 0x200030
#define MD_MEMORY_CONFIG 0x200018
#define MD_REFRESH_CONTROL 0x200020
#define MD_FANDOP_CAC_STAT 0x200028
#define MD_MIG_DIFF_THRESH 0x200030
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_MIG_VALUE_THRESH 0x200038
#define MD_MIG_CANDIDATE 0x200040
#define MD_MIG_CANDIDATE_CLR 0x200048
#define MD_DIR_ERROR 0x200050
#define MD_MIG_VALUE_THRESH 0x200038
#define MD_MIG_CANDIDATE 0x200040
#define MD_MIG_CANDIDATE_CLR 0x200048
#define MD_DIR_ERROR 0x200050
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_DIR_ERROR_CLR 0x200058
#define MD_PROTOCOL_ERROR 0x200060
#define MD_PROTOCOL_ERROR_CLR 0x200068
#define MD_MEM_ERROR 0x200070
#define MD_DIR_ERROR_CLR 0x200058
#define MD_PROTOCOL_ERROR 0x200060
#define MD_PROTOCOL_ERROR_CLR 0x200068
#define MD_MEM_ERROR 0x200070
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_MEM_ERROR_CLR 0x200078
#define MD_MISC_ERROR 0x200080
#define MD_MISC_ERROR_CLR 0x200088
#define MD_MEM_DIMM_INIT 0x200090
#define MD_MEM_ERROR_CLR 0x200078
#define MD_MISC_ERROR 0x200080
#define MD_MISC_ERROR_CLR 0x200088
#define MD_MEM_DIMM_INIT 0x200090
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_DIR_DIMM_INIT 0x200098
#define MD_MOQ_SIZE 0x2000a0
#define MD_MLAN_CTL 0x2000a8
#define MD_PERF_SEL 0x210000
#define MD_DIR_DIMM_INIT 0x200098
#define MD_MOQ_SIZE 0x2000a0
#define MD_MLAN_CTL 0x2000a8
#define MD_PERF_SEL 0x210000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PERF_CNT0 0x210010
#define MD_PERF_CNT1 0x210018
#define MD_PERF_CNT2 0x210020
#define MD_PERF_CNT3 0x210028
#define MD_PERF_CNT0 0x210010
#define MD_PERF_CNT1 0x210018
#define MD_PERF_CNT2 0x210020
#define MD_PERF_CNT3 0x210028
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PERF_CNT4 0x210030
#define MD_PERF_CNT5 0x210038
#define MD_UREG0_0 0x220000
#define MD_UREG0_1 0x220008
#define MD_PERF_CNT4 0x210030
#define MD_PERF_CNT5 0x210038
#define MD_UREG0_0 0x220000
#define MD_UREG0_1 0x220008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_UREG0_2 0x220010
#define MD_UREG0_3 0x220018
#define MD_UREG0_4 0x220020
#define MD_UREG0_5 0x220028
#define MD_UREG0_2 0x220010
#define MD_UREG0_3 0x220018
#define MD_UREG0_4 0x220020
#define MD_UREG0_5 0x220028
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_UREG0_6 0x220030
#define MD_UREG0_7 0x220038
#define MD_SLOTID_USTAT 0x220048
#define MD_LED0 0x220050
#define MD_UREG0_6 0x220030
#define MD_UREG0_7 0x220038
#define MD_SLOTID_USTAT 0x220048
#define MD_LED0 0x220050
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_LED1 0x220058
#define MD_UREG1_0 0x220080
#define MD_UREG1_1 0x220088
#define MD_UREG1_2 0x220090
#define MD_LED1 0x220058
#define MD_UREG1_0 0x220080
#define MD_UREG1_1 0x220088
#define MD_UREG1_2 0x220090
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_UREG1_3 0x220098
#define MD_UREG1_4 0x2200a0
#define MD_UREG1_5 0x2200a8
#define MD_UREG1_6 0x2200b0
#define MD_UREG1_3 0x220098
#define MD_UREG1_4 0x2200a0
#define MD_UREG1_5 0x2200a8
#define MD_UREG1_6 0x2200b0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_UREG1_7 0x2200b8
#define MD_UREG1_8 0x2200c0
#define MD_UREG1_9 0x2200c8
#define MD_UREG1_10 0x2200d0
#define MD_UREG1_7 0x2200b8
#define MD_UREG1_8 0x2200c0
#define MD_UREG1_9 0x2200c8
#define MD_UREG1_10 0x2200d0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_UREG1_11 0x2200d8
#define MD_UREG1_12 0x2200e0
#define MD_UREG1_13 0x2200e8
#define MD_UREG1_14 0x2200f0
#define MD_UREG1_11 0x2200d8
#define MD_UREG1_12 0x2200e0
#define MD_UREG1_13 0x2200e8
#define MD_UREG1_14 0x2200f0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_UREG1_15 0x2200f8
#define MD_MEM_BANKS 8
#define MD_SIZE_EMPTY 0
#define MD_UREG1_15 0x2200f8
#define MD_MEM_BANKS 8
#define MD_SIZE_EMPTY 0
#define MD_SIZE_8MB 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SIZE_16MB 2
#define MD_SIZE_32MB 3
#define MD_SIZE_64MB 4
#define MD_SIZE_128MB 5
#define MD_SIZE_32MB 3
#define MD_SIZE_64MB 4
#define MD_SIZE_128MB 5
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SIZE_256MB 6
#define MD_SIZE_512MB 7
#define MD_SIZE_512MB 7
#define MD_SIZE_1GB 8
#define MD_SIZE_2GB 9
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SIZE_4GB 10
#define MD_SIZE_BYTES(size) ((size) == 0 ? 0 : 0x400000L << (size))
#define MD_SIZE_MBYTES(size) ((size) == 0 ? 0 : 4 << (size))
#define MMC_FPROM_CYC_SHFT 49
#define MMC_FPROM_CYC_SHFT 49
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MMC_FPROM_CYC_MASK (UINT64_CAST 31 << 49)
#define MMC_FPROM_WR_SHFT 44
#define MMC_FPROM_CYC_MASK (UINT64_CAST 31 << 49)
#define MMC_FPROM_WR_SHFT 44
#define MMC_FPROM_WR_MASK (UINT64_CAST 31 << 44)
#define MMC_UCTLR_CYC_SHFT 39
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -191,27 +191,27 @@
#define MLAN_RD_DATA (UINT64_CAST 0x01)
#define MLAN_RESET_DEFAULTS (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSU_CORECLK_TST_SHFT 7
#define MSU_CORECLK_TST_SHFT 7
#define MSU_CORECLK_TST_MASK (UINT64_CAST 1 << 7)
#define MSU_CORECLK_TST (UINT64_CAST 1 << 7)
#define MSU_CORECLK_SHFT 6
#define MSU_CORECLK_SHFT 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSU_CORECLK_MASK (UINT64_CAST 1 << 6)
#define MSU_CORECLK (UINT64_CAST 1 << 6)
#define MSU_NETSYNC_SHFT 5
#define MSU_NETSYNC_SHFT 5
#define MSU_NETSYNC_MASK (UINT64_CAST 1 << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSU_NETSYNC (UINT64_CAST 1 << 5)
#define MSU_FPROMRDY_SHFT 4
#define MSU_FPROMRDY_SHFT 4
#define MSU_FPROMRDY_MASK (UINT64_CAST 1 << 4)
#define MSU_FPROMRDY (UINT64_CAST 1 << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSU_I2CINTR_SHFT 3
#define MSU_I2CINTR_SHFT 3
#define MSU_I2CINTR_MASK (UINT64_CAST 1 << 3)
#define MSU_I2CINTR (UINT64_CAST 1 << 3)
#define MSU_SLOTID_MASK 0xff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSU_SN0_SLOTID_SHFT 0
#define MSU_SN0_SLOTID_SHFT 0
#define MSU_SN0_SLOTID_MASK (UINT64_CAST 7)
#define MSU_SN00_SLOTID_SHFT 7
#define MSU_SN00_SLOTID_MASK (UINT64_CAST 0x80)
@ -239,55 +239,55 @@
#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
#define MD_MIG_CANDIDATE_NODEID_SHFT 20
#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
#define MD_MIG_CANDIDATE_ADDR_SHFT 14
#define MD_MIG_CANDIDATE_ADDR_SHFT 14
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_BANK_SHFT 29
#define MD_BANK_SHFT 29
#define MD_BANK_MASK (UINT64_CAST 7 << 29)
#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT)
#define MD_BANK_SIZE (UINT64_CAST 1 << MD_BANK_SHFT)
#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_DIR_SHARED (UINT64_CAST 0x0)
#define MD_DIR_POISONED (UINT64_CAST 0x1)
#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x2)
#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x3)
#define MD_DIR_SHARED (UINT64_CAST 0x0)
#define MD_DIR_POISONED (UINT64_CAST 0x1)
#define MD_DIR_EXCLUSIVE (UINT64_CAST 0x2)
#define MD_DIR_BUSY_SHARED (UINT64_CAST 0x3)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x4)
#define MD_DIR_WAIT (UINT64_CAST 0x5)
#define MD_DIR_UNOWNED (UINT64_CAST 0x7)
#define MD_DIR_BUSY_EXCL (UINT64_CAST 0x4)
#define MD_DIR_WAIT (UINT64_CAST 0x5)
#define MD_DIR_UNOWNED (UINT64_CAST 0x7)
#define MD_DIR_FORCE_ECC (UINT64_CAST 1 << 63)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PDIR_MASK 0xffffffffffff
#define MD_PDIR_ECC_SHFT 0
#define MD_PDIR_MASK 0xffffffffffff
#define MD_PDIR_ECC_SHFT 0
#define MD_PDIR_ECC_MASK 0x7f
#define MD_PDIR_PRIO_SHFT 8
#define MD_PDIR_PRIO_SHFT 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PDIR_PRIO_MASK (0xf << 8)
#define MD_PDIR_AX_SHFT 7
#define MD_PDIR_AX_SHFT 7
#define MD_PDIR_AX_MASK (1 << 7)
#define MD_PDIR_AX (1 << 7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PDIR_FINE_SHFT 12
#define MD_PDIR_FINE_SHFT 12
#define MD_PDIR_FINE_MASK (1 << 12)
#define MD_PDIR_FINE (1 << 12)
#define MD_PDIR_OCT_SHFT 13
#define MD_PDIR_OCT_SHFT 13
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PDIR_OCT_MASK (7 << 13)
#define MD_PDIR_STATE_SHFT 13
#define MD_PDIR_STATE_SHFT 13
#define MD_PDIR_STATE_MASK (7 << 13)
#define MD_PDIR_ONECNT_SHFT 16
#define MD_PDIR_ONECNT_SHFT 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PDIR_ONECNT_MASK (0x3f << 16)
#define MD_PDIR_PTR_SHFT 22
#define MD_PDIR_PTR_SHFT 22
#define MD_PDIR_PTR_MASK (UINT64_CAST 0x7ff << 22)
#define MD_PDIR_VECMSB_SHFT 22
#define MD_PDIR_VECMSB_SHFT 22
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PDIR_VECMSB_BITMASK 0x3ffffff
#define MD_PDIR_VECMSB_BITSHFT 27
#define MD_PDIR_VECMSB_MASK (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
#define MD_PDIR_CWOFF_SHFT 7
#define MD_PDIR_CWOFF_SHFT 7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PDIR_CWOFF_MASK (7 << 7)
#define MD_PDIR_VECLSB_SHFT 10
#define MD_PDIR_VECLSB_SHFT 10
#define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff)
#define MD_PDIR_VECLSB_BITSHFT 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -296,29 +296,29 @@
#define MD_PDIR_INIT_HI 0
#define MD_PDIR_INIT_PROT (MD_PROT_RW << MD_PPROT_IO_SHFT | MD_PROT_RW << MD_PPROT_SHFT)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SDIR_MASK 0xffff
#define MD_SDIR_ECC_SHFT 0
#define MD_SDIR_MASK 0xffff
#define MD_SDIR_ECC_SHFT 0
#define MD_SDIR_ECC_MASK 0x1f
#define MD_SDIR_PRIO_SHFT 6
#define MD_SDIR_PRIO_SHFT 6
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SDIR_PRIO_MASK (1 << 6)
#define MD_SDIR_AX_SHFT 5
#define MD_SDIR_AX_SHFT 5
#define MD_SDIR_AX_MASK (1 << 5)
#define MD_SDIR_AX (1 << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SDIR_STATE_SHFT 7
#define MD_SDIR_STATE_SHFT 7
#define MD_SDIR_STATE_MASK (7 << 7)
#define MD_SDIR_PTR_SHFT 10
#define MD_SDIR_PTR_SHFT 10
#define MD_SDIR_PTR_MASK (0x3f << 10)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SDIR_CWOFF_SHFT 5
#define MD_SDIR_CWOFF_SHFT 5
#define MD_SDIR_CWOFF_MASK (7 << 5)
#define MD_SDIR_VECMSB_SHFT 11
#define MD_SDIR_VECMSB_SHFT 11
#define MD_SDIR_VECMSB_BITMASK 0x1f
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SDIR_VECMSB_BITSHFT 7
#define MD_SDIR_VECMSB_MASK (MD_SDIR_VECMSB_BITMASK << 11)
#define MD_SDIR_VECLSB_SHFT 5
#define MD_SDIR_VECLSB_SHFT 5
#define MD_SDIR_VECLSB_BITMASK 0x7ff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SDIR_VECLSB_BITSHFT 0
@ -332,23 +332,23 @@
#define MD_PROT_NO (UINT64_CAST 0x0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PROT_BAD (UINT64_CAST 0x5)
#define MD_PPROT_SHFT 0
#define MD_PPROT_SHFT 0
#define MD_PPROT_MASK 7
#define MD_PPROT_MIGMD_SHFT 3
#define MD_PPROT_MIGMD_SHFT 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PPROT_MIGMD_MASK (3 << 3)
#define MD_PPROT_REFCNT_SHFT 5
#define MD_PPROT_REFCNT_SHFT 5
#define MD_PPROT_REFCNT_WIDTH 0x7ffff
#define MD_PPROT_REFCNT_MASK (MD_PPROT_REFCNT_WIDTH << 5)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_PPROT_IO_SHFT 45
#define MD_PPROT_IO_SHFT 45
#define MD_PPROT_IO_MASK (UINT64_CAST 7 << 45)
#define MD_SPROT_SHFT 0
#define MD_SPROT_SHFT 0
#define MD_SPROT_MASK 7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SPROT_MIGMD_SHFT 3
#define MD_SPROT_MIGMD_SHFT 3
#define MD_SPROT_MIGMD_MASK (3 << 3)
#define MD_SPROT_REFCNT_SHFT 5
#define MD_SPROT_REFCNT_SHFT 5
#define MD_SPROT_REFCNT_WIDTH 0x7ff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MD_SPROT_REFCNT_MASK (MD_SPROT_REFCNT_WIDTH << 5)

116
libc/kernel/arch-mips/asm/sn/sn0/hubni.h
View File

@ -24,47 +24,47 @@
#endif
#define NI_BASE 0x600000
#define NI_BASE_TABLES 0x630000
#define NI_STATUS_REV_ID 0x600000
#define NI_STATUS_REV_ID 0x600000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NI_PORT_RESET 0x600008
#define NI_PROTECTION 0x600010
#define NI_GLOBAL_PARMS 0x600018
#define NI_SCRATCH_REG0 0x600100
#define NI_PORT_RESET 0x600008
#define NI_PROTECTION 0x600010
#define NI_GLOBAL_PARMS 0x600018
#define NI_SCRATCH_REG0 0x600100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NI_SCRATCH_REG1 0x600108
#define NI_DIAG_PARMS 0x600110
#define NI_VECTOR_PARMS 0x600200
#define NI_VECTOR 0x600208
#define NI_SCRATCH_REG1 0x600108
#define NI_DIAG_PARMS 0x600110
#define NI_VECTOR_PARMS 0x600200
#define NI_VECTOR 0x600208
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NI_VECTOR_DATA 0x600210
#define NI_VECTOR_STATUS 0x600300
#define NI_RETURN_VECTOR 0x600308
#define NI_VECTOR_READ_DATA 0x600310
#define NI_VECTOR_DATA 0x600210
#define NI_VECTOR_STATUS 0x600300
#define NI_RETURN_VECTOR 0x600308
#define NI_VECTOR_READ_DATA 0x600310
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NI_VECTOR_CLEAR 0x600380
#define NI_IO_PROTECT 0x600400
#define NI_IO_PROT_OVRRD 0x600408
#define NI_AGE_CPU0_MEMORY 0x600500
#define NI_VECTOR_CLEAR 0x600380
#define NI_IO_PROTECT 0x600400
#define NI_IO_PROT_OVRRD 0x600408
#define NI_AGE_CPU0_MEMORY 0x600500
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NI_AGE_CPU0_PIO 0x600508
#define NI_AGE_CPU1_MEMORY 0x600510
#define NI_AGE_CPU1_PIO 0x600518
#define NI_AGE_GBR_MEMORY 0x600520
#define NI_AGE_CPU0_PIO 0x600508
#define NI_AGE_CPU1_MEMORY 0x600510
#define NI_AGE_CPU1_PIO 0x600518
#define NI_AGE_GBR_MEMORY 0x600520
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NI_AGE_GBR_PIO 0x600528
#define NI_AGE_IO_MEMORY 0x600530
#define NI_AGE_IO_PIO 0x600538
#define NI_AGE_GBR_PIO 0x600528
#define NI_AGE_IO_MEMORY 0x600530
#define NI_AGE_IO_PIO 0x600538
#define NI_AGE_REG_MIN NI_AGE_CPU0_MEMORY
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NI_AGE_REG_MAX NI_AGE_IO_PIO
#define NI_PORT_PARMS 0x608000
#define NI_PORT_ERROR 0x608008
#define NI_PORT_ERROR_CLEAR 0x608088
#define NI_PORT_PARMS 0x608000
#define NI_PORT_ERROR 0x608008
#define NI_PORT_ERROR_CLEAR 0x608088
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NI_META_TABLE0 0x638000
#define NI_META_TABLE0 0x638000
#define NI_META_TABLE(_x) (NI_META_TABLE0 + (8 * (_x)))
#define NI_META_ENTRIES 32
#define NI_LOCAL_TABLE0 0x638100
#define NI_LOCAL_TABLE0 0x638100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NI_LOCAL_TABLE(_x) (NI_LOCAL_TABLE0 + (8 * (_x)))
#define NI_LOCAL_ENTRIES 16
@ -73,55 +73,55 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NSRI_LINKUP_SHFT 29
#define NSRI_LINKUP_MASK (UINT64_CAST 0x1 << 29)
#define NSRI_DOWNREASON_SHFT 28
#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28)
#define NSRI_DOWNREASON_SHFT 28
#define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NSRI_MORENODES_SHFT 18
#define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18)
#define NSRI_MORENODES_MASK (UINT64_CAST 1 << 18)
#define MORE_MEMORY 0
#define MORE_NODES 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NSRI_REGIONSIZE_SHFT 17
#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17)
#define NSRI_REGIONSIZE_MASK (UINT64_CAST 1 << 17)
#define REGIONSIZE_FINE 1
#define REGIONSIZE_COARSE 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NSRI_NODEID_SHFT 8
#define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)
#define NSRI_NODEID_MASK (UINT64_CAST 0x1ff << 8)
#define NSRI_REV_SHFT 4
#define NSRI_REV_MASK (UINT64_CAST 0xf << 4)
#define NSRI_REV_MASK (UINT64_CAST 0xf << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NSRI_CHIPID_SHFT 0
#define NSRI_CHIPID_MASK (UINT64_CAST 0xf)
#define NSRI_CHIPID_MASK (UINT64_CAST 0xf)
#define NASID_TO_FINEREG_SHFT 0
#define NASID_TO_COARSEREG_SHFT 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NPR_PORTRESET (UINT64_CAST 1 << 7)
#define NPR_LINKRESET (UINT64_CAST 1 << 1)
#define NPR_LOCALRESET (UINT64_CAST 1)
#define NPR_PORTRESET (UINT64_CAST 1 << 7)
#define NPR_LINKRESET (UINT64_CAST 1 << 1)
#define NPR_LOCALRESET (UINT64_CAST 1)
#define NPROT_RESETOK (UINT64_CAST 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NGP_MAXRETRY_SHFT 48
#define NGP_MAXRETRY_SHFT 48
#define NGP_MAXRETRY_MASK (UINT64_CAST 0x3ff << 48)
#define NGP_TAILTOWRAP_SHFT 32
#define NGP_TAILTOWRAP_SHFT 32
#define NGP_TAILTOWRAP_MASK (UINT64_CAST 0xffff << 32)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NGP_CREDITTOVAL_SHFT 16
#define NGP_CREDITTOVAL_SHFT 16
#define NGP_CREDITTOVAL_MASK (UINT64_CAST 0xf << 16)
#define NGP_TAILTOVAL_SHFT 4
#define NGP_TAILTOVAL_SHFT 4
#define NGP_TAILTOVAL_MASK (UINT64_CAST 0xf << 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NDP_PORTTORESET (UINT64_CAST 1 << 18)
#define NDP_LLP8BITMODE (UINT64_CAST 1 << 12)
#define NDP_PORTDISABLE (UINT64_CAST 1 << 6)
#define NDP_SENDERROR (UINT64_CAST 1)
#define NDP_PORTTORESET (UINT64_CAST 1 << 18)
#define NDP_LLP8BITMODE (UINT64_CAST 1 << 12)
#define NDP_PORTDISABLE (UINT64_CAST 1 << 6)
#define NDP_SENDERROR (UINT64_CAST 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NVP_PIOID_SHFT 40
#define NVP_PIOID_MASK (UINT64_CAST 0x3ff << 40)
#define NVP_WRITEID_SHFT 32
#define NVP_WRITEID_MASK (UINT64_CAST 0xff << 32)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8)
#define NVP_ADDRESS_MASK (UINT64_CAST 0xffff8)
#define NVP_TYPE_SHFT 0
#define NVP_TYPE_MASK (UINT64_CAST 0x3)
#define NVS_VALID (UINT64_CAST 1 << 63)
@ -134,21 +134,21 @@
#define NVS_PIOID_MASK (UINT64_CAST 0x3ff << 40)
#define NVS_WRITEID_SHFT 32
#define NVS_WRITEID_MASK (UINT64_CAST 0xff << 32)
#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8)
#define NVS_ADDRESS_MASK (UINT64_CAST 0xfffffff8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NVS_TYPE_SHFT 0
#define NVS_TYPE_MASK (UINT64_CAST 0x7)
#define NVS_ERROR_MASK (UINT64_CAST 0x4)
#define PIOTYPE_READ 0
#define NVS_ERROR_MASK (UINT64_CAST 0x4)
#define PIOTYPE_READ 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PIOTYPE_WRITE 1
#define PIOTYPE_UNDEFINED 2
#define PIOTYPE_EXCHANGE 3
#define PIOTYPE_ADDR_ERR 4
#define PIOTYPE_WRITE 1
#define PIOTYPE_UNDEFINED 2
#define PIOTYPE_EXCHANGE 3
#define PIOTYPE_ADDR_ERR 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PIOTYPE_CMD_ERR 5
#define PIOTYPE_PROT_ERR 6
#define PIOTYPE_UNKNOWN 7
#define PIOTYPE_CMD_ERR 5
#define PIOTYPE_PROT_ERR 6
#define PIOTYPE_UNKNOWN 7
#define NAGE_VCH_SHFT 10
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define NAGE_VCH_MASK (UINT64_CAST 3 << 10)

218
libc/kernel/arch-mips/asm/sn/sn0/hubpi.h
View File

@ -21,15 +21,15 @@
#include <linux/types.h>
#define PI_BASE 0x000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_CPU_PROTECT 0x000000
#define PI_PROT_OVERRD 0x000008
#define PI_IO_PROTECT 0x000010
#define PI_REGION_PRESENT 0x000018
#define PI_CPU_PROTECT 0x000000
#define PI_PROT_OVERRD 0x000008
#define PI_IO_PROTECT 0x000010
#define PI_REGION_PRESENT 0x000018
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_CPU_NUM 0x000020
#define PI_CALIAS_SIZE 0x000028
#define PI_MAX_CRB_TIMEOUT 0x000030
#define PI_CRB_SFACTOR 0x000038
#define PI_CPU_NUM 0x000020
#define PI_CALIAS_SIZE 0x000028
#define PI_MAX_CRB_TIMEOUT 0x000030
#define PI_CRB_SFACTOR 0x000038
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_CALIAS_SIZE_0 0
#define PI_CALIAS_SIZE_4K 1
@ -51,143 +51,143 @@
#define PI_CALIAS_SIZE_32M 14
#define PI_CALIAS_SIZE_64M 15
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_CPU_PRESENT_A 0x000040
#define PI_CPU_PRESENT_B 0x000048
#define PI_CPU_ENABLE_A 0x000050
#define PI_CPU_ENABLE_B 0x000058
#define PI_CPU_PRESENT_A 0x000040
#define PI_CPU_PRESENT_B 0x000048
#define PI_CPU_ENABLE_A 0x000050
#define PI_CPU_ENABLE_B 0x000058
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_REPLY_LEVEL 0x000060
#define PI_HARDRESET_BIT 0x020068
#define PI_NMI_A 0x000070
#define PI_NMI_B 0x000078
#define PI_REPLY_LEVEL 0x000060
#define PI_HARDRESET_BIT 0x020068
#define PI_NMI_A 0x000070
#define PI_NMI_B 0x000078
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A)
#define PI_SOFTRESET 0x000080
#define PI_INT_PEND_MOD 0x000090
#define PI_INT_PEND0 0x000098
#define PI_SOFTRESET 0x000080
#define PI_INT_PEND_MOD 0x000090
#define PI_INT_PEND0 0x000098
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_INT_PEND1 0x0000a0
#define PI_INT_MASK0_A 0x0000a8
#define PI_INT_MASK1_A 0x0000b0
#define PI_INT_MASK0_B 0x0000b8
#define PI_INT_PEND1 0x0000a0
#define PI_INT_MASK0_A 0x0000a8
#define PI_INT_MASK1_A 0x0000b0
#define PI_INT_MASK0_B 0x0000b8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_INT_MASK1_B 0x0000c0
#define PI_INT_MASK_OFFSET 0x10
#define PI_CC_PEND_SET_A 0x0000c8
#define PI_CC_PEND_SET_B 0x0000d0
#define PI_INT_MASK1_B 0x0000c0
#define PI_INT_MASK_OFFSET 0x10
#define PI_CC_PEND_SET_A 0x0000c8
#define PI_CC_PEND_SET_B 0x0000d0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_CC_PEND_CLR_A 0x0000d8
#define PI_CC_PEND_CLR_B 0x0000e0
#define PI_CC_MASK 0x0000e8
#define PI_INT_SET_OFFSET 0x08
#define PI_CC_PEND_CLR_A 0x0000d8
#define PI_CC_PEND_CLR_B 0x0000e0
#define PI_CC_MASK 0x0000e8
#define PI_INT_SET_OFFSET 0x08
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_RT_COUNT 0x030100
#define PI_RT_COMPARE_A 0x000108
#define PI_RT_COMPARE_B 0x000110
#define PI_PROFILE_COMPARE 0x000118
#define PI_RT_COUNT 0x030100
#define PI_RT_COMPARE_A 0x000108
#define PI_RT_COMPARE_B 0x000110
#define PI_PROFILE_COMPARE 0x000118
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_RT_PEND_A 0x000120
#define PI_RT_PEND_B 0x000128
#define PI_PROF_PEND_A 0x000130
#define PI_PROF_PEND_B 0x000138
#define PI_RT_PEND_A 0x000120
#define PI_RT_PEND_B 0x000128
#define PI_PROF_PEND_A 0x000130
#define PI_PROF_PEND_B 0x000138
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_RT_EN_A 0x000140
#define PI_RT_EN_B 0x000148
#define PI_PROF_EN_A 0x000150
#define PI_PROF_EN_B 0x000158
#define PI_RT_EN_A 0x000140
#define PI_RT_EN_B 0x000148
#define PI_PROF_EN_A 0x000150
#define PI_PROF_EN_B 0x000158
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_RT_LOCAL_CTRL 0x000160
#define PI_RT_FILTER_CTRL 0x000168
#define PI_COUNT_OFFSET 0x08
#define PI_BIST_WRITE_DATA 0x000200
#define PI_RT_LOCAL_CTRL 0x000160
#define PI_RT_FILTER_CTRL 0x000168
#define PI_COUNT_OFFSET 0x08
#define PI_BIST_WRITE_DATA 0x000200
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_BIST_READ_DATA 0x000208
#define PI_BIST_COUNT_TARG 0x000210
#define PI_BIST_READY 0x000218
#define PI_BIST_SHIFT_LOAD 0x000220
#define PI_BIST_READ_DATA 0x000208
#define PI_BIST_COUNT_TARG 0x000210
#define PI_BIST_READY 0x000218
#define PI_BIST_SHIFT_LOAD 0x000220
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_BIST_SHIFT_UNLOAD 0x000228
#define PI_BIST_ENTER_RUN 0x000230
#define PI_GFX_PAGE_A 0x000300
#define PI_GFX_CREDIT_CNTR_A 0x000308
#define PI_BIST_SHIFT_UNLOAD 0x000228
#define PI_BIST_ENTER_RUN 0x000230
#define PI_GFX_PAGE_A 0x000300
#define PI_GFX_CREDIT_CNTR_A 0x000308
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_GFX_BIAS_A 0x000310
#define PI_GFX_INT_CNTR_A 0x000318
#define PI_GFX_INT_CMP_A 0x000320
#define PI_GFX_PAGE_B 0x000328
#define PI_GFX_BIAS_A 0x000310
#define PI_GFX_INT_CNTR_A 0x000318
#define PI_GFX_INT_CMP_A 0x000320
#define PI_GFX_PAGE_B 0x000328
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_GFX_CREDIT_CNTR_B 0x000330
#define PI_GFX_BIAS_B 0x000338
#define PI_GFX_INT_CNTR_B 0x000340
#define PI_GFX_INT_CMP_B 0x000348
#define PI_GFX_CREDIT_CNTR_B 0x000330
#define PI_GFX_BIAS_B 0x000338
#define PI_GFX_INT_CNTR_B 0x000340
#define PI_GFX_INT_CMP_B 0x000348
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_GFX_OFFSET (PI_GFX_PAGE_B - PI_GFX_PAGE_A)
#define PI_GFX_PAGE_ENABLE 0x0000010000000000LL
#define PI_ERR_INT_PEND 0x000400
#define PI_ERR_INT_MASK_A 0x000408
#define PI_ERR_INT_PEND 0x000400
#define PI_ERR_INT_MASK_A 0x000408
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_INT_MASK_B 0x000410
#define PI_ERR_STACK_ADDR_A 0x000418
#define PI_ERR_STACK_ADDR_B 0x000420
#define PI_ERR_STACK_SIZE 0x000428
#define PI_ERR_INT_MASK_B 0x000410
#define PI_ERR_STACK_ADDR_A 0x000418
#define PI_ERR_STACK_ADDR_B 0x000420
#define PI_ERR_STACK_SIZE 0x000428
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_STATUS0_A 0x000430
#define PI_ERR_STATUS0_A_RCLR 0x000438
#define PI_ERR_STATUS1_A 0x000440
#define PI_ERR_STATUS1_A_RCLR 0x000448
#define PI_ERR_STATUS0_A 0x000430
#define PI_ERR_STATUS0_A_RCLR 0x000438
#define PI_ERR_STATUS1_A 0x000440
#define PI_ERR_STATUS1_A_RCLR 0x000448
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_STATUS0_B 0x000450
#define PI_ERR_STATUS0_B_RCLR 0x000458
#define PI_ERR_STATUS1_B 0x000460
#define PI_ERR_STATUS1_B_RCLR 0x000468
#define PI_ERR_STATUS0_B 0x000450
#define PI_ERR_STATUS0_B_RCLR 0x000458
#define PI_ERR_STATUS1_B 0x000460
#define PI_ERR_STATUS1_B_RCLR 0x000468
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_SPOOL_CMP_A 0x000470
#define PI_SPOOL_CMP_B 0x000478
#define PI_CRB_TIMEOUT_A 0x000480
#define PI_CRB_TIMEOUT_B 0x000488
#define PI_SPOOL_CMP_A 0x000470
#define PI_SPOOL_CMP_B 0x000478
#define PI_CRB_TIMEOUT_A 0x000480
#define PI_CRB_TIMEOUT_B 0x000488
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_SYSAD_ERRCHK_EN 0x000490
#define PI_BAD_CHECK_BIT_A 0x000498
#define PI_BAD_CHECK_BIT_B 0x0004a0
#define PI_NACK_CNT_A 0x0004a8
#define PI_SYSAD_ERRCHK_EN 0x000490
#define PI_BAD_CHECK_BIT_A 0x000498
#define PI_BAD_CHECK_BIT_B 0x0004a0
#define PI_NACK_CNT_A 0x0004a8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_NACK_CNT_B 0x0004b0
#define PI_NACK_CMP 0x0004b8
#define PI_NACK_CNT_B 0x0004b0
#define PI_NACK_CMP 0x0004b8
#define PI_STACKADDR_OFFSET (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
#define PI_ERRSTAT_OFFSET (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_RDCLR_OFFSET (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)
#define PI_ERR_SPOOL_CMP_B 0x00000001
#define PI_ERR_SPOOL_CMP_B 0x00000001
#define PI_ERR_SPOOL_CMP_A 0x00000002
#define PI_ERR_SPUR_MSG_B 0x00000004
#define PI_ERR_SPUR_MSG_B 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_SPUR_MSG_A 0x00000008
#define PI_ERR_WRB_TERR_B 0x00000010
#define PI_ERR_WRB_TERR_B 0x00000010
#define PI_ERR_WRB_TERR_A 0x00000020
#define PI_ERR_WRB_WERR_B 0x00000040
#define PI_ERR_WRB_WERR_B 0x00000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_WRB_WERR_A 0x00000080
#define PI_ERR_SYSSTATE_B 0x00000100
#define PI_ERR_SYSSTATE_B 0x00000100
#define PI_ERR_SYSSTATE_A 0x00000200
#define PI_ERR_SYSAD_DATA_B 0x00000400
#define PI_ERR_SYSAD_DATA_B 0x00000400
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_SYSAD_DATA_A 0x00000800
#define PI_ERR_SYSAD_ADDR_B 0x00001000
#define PI_ERR_SYSAD_ADDR_B 0x00001000
#define PI_ERR_SYSAD_ADDR_A 0x00002000
#define PI_ERR_SYSCMD_DATA_B 0x00004000
#define PI_ERR_SYSCMD_DATA_B 0x00004000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_SYSCMD_DATA_A 0x00008000
#define PI_ERR_SYSCMD_ADDR_B 0x00010000
#define PI_ERR_SYSCMD_ADDR_B 0x00010000
#define PI_ERR_SYSCMD_ADDR_A 0x00020000
#define PI_ERR_BAD_SPOOL_B 0x00040000
#define PI_ERR_BAD_SPOOL_B 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_BAD_SPOOL_A 0x00080000
#define PI_ERR_UNCAC_UNCORR_B 0x00100000
#define PI_ERR_UNCAC_UNCORR_B 0x00100000
#define PI_ERR_UNCAC_UNCORR_A 0x00200000
#define PI_ERR_SYSSTATE_TAG_B 0x00400000
#define PI_ERR_SYSSTATE_TAG_B 0x00400000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_ERR_SYSSTATE_TAG_A 0x00800000
#define PI_ERR_MD_UNCORR 0x01000000
#define PI_ERR_MD_UNCORR 0x01000000
#define PI_ERR_CLEAR_ALL_A 0x00aaaaaa
#define PI_ERR_CLEAR_ALL_B 0x00555555
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -266,8 +266,8 @@
#define ERR_STK_ADDR_SHFT 7
#define ERR_STAT0_ADDR_SHFT 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_MIN_STACK_SIZE 4096
#define PI_STACK_SIZE_SHFT 12
#define PI_MIN_STACK_SIZE 4096
#define PI_STACK_SIZE_SHFT 12
#define ERR_STACK_SIZE_BYTES(_sz) ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)
#ifndef __ASSEMBLY__
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -323,15 +323,15 @@ typedef union pi_err_stat1 {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
typedef u64 rtc_time_t;
#endif
#define PI_SYSAD_ERRCHK_ECCGEN 0x01
#define PI_SYSAD_ERRCHK_QUALGEN 0x02
#define PI_SYSAD_ERRCHK_ECCGEN 0x01
#define PI_SYSAD_ERRCHK_QUALGEN 0x02
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_SYSAD_ERRCHK_SADP 0x04
#define PI_SYSAD_ERRCHK_CMDP 0x08
#define PI_SYSAD_ERRCHK_STATE 0x10
#define PI_SYSAD_ERRCHK_QUAL 0x20
#define PI_SYSAD_ERRCHK_SADP 0x04
#define PI_SYSAD_ERRCHK_CMDP 0x08
#define PI_SYSAD_ERRCHK_STATE 0x10
#define PI_SYSAD_ERRCHK_QUAL 0x20
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PI_SYSAD_CHECK_ALL 0x3f
#define PI_SYSAD_CHECK_ALL 0x3f
#define HUB_IP_PEND0 0x0400
#define HUB_IP_PEND1_CC 0x0800
#define HUB_IP_RT 0x1000

36
libc/kernel/arch-mips/asm/socket.h
View File

@ -21,29 +21,29 @@
#include <asm/sockios.h>
#define SOL_SOCKET 0xffff
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SO_DEBUG 0x0001
#define SO_REUSEADDR 0x0004
#define SO_KEEPALIVE 0x0008
#define SO_DONTROUTE 0x0010
#define SO_DEBUG 0x0001
#define SO_REUSEADDR 0x0004
#define SO_KEEPALIVE 0x0008
#define SO_DONTROUTE 0x0010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SO_BROADCAST 0x0020
#define SO_LINGER 0x0080
#define SO_OOBINLINE 0x0100
#define SO_TYPE 0x1008
#define SO_BROADCAST 0x0020
#define SO_LINGER 0x0080
#define SO_OOBINLINE 0x0100
#define SO_TYPE 0x1008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SO_STYLE SO_TYPE
#define SO_ERROR 0x1007
#define SO_SNDBUF 0x1001
#define SO_RCVBUF 0x1002
#define SO_STYLE SO_TYPE
#define SO_ERROR 0x1007
#define SO_SNDBUF 0x1001
#define SO_RCVBUF 0x1002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SO_SNDLOWAT 0x1003
#define SO_RCVLOWAT 0x1004
#define SO_SNDTIMEO 0x1005
#define SO_RCVTIMEO 0x1006
#define SO_SNDLOWAT 0x1003
#define SO_RCVLOWAT 0x1004
#define SO_SNDTIMEO 0x1005
#define SO_RCVTIMEO 0x1006
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SO_ACCEPTCONN 0x1009
#define SO_PROTOCOL 0x1028
#define SO_DOMAIN 0x1029
#define SO_PROTOCOL 0x1028
#define SO_DOMAIN 0x1029
#define SO_NO_CHECK 11
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SO_PRIORITY 12

4
libc/kernel/arch-mips/asm/sockios.h
View File

@ -26,6 +26,6 @@
#define SIOCSPGRP _IOW('s', 8, pid_t)
#define SIOCGPGRP _IOR('s', 9, pid_t)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define SIOCGSTAMP 0x8906
#define SIOCGSTAMPNS 0x8907
#define SIOCGSTAMP 0x8906
#define SIOCGSTAMPNS 0x8907
#endif

10
libc/kernel/arch-mips/asm/sysmips.h
View File

@ -18,11 +18,11 @@
****************************************************************************/
#ifndef _ASM_SYSMIPS_H
#define _ASM_SYSMIPS_H
#define SETNAME 1
#define FLUSH_CACHE 3
#define SETNAME 1
#define FLUSH_CACHE 3
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MIPS_FIXADE 7
#define MIPS_RDNVRAM 10
#define MIPS_ATOMIC_SET 2001
#define MIPS_FIXADE 7
#define MIPS_RDNVRAM 10
#define MIPS_ATOMIC_SET 2001
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

150
libc/kernel/arch-mips/asm/termbits.h
View File

@ -59,51 +59,51 @@ struct ktermios {
speed_t c_ispeed;
speed_t c_ospeed;
};
#define VINTR 0
#define VINTR 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VQUIT 1
#define VERASE 2
#define VKILL 3
#define VMIN 4
#define VQUIT 1
#define VERASE 2
#define VKILL 3
#define VMIN 4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VTIME 5
#define VEOL2 6
#define VSWTC 7
#define VTIME 5
#define VEOL2 6
#define VSWTC 7
#define VSWTCH VSWTC
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VSTART 8
#define VSTOP 9
#define VSUSP 10
#define VREPRINT 12
#define VSTART 8
#define VSTOP 9
#define VSUSP 10
#define VREPRINT 12
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VDISCARD 13
#define VWERASE 14
#define VLNEXT 15
#define VEOF 16
#define VDISCARD 13
#define VWERASE 14
#define VLNEXT 15
#define VEOF 16
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define VEOL 17
#define IGNBRK 0000001
#define BRKINT 0000002
#define IGNPAR 0000004
#define VEOL 17
#define IGNBRK 0000001
#define BRKINT 0000002
#define IGNPAR 0000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define PARMRK 0000010
#define INPCK 0000020
#define ISTRIP 0000040
#define INLCR 0000100
#define PARMRK 0000010
#define INPCK 0000020
#define ISTRIP 0000040
#define INLCR 0000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IGNCR 0000200
#define ICRNL 0000400
#define IUCLC 0001000
#define IXON 0002000
#define IGNCR 0000200
#define ICRNL 0000400
#define IUCLC 0001000
#define IXON 0002000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IXANY 0004000
#define IXOFF 0010000
#define IMAXBEL 0020000
#define IUTF8 0040000
#define IXANY 0004000
#define IXOFF 0010000
#define IMAXBEL 0020000
#define IUTF8 0040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define OPOST 0000001
#define OLCUC 0000002
#define ONLCR 0000004
#define OPOST 0000001
#define OLCUC 0000002
#define ONLCR 0000004
#define OCRNL 0000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ONOCR 0000020
@ -141,7 +141,7 @@ struct ktermios {
#define FF1 0100000
#define CBAUD 0010017
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define B0 0000000
#define B0 0000000
#define B50 0000001
#define B75 0000002
#define B110 0000003
@ -163,20 +163,20 @@ struct ktermios {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define EXTA B19200
#define EXTB B38400
#define CSIZE 0000060
#define CS5 0000000
#define CSIZE 0000060
#define CS5 0000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CS6 0000020
#define CS7 0000040
#define CS8 0000060
#define CSTOPB 0000100
#define CS6 0000020
#define CS7 0000040
#define CS8 0000060
#define CSTOPB 0000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CREAD 0000200
#define PARENB 0000400
#define PARODD 0001000
#define HUPCL 0002000
#define CREAD 0000200
#define PARENB 0000400
#define PARODD 0001000
#define HUPCL 0002000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CLOCAL 0004000
#define CLOCAL 0004000
#define CBAUDEX 0010000
#define BOTHER 0010000
#define B57600 0010001
@ -198,43 +198,43 @@ struct ktermios {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define B3500000 0010016
#define B4000000 0010017
#define CIBAUD 002003600000
#define CMSPAR 010000000000
#define CIBAUD 002003600000
#define CMSPAR 010000000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CRTSCTS 020000000000
#define IBSHIFT 16
#define ISIG 0000001
#define ICANON 0000002
#define CRTSCTS 020000000000
#define IBSHIFT 16
#define ISIG 0000001
#define ICANON 0000002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define XCASE 0000004
#define ECHO 0000010
#define ECHOE 0000020
#define ECHOK 0000040
#define ECHO 0000010
#define ECHOE 0000020
#define ECHOK 0000040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ECHONL 0000100
#define NOFLSH 0000200
#define IEXTEN 0000400
#define ECHOCTL 0001000
#define ECHONL 0000100
#define NOFLSH 0000200
#define IEXTEN 0000400
#define ECHOCTL 0001000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define ECHOPRT 0002000
#define ECHOKE 0004000
#define ECHOPRT 0002000
#define ECHOKE 0004000
#define FLUSHO 0020000
#define PENDIN 0040000
#define PENDIN 0040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TOSTOP 0100000
#define TOSTOP 0100000
#define ITOSTOP TOSTOP
#define TIOCSER_TEMT 0x01
#define TCOOFF 0
#define TIOCSER_TEMT 0x01
#define TCOOFF 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCOON 1
#define TCIOFF 2
#define TCION 3
#define TCIFLUSH 0
#define TCOON 1
#define TCIOFF 2
#define TCION 3
#define TCIFLUSH 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCOFLUSH 1
#define TCIOFLUSH 2
#define TCSANOW TCSETS
#define TCSADRAIN TCSETSW
#define TCOFLUSH 1
#define TCIOFLUSH 2
#define TCSANOW TCSETS
#define TCSADRAIN TCSETSW
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSAFLUSH TCSETSF
#define TCSAFLUSH TCSETSF
#endif

18
libc/kernel/arch-mips/asm/termios.h
View File

@ -68,20 +68,20 @@ struct termio {
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char c_cc[NCCS];
};
#define TIOCM_LE 0x001
#define TIOCM_DTR 0x002
#define TIOCM_LE 0x001
#define TIOCM_DTR 0x002
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCM_RTS 0x004
#define TIOCM_ST 0x010
#define TIOCM_SR 0x020
#define TIOCM_CTS 0x040
#define TIOCM_RTS 0x004
#define TIOCM_ST 0x010
#define TIOCM_SR 0x020
#define TIOCM_CTS 0x040
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCM_CAR 0x100
#define TIOCM_CAR 0x100
#define TIOCM_CD TIOCM_CAR
#define TIOCM_RNG 0x200
#define TIOCM_RNG 0x200
#define TIOCM_RI TIOCM_RNG
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCM_DSR 0x400
#define TIOCM_DSR 0x400
#define TIOCM_OUT1 0x2000
#define TIOCM_OUT2 0x4000
#define TIOCM_LOOP 0x8000

2
libc/kernel/arch-mips/asm/unistd.h
View File

@ -193,7 +193,7 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __NR_sysfs (__NR_Linux + 135)
#define __NR_personality (__NR_Linux + 136)
#define __NR_afs_syscall (__NR_Linux + 137)
#define __NR_afs_syscall (__NR_Linux + 137)
#define __NR_setfsuid (__NR_Linux + 138)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define __NR_setfsgid (__NR_Linux + 139)

4
libc/kernel/arch-mips/asm/vr41xx/irq.h
View File

@ -59,7 +59,7 @@
#define HSP_IRQ SYSINT2_IRQ(2)
#define TCLOCK_IRQ SYSINT2_IRQ(3)
#define FIR_IRQ SYSINT2_IRQ(4)
#define CEU_IRQ SYSINT2_IRQ(4)
#define CEU_IRQ SYSINT2_IRQ(4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DSIU_IRQ SYSINT2_IRQ(5)
#define PCI_IRQ SYSINT2_IRQ(6)
@ -71,7 +71,7 @@
#define SYSINT2_IRQ_LAST ETHERNET_IRQ
#define GIU_IRQ_BASE 40
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define GIU_IRQ(x) (GIU_IRQ_BASE + (x))
#define GIU_IRQ(x) (GIU_IRQ_BASE + (x))
#define GIU_IRQ_LAST GIU_IRQ(31)
#define VRC4173_IRQ_BASE 72
#define VRC4173_IRQ(x) (VRC4173_IRQ_BASE + (x))

4
libc/kernel/arch-x86/asm/apicdef_32.h
View File

@ -36,7 +36,7 @@
#define APIC_PROCPRI 0xA0
#define APIC_EOI 0xB0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define APIC_EIO_ACK 0x0
#define APIC_EIO_ACK 0x0
#define APIC_RRR 0xC0
#define APIC_LDR 0xD0
#define APIC_LDR_MASK (0xFF<<24)
@ -53,7 +53,7 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define APIC_SPIV_APIC_ENABLED (1<<8)
#define APIC_ISR 0x100
#define APIC_ISR_NR 0x8
#define APIC_ISR_NR 0x8
#define APIC_TMR 0x180
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define APIC_IRR 0x200

2
libc/kernel/arch-x86/asm/cmpxchg_32.h
View File

@ -18,7 +18,7 @@
****************************************************************************/
#ifndef __ASM_CMPXCHG_H
#define __ASM_CMPXCHG_H
#include <linux/bitops.h>
#include <linux/bitops.h>
#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct __xchg_dummy { unsigned long a[100]; };

158
libc/kernel/arch-x86/asm/cpufeature_32.h
View File

@ -23,105 +23,105 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif
#include <asm/required-features.h>
#define NCAPINTS 8
#define X86_FEATURE_FPU (0*32+ 0)
#define NCAPINTS 8
#define X86_FEATURE_FPU (0*32+ 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_VME (0*32+ 1)
#define X86_FEATURE_DE (0*32+ 2)
#define X86_FEATURE_PSE (0*32+ 3)
#define X86_FEATURE_TSC (0*32+ 4)
#define X86_FEATURE_VME (0*32+ 1)
#define X86_FEATURE_DE (0*32+ 2)
#define X86_FEATURE_PSE (0*32+ 3)
#define X86_FEATURE_TSC (0*32+ 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_MSR (0*32+ 5)
#define X86_FEATURE_PAE (0*32+ 6)
#define X86_FEATURE_MCE (0*32+ 7)
#define X86_FEATURE_CX8 (0*32+ 8)
#define X86_FEATURE_MSR (0*32+ 5)
#define X86_FEATURE_PAE (0*32+ 6)
#define X86_FEATURE_MCE (0*32+ 7)
#define X86_FEATURE_CX8 (0*32+ 8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_APIC (0*32+ 9)
#define X86_FEATURE_SEP (0*32+11)
#define X86_FEATURE_MTRR (0*32+12)
#define X86_FEATURE_PGE (0*32+13)
#define X86_FEATURE_APIC (0*32+ 9)
#define X86_FEATURE_SEP (0*32+11)
#define X86_FEATURE_MTRR (0*32+12)
#define X86_FEATURE_PGE (0*32+13)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_MCA (0*32+14)
#define X86_FEATURE_CMOV (0*32+15)
#define X86_FEATURE_PAT (0*32+16)
#define X86_FEATURE_PSE36 (0*32+17)
#define X86_FEATURE_MCA (0*32+14)
#define X86_FEATURE_CMOV (0*32+15)
#define X86_FEATURE_PAT (0*32+16)
#define X86_FEATURE_PSE36 (0*32+17)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_PN (0*32+18)
#define X86_FEATURE_CLFLSH (0*32+19)
#define X86_FEATURE_DS (0*32+21)
#define X86_FEATURE_ACPI (0*32+22)
#define X86_FEATURE_PN (0*32+18)
#define X86_FEATURE_CLFLSH (0*32+19)
#define X86_FEATURE_DS (0*32+21)
#define X86_FEATURE_ACPI (0*32+22)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_MMX (0*32+23)
#define X86_FEATURE_FXSR (0*32+24)
#define X86_FEATURE_XMM (0*32+25)
#define X86_FEATURE_XMM2 (0*32+26)
#define X86_FEATURE_MMX (0*32+23)
#define X86_FEATURE_FXSR (0*32+24)
#define X86_FEATURE_XMM (0*32+25)
#define X86_FEATURE_XMM2 (0*32+26)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_SELFSNOOP (0*32+27)
#define X86_FEATURE_HT (0*32+28)
#define X86_FEATURE_ACC (0*32+29)
#define X86_FEATURE_IA64 (0*32+30)
#define X86_FEATURE_SELFSNOOP (0*32+27)
#define X86_FEATURE_HT (0*32+28)
#define X86_FEATURE_ACC (0*32+29)
#define X86_FEATURE_IA64 (0*32+30)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_SYSCALL (1*32+11)
#define X86_FEATURE_MP (1*32+19)
#define X86_FEATURE_NX (1*32+20)
#define X86_FEATURE_MMXEXT (1*32+22)
#define X86_FEATURE_SYSCALL (1*32+11)
#define X86_FEATURE_MP (1*32+19)
#define X86_FEATURE_NX (1*32+20)
#define X86_FEATURE_MMXEXT (1*32+22)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_RDTSCP (1*32+27)
#define X86_FEATURE_LM (1*32+29)
#define X86_FEATURE_3DNOWEXT (1*32+30)
#define X86_FEATURE_3DNOW (1*32+31)
#define X86_FEATURE_RDTSCP (1*32+27)
#define X86_FEATURE_LM (1*32+29)
#define X86_FEATURE_3DNOWEXT (1*32+30)
#define X86_FEATURE_3DNOW (1*32+31)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_RECOVERY (2*32+ 0)
#define X86_FEATURE_LONGRUN (2*32+ 1)
#define X86_FEATURE_LRTI (2*32+ 3)
#define X86_FEATURE_CXMMX (3*32+ 0)
#define X86_FEATURE_RECOVERY (2*32+ 0)
#define X86_FEATURE_LONGRUN (2*32+ 1)
#define X86_FEATURE_LRTI (2*32+ 3)
#define X86_FEATURE_CXMMX (3*32+ 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_K6_MTRR (3*32+ 1)
#define X86_FEATURE_CYRIX_ARR (3*32+ 2)
#define X86_FEATURE_CENTAUR_MCR (3*32+ 3)
#define X86_FEATURE_K8 (3*32+ 4)
#define X86_FEATURE_K6_MTRR (3*32+ 1)
#define X86_FEATURE_CYRIX_ARR (3*32+ 2)
#define X86_FEATURE_CENTAUR_MCR (3*32+ 3)
#define X86_FEATURE_K8 (3*32+ 4)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_K7 (3*32+ 5)
#define X86_FEATURE_P3 (3*32+ 6)
#define X86_FEATURE_P4 (3*32+ 7)
#define X86_FEATURE_CONSTANT_TSC (3*32+ 8)
#define X86_FEATURE_K7 (3*32+ 5)
#define X86_FEATURE_P3 (3*32+ 6)
#define X86_FEATURE_P4 (3*32+ 7)
#define X86_FEATURE_CONSTANT_TSC (3*32+ 8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_UP (3*32+ 9)
#define X86_FEATURE_FXSAVE_LEAK (3*32+10)
#define X86_FEATURE_ARCH_PERFMON (3*32+11)
#define X86_FEATURE_PEBS (3*32+12)
#define X86_FEATURE_UP (3*32+ 9)
#define X86_FEATURE_FXSAVE_LEAK (3*32+10)
#define X86_FEATURE_ARCH_PERFMON (3*32+11)
#define X86_FEATURE_PEBS (3*32+12)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_BTS (3*32+13)
#define X86_FEATURE_SYNC_RDTSC (3*32+15)
#define X86_FEATURE_REP_GOOD (3*32+16)
#define X86_FEATURE_XMM3 (4*32+ 0)
#define X86_FEATURE_BTS (3*32+13)
#define X86_FEATURE_SYNC_RDTSC (3*32+15)
#define X86_FEATURE_REP_GOOD (3*32+16)
#define X86_FEATURE_XMM3 (4*32+ 0)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_MWAIT (4*32+ 3)
#define X86_FEATURE_DSCPL (4*32+ 4)
#define X86_FEATURE_EST (4*32+ 7)
#define X86_FEATURE_TM2 (4*32+ 8)
#define X86_FEATURE_MWAIT (4*32+ 3)
#define X86_FEATURE_DSCPL (4*32+ 4)
#define X86_FEATURE_EST (4*32+ 7)
#define X86_FEATURE_TM2 (4*32+ 8)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_CID (4*32+10)
#define X86_FEATURE_CX16 (4*32+13)
#define X86_FEATURE_XTPR (4*32+14)
#define X86_FEATURE_DCA (4*32+18)
#define X86_FEATURE_CID (4*32+10)
#define X86_FEATURE_CX16 (4*32+13)
#define X86_FEATURE_XTPR (4*32+14)
#define X86_FEATURE_DCA (4*32+18)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_XSTORE (5*32+ 2)
#define X86_FEATURE_XSTORE_EN (5*32+ 3)
#define X86_FEATURE_XCRYPT (5*32+ 6)
#define X86_FEATURE_XCRYPT_EN (5*32+ 7)
#define X86_FEATURE_XSTORE (5*32+ 2)
#define X86_FEATURE_XSTORE_EN (5*32+ 3)
#define X86_FEATURE_XCRYPT (5*32+ 6)
#define X86_FEATURE_XCRYPT_EN (5*32+ 7)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_ACE2 (5*32+ 8)
#define X86_FEATURE_ACE2_EN (5*32+ 9)
#define X86_FEATURE_PHE (5*32+ 10)
#define X86_FEATURE_PHE_EN (5*32+ 11)
#define X86_FEATURE_ACE2 (5*32+ 8)
#define X86_FEATURE_ACE2_EN (5*32+ 9)
#define X86_FEATURE_PHE (5*32+ 10)
#define X86_FEATURE_PHE_EN (5*32+ 11)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_PMM (5*32+ 12)
#define X86_FEATURE_PMM_EN (5*32+ 13)
#define X86_FEATURE_LAHF_LM (6*32+ 0)
#define X86_FEATURE_CMP_LEGACY (6*32+ 1)
#define X86_FEATURE_PMM (5*32+ 12)
#define X86_FEATURE_PMM_EN (5*32+ 13)
#define X86_FEATURE_LAHF_LM (6*32+ 0)
#define X86_FEATURE_CMP_LEGACY (6*32+ 1)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_FEATURE_IDA (7*32+ 0)
#define X86_FEATURE_IDA (7*32+ 0)
#define cpu_has(c, bit) (__builtin_constant_p(bit) && ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) ? 1 : test_bit(bit, (c)->x86_capability))
#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)

14
libc/kernel/arch-x86/asm/desc_32.h
View File

@ -38,15 +38,15 @@ struct gdt_page
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
struct desc_struct gdt[GDT_ENTRIES];
} __attribute__((aligned(PAGE_SIZE)));
#define DESCTYPE_LDT 0x82
#define DESCTYPE_TSS 0x89
#define DESCTYPE_LDT 0x82
#define DESCTYPE_TSS 0x89
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DESCTYPE_TASK 0x85
#define DESCTYPE_INT 0x8e
#define DESCTYPE_TRAP 0x8f
#define DESCTYPE_DPL3 0x60
#define DESCTYPE_TASK 0x85
#define DESCTYPE_INT 0x8e
#define DESCTYPE_TRAP 0x8f
#define DESCTYPE_DPL3 0x60
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DESCTYPE_S 0x10
#define DESCTYPE_S 0x10
#define load_TR_desc() native_load_tr_desc()
#define load_gdt(dtr) native_load_gdt(dtr)
#define load_idt(dtr) native_load_idt(dtr)

60
libc/kernel/arch-x86/asm/dma_32.h
View File

@ -18,8 +18,8 @@
****************************************************************************/
#ifndef _ASM_DMA_H
#define _ASM_DMA_H
#include <linux/spinlock.h>
#include <asm/io.h>
#include <linux/spinlock.h>
#include <asm/io.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#include <linux/delay.h>
#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
@ -32,34 +32,34 @@
#define MAX_DMA_CHANNELS 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000)
#define IO_DMA1_BASE 0x00
#define IO_DMA2_BASE 0xC0
#define DMA1_CMD_REG 0x08
#define IO_DMA1_BASE 0x00
#define IO_DMA2_BASE 0xC0
#define DMA1_CMD_REG 0x08
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA1_STAT_REG 0x08
#define DMA1_REQ_REG 0x09
#define DMA1_MASK_REG 0x0A
#define DMA1_MODE_REG 0x0B
#define DMA1_STAT_REG 0x08
#define DMA1_REQ_REG 0x09
#define DMA1_MASK_REG 0x0A
#define DMA1_MODE_REG 0x0B
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA1_CLEAR_FF_REG 0x0C
#define DMA1_TEMP_REG 0x0D
#define DMA1_RESET_REG 0x0D
#define DMA1_CLR_MASK_REG 0x0E
#define DMA1_CLEAR_FF_REG 0x0C
#define DMA1_TEMP_REG 0x0D
#define DMA1_RESET_REG 0x0D
#define DMA1_CLR_MASK_REG 0x0E
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA1_MASK_ALL_REG 0x0F
#define DMA2_CMD_REG 0xD0
#define DMA2_STAT_REG 0xD0
#define DMA2_REQ_REG 0xD2
#define DMA1_MASK_ALL_REG 0x0F
#define DMA2_CMD_REG 0xD0
#define DMA2_STAT_REG 0xD0
#define DMA2_REQ_REG 0xD2
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA2_MASK_REG 0xD4
#define DMA2_MODE_REG 0xD6
#define DMA2_CLEAR_FF_REG 0xD8
#define DMA2_TEMP_REG 0xDA
#define DMA2_MASK_REG 0xD4
#define DMA2_MODE_REG 0xD6
#define DMA2_CLEAR_FF_REG 0xD8
#define DMA2_TEMP_REG 0xDA
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA2_RESET_REG 0xDA
#define DMA2_CLR_MASK_REG 0xDC
#define DMA2_MASK_ALL_REG 0xDE
#define DMA_ADDR_0 0x00
#define DMA2_RESET_REG 0xDA
#define DMA2_CLR_MASK_REG 0xDC
#define DMA2_MASK_ALL_REG 0xDE
#define DMA_ADDR_0 0x00
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_ADDR_1 0x02
#define DMA_ADDR_2 0x04
@ -69,7 +69,7 @@
#define DMA_ADDR_5 0xC4
#define DMA_ADDR_6 0xC8
#define DMA_ADDR_7 0xCC
#define DMA_CNT_0 0x01
#define DMA_CNT_0 0x01
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_CNT_1 0x03
#define DMA_CNT_2 0x05
@ -79,7 +79,7 @@
#define DMA_CNT_5 0xC6
#define DMA_CNT_6 0xCA
#define DMA_CNT_7 0xCE
#define DMA_PAGE_0 0x87
#define DMA_PAGE_0 0x87
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_PAGE_1 0x83
#define DMA_PAGE_2 0x81
@ -88,10 +88,10 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_PAGE_6 0x89
#define DMA_PAGE_7 0x8A
#define DMA_MODE_READ 0x44
#define DMA_MODE_WRITE 0x48
#define DMA_MODE_READ 0x44
#define DMA_MODE_WRITE 0x48
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define DMA_MODE_CASCADE 0xC0
#define DMA_MODE_CASCADE 0xC0
#define DMA_AUTOINIT 0x10
#define isa_dma_bridge_buggy (0)
#endif

6
libc/kernel/arch-x86/asm/e820.h
View File

@ -18,10 +18,10 @@
****************************************************************************/
#ifndef __ASM_E820_H
#define __ASM_E820_H
#define E820MAP 0x2d0
#define E820MAX 128
#define E820MAP 0x2d0
#define E820MAX 128
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define E820NR 0x1e8
#define E820NR 0x1e8
#define E820_RAM 1
#define E820_RESERVED 2
#define E820_ACPI 3

2
libc/kernel/arch-x86/asm/io_32.h
View File

@ -23,7 +23,7 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define IO_SPACE_LIMIT 0xffff
#define XQUAD_PORTIO_BASE 0xfe400000
#define XQUAD_PORTIO_QUAD 0x40000
#define XQUAD_PORTIO_QUAD 0x40000
#ifdef REALLY_SLOW_IO
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#endif

32
libc/kernel/arch-x86/asm/ioctls.h
View File

@ -21,7 +21,7 @@
#include <asm/ioctl.h>
#define TCGETS 0x5401
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSETS 0x5402
#define TCSETS 0x5402
#define TCSETSW 0x5403
#define TCSETSF 0x5404
#define TCGETA 0x5405
@ -66,18 +66,18 @@
#define TIOCSETD 0x5423
#define TIOCGETD 0x5424
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCSBRKP 0x5425
#define TIOCSBRK 0x5427
#define TIOCCBRK 0x5428
#define TIOCGSID 0x5429
#define TCSBRKP 0x5425
#define TIOCSBRK 0x5427
#define TIOCCBRK 0x5428
#define TIOCGSID 0x5429
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TCGETS2 _IOR('T',0x2A, struct termios2)
#define TCSETS2 _IOW('T',0x2B, struct termios2)
#define TCSETSW2 _IOW('T',0x2C, struct termios2)
#define TCSETSF2 _IOW('T',0x2D, struct termios2)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGPTN _IOR('T',0x30, unsigned int)
#define TIOCSPTLCK _IOW('T',0x31, int)
#define TIOCGPTN _IOR('T',0x30, unsigned int)
#define TIOCSPTLCK _IOW('T',0x31, int)
#define FIONCLEX 0x5450
#define FIOCLEX 0x5451
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -88,16 +88,16 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGLCKTRMIOS 0x5456
#define TIOCSLCKTRMIOS 0x5457
#define TIOCSERGSTRUCT 0x5458
#define TIOCSERGETLSR 0x5459
#define TIOCSERGSTRUCT 0x5458
#define TIOCSERGETLSR 0x5459
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCSERGETMULTI 0x545A
#define TIOCSERSETMULTI 0x545B
#define TIOCMIWAIT 0x545C
#define TIOCGICOUNT 0x545D
#define TIOCSERGETMULTI 0x545A
#define TIOCSERSETMULTI 0x545B
#define TIOCMIWAIT 0x545C
#define TIOCGICOUNT 0x545D
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCGHAYESESP 0x545E
#define TIOCSHAYESESP 0x545F
#define TIOCGHAYESESP 0x545E
#define TIOCSHAYESESP 0x545F
#define FIOQSIZE 0x5460
#define TIOCPKT_DATA 0
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -108,6 +108,6 @@
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define TIOCPKT_NOSTOP 16
#define TIOCPKT_DOSTOP 32
#define TIOCSER_TEMT 0x01
#define TIOCSER_TEMT 0x01
#endif
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

2
libc/kernel/arch-x86/asm/local_32.h
View File

@ -44,7 +44,7 @@ typedef struct
#define __local_add(i,l) local_add((i),(l))
#define __local_sub(i,l) local_sub((i),(l))
#define cpu_local_wrap_v(l) ({ local_t res__; preempt_disable(); res__ = (l); preempt_enable(); res__; })
#define cpu_local_wrap(l) ({ preempt_disable(); l; preempt_enable(); })
#define cpu_local_wrap(l) ({ preempt_disable(); l; preempt_enable(); })
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define cpu_local_read(l) cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
#define cpu_local_set(l, i) cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))

2
libc/kernel/arch-x86/asm/mc146818rtc_32.h
View File

@ -26,7 +26,7 @@
#ifndef RTC_PORT
#define RTC_PORT(x) (0x70 + (x))
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define RTC_ALWAYS_BCD 1
#define RTC_ALWAYS_BCD 1
#endif
#ifdef __HAVE_ARCH_CMPXCHG
#include <linux/smp.h>

20
libc/kernel/arch-x86/asm/mman.h
View File

@ -19,17 +19,17 @@
#ifndef _ASM_X86_MMAN_H
#define _ASM_X86_MMAN_H
#include <asm-generic/mman.h>
#define MAP_32BIT 0x40
#define MAP_32BIT 0x40
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAP_GROWSDOWN 0x0100
#define MAP_DENYWRITE 0x0800
#define MAP_EXECUTABLE 0x1000
#define MAP_LOCKED 0x2000
#define MAP_GROWSDOWN 0x0100
#define MAP_DENYWRITE 0x0800
#define MAP_EXECUTABLE 0x1000
#define MAP_LOCKED 0x2000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MAP_NORESERVE 0x4000
#define MAP_POPULATE 0x8000
#define MAP_NONBLOCK 0x10000
#define MCL_CURRENT 1
#define MAP_NORESERVE 0x4000
#define MAP_POPULATE 0x8000
#define MAP_NONBLOCK 0x10000
#define MCL_CURRENT 1
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MCL_FUTURE 2
#define MCL_FUTURE 2
#endif

10
libc/kernel/arch-x86/asm/mpspec_def.h
View File

@ -63,7 +63,7 @@ struct mp_config_table
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MP_INTSRC 3
#define MP_LINTSRC 4
#define MP_TRANSLATION 192
#define MP_TRANSLATION 192
struct mpc_config_processor
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
{
@ -72,8 +72,8 @@ struct mpc_config_processor
unsigned char mpc_apicver;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
unsigned char mpc_cpuflag;
#define CPU_ENABLED 1
#define CPU_BOOTPROCESSOR 2
#define CPU_ENABLED 1
#define CPU_BOOTPROCESSOR 2
unsigned long mpc_cpufeature;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define CPU_STEPPING_MASK 0x0F
@ -93,10 +93,10 @@ struct mpc_config_bus
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BUSTYPE_EISA "EISA"
#define BUSTYPE_ISA "ISA"
#define BUSTYPE_INTERN "INTERN"
#define BUSTYPE_INTERN "INTERN"
#define BUSTYPE_MCA "MCA"
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define BUSTYPE_VL "VL"
#define BUSTYPE_VL "VL"
#define BUSTYPE_PCI "PCI"
#define BUSTYPE_PCMCIA "PCMCIA"
#define BUSTYPE_CBUS "CBUS"

32
libc/kernel/arch-x86/asm/msr-index.h
View File

@ -18,21 +18,21 @@
****************************************************************************/
#ifndef __ASM_MSR_INDEX_H
#define __ASM_MSR_INDEX_H
#define MSR_EFER 0xc0000080
#define MSR_STAR 0xc0000081
#define MSR_EFER 0xc0000080
#define MSR_STAR 0xc0000081
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_LSTAR 0xc0000082
#define MSR_CSTAR 0xc0000083
#define MSR_SYSCALL_MASK 0xc0000084
#define MSR_FS_BASE 0xc0000100
#define MSR_LSTAR 0xc0000082
#define MSR_CSTAR 0xc0000083
#define MSR_SYSCALL_MASK 0xc0000084
#define MSR_FS_BASE 0xc0000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_GS_BASE 0xc0000101
#define MSR_KERNEL_GS_BASE 0xc0000102
#define _EFER_SCE 0
#define _EFER_LME 8
#define MSR_GS_BASE 0xc0000101
#define MSR_KERNEL_GS_BASE 0xc0000102
#define _EFER_SCE 0
#define _EFER_LME 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _EFER_LMA 10
#define _EFER_NX 11
#define _EFER_LMA 10
#define _EFER_NX 11
#define EFER_SCE (1<<_EFER_SCE)
#define EFER_LME (1<<_EFER_LME)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
@ -107,9 +107,9 @@
#define MSR_K8_HWCR 0xc0010015
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_K8_ENABLE_C1E 0xc0010055
#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000
#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000
#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818
#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000
#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000
#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_K7_EVNTSEL0 0xc0010000
#define MSR_K7_PERFCTR0 0xc0010004
@ -294,7 +294,7 @@
#define MSR_P4_SAAT_ESCR0 0x000003ae
#define MSR_P4_SAAT_ESCR1 0x000003af
#define MSR_P4_SSU_ESCR0 0x000003be
#define MSR_P4_SSU_ESCR1 0x000003bf
#define MSR_P4_SSU_ESCR1 0x000003bf
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define MSR_P4_TBPU_ESCR0 0x000003c2
#define MSR_P4_TBPU_ESCR1 0x000003c3

2
libc/kernel/arch-x86/asm/pgalloc_32.h
View File

@ -19,7 +19,7 @@
#ifndef _I386_PGALLOC_H
#define _I386_PGALLOC_H
#include <linux/threads.h>
#include <linux/mm.h>
#include <linux/mm.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define paravirt_alloc_pt(mm, pfn) do { } while (0)
#define paravirt_alloc_pd(pfn) do { } while (0)

16
libc/kernel/arch-x86/asm/pgtable_32.h
View File

@ -58,10 +58,10 @@ struct vm_area_struct;
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _PAGE_BIT_ACCESSED 5
#define _PAGE_BIT_DIRTY 6
#define _PAGE_BIT_PSE 7
#define _PAGE_BIT_GLOBAL 8
#define _PAGE_BIT_PSE 7
#define _PAGE_BIT_GLOBAL 8
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _PAGE_BIT_UNUSED1 9
#define _PAGE_BIT_UNUSED1 9
#define _PAGE_BIT_UNUSED2 10
#define _PAGE_BIT_UNUSED3 11
#define _PAGE_BIT_NX 63
@ -74,15 +74,15 @@ struct vm_area_struct;
#define _PAGE_PCD 0x010
#define _PAGE_ACCESSED 0x020
#define _PAGE_DIRTY 0x040
#define _PAGE_PSE 0x080
#define _PAGE_PSE 0x080
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _PAGE_GLOBAL 0x100
#define _PAGE_UNUSED1 0x200
#define _PAGE_GLOBAL 0x100
#define _PAGE_UNUSED1 0x200
#define _PAGE_UNUSED2 0x400
#define _PAGE_UNUSED3 0x800
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define _PAGE_FILE 0x040
#define _PAGE_PROTNONE 0x080
#define _PAGE_FILE 0x040
#define _PAGE_PROTNONE 0x080
#define _PAGE_NX 0
#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

86
libc/kernel/arch-x86/asm/processor-flags.h
View File

@ -18,60 +18,60 @@
****************************************************************************/
#ifndef __ASM_I386_PROCESSOR_FLAGS_H
#define __ASM_I386_PROCESSOR_FLAGS_H
#define X86_EFLAGS_CF 0x00000001
#define X86_EFLAGS_PF 0x00000004
#define X86_EFLAGS_CF 0x00000001
#define X86_EFLAGS_PF 0x00000004
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_EFLAGS_AF 0x00000010
#define X86_EFLAGS_ZF 0x00000040
#define X86_EFLAGS_SF 0x00000080
#define X86_EFLAGS_TF 0x00000100
#define X86_EFLAGS_AF 0x00000010
#define X86_EFLAGS_ZF 0x00000040
#define X86_EFLAGS_SF 0x00000080
#define X86_EFLAGS_TF 0x00000100
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_EFLAGS_IF 0x00000200
#define X86_EFLAGS_DF 0x00000400
#define X86_EFLAGS_OF 0x00000800
#define X86_EFLAGS_IOPL 0x00003000
#define X86_EFLAGS_IF 0x00000200
#define X86_EFLAGS_DF 0x00000400
#define X86_EFLAGS_OF 0x00000800
#define X86_EFLAGS_IOPL 0x00003000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_EFLAGS_NT 0x00004000
#define X86_EFLAGS_RF 0x00010000
#define X86_EFLAGS_VM 0x00020000
#define X86_EFLAGS_AC 0x00040000
#define X86_EFLAGS_NT 0x00004000
#define X86_EFLAGS_RF 0x00010000
#define X86_EFLAGS_VM 0x00020000
#define X86_EFLAGS_AC 0x00040000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_EFLAGS_VIF 0x00080000
#define X86_EFLAGS_VIP 0x00100000
#define X86_EFLAGS_ID 0x00200000
#define X86_CR0_PE 0x00000001
#define X86_EFLAGS_VIF 0x00080000
#define X86_EFLAGS_VIP 0x00100000
#define X86_EFLAGS_ID 0x00200000
#define X86_CR0_PE 0x00000001
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_CR0_MP 0x00000002
#define X86_CR0_EM 0x00000004
#define X86_CR0_TS 0x00000008
#define X86_CR0_ET 0x00000010
#define X86_CR0_MP 0x00000002
#define X86_CR0_EM 0x00000004
#define X86_CR0_TS 0x00000008
#define X86_CR0_ET 0x00000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_CR0_NE 0x00000020
#define X86_CR0_WP 0x00010000
#define X86_CR0_AM 0x00040000
#define X86_CR0_NW 0x20000000
#define X86_CR0_NE 0x00000020
#define X86_CR0_WP 0x00010000
#define X86_CR0_AM 0x00040000
#define X86_CR0_NW 0x20000000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_CR0_CD 0x40000000
#define X86_CR0_PG 0x80000000
#define X86_CR3_PWT 0x00000008
#define X86_CR3_PCD 0x00000010
#define X86_CR0_CD 0x40000000
#define X86_CR0_PG 0x80000000
#define X86_CR3_PWT 0x00000008
#define X86_CR3_PCD 0x00000010
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_CR4_VME 0x00000001
#define X86_CR4_PVI 0x00000002
#define X86_CR4_TSD 0x00000004
#define X86_CR4_DE 0x00000008
#define X86_CR4_VME 0x00000001
#define X86_CR4_PVI 0x00000002
#define X86_CR4_TSD 0x00000004
#define X86_CR4_DE 0x00000008
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_CR4_PSE 0x00000010
#define X86_CR4_PAE 0x00000020
#define X86_CR4_MCE 0x00000040
#define X86_CR4_PGE 0x00000080
#define X86_CR4_PSE 0x00000010
#define X86_CR4_PAE 0x00000020
#define X86_CR4_MCE 0x00000040
#define X86_CR4_PGE 0x00000080
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_CR4_PCE 0x00000100
#define X86_CR4_OSFXSR 0x00000200
#define X86_CR4_OSXMMEXCPT 0x00000400
#define X86_CR4_VMXE 0x00002000
#define X86_CR4_PCE 0x00000100
#define X86_CR4_OSFXSR 0x00000200
#define X86_CR4_OSXMMEXCPT 0x00000400
#define X86_CR4_VMXE 0x00002000
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define X86_CR8_TPR 0x0000000F
#define X86_CR8_TPR 0x0000000F
#define CX86_PCR0 0x20
#define CX86_GCR 0xb8
#define CX86_CCR0 0xc0

10
libc/kernel/arch-x86/asm/processor_32.h
View File

@ -297,17 +297,17 @@ struct extended_sigtable {
#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K8_NOP1 GENERIC_NOP1
#define K8_NOP2 ".byte 0x66,0x90\n"
#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
#define K8_NOP2 ".byte 0x66,0x90\n"
#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K8_NOP5 K8_NOP3 K8_NOP2
#define K8_NOP5 K8_NOP3 K8_NOP2
#define K8_NOP6 K8_NOP3 K8_NOP3
#define K8_NOP7 K8_NOP4 K8_NOP3
#define K8_NOP8 K8_NOP4 K8_NOP4
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#define K7_NOP1 GENERIC_NOP1
#define K7_NOP2 ".byte 0x8b,0xc0\n"
#define K7_NOP2 ".byte 0x8b,0xc0\n"
#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */

2
libc/kernel/arch-x86/asm/ptrace.h
View File

@ -18,7 +18,7 @@
****************************************************************************/
#ifndef _ASM_X86_PTRACE_H
#define _ASM_X86_PTRACE_H
#include <linux/compiler.h>
#include <linux/compiler.h>
#include <asm/ptrace-abi.h>
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
#ifndef __ASSEMBLY__

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