am 26c5b2d4: Merge "[MIPS] Rewrite fenv.h for Android"
* commit '26c5b2d460e3b2595eb7f0605edcd02753a13594': [MIPS] Rewrite fenv.h for Android
This commit is contained in:
Elliott Hughes
Android Git Automerger
commit
2458d06fc1
@ -26,193 +26,200 @@
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* $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $
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*/
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#ifndef _FENV_H_
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#define _FENV_H_
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/*
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Rewritten for Android.
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*/
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/* MIPS FPU floating point control register bits.
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*
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* 31-25 -> floating point conditions code bits set by FP compare
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* instructions
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* 24 -> flush denormalized results to zero instead of
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* causing unimplemented operation exception.
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* 23 -> Condition bit
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* 22 -> In conjunction with FS detects denormalized
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* operands and replaces them internally with 0.
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* 21 -> In conjunction with FS forces denormalized operands
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* to the closest normalized value.
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* 20-18 -> reserved (read as 0, write with 0)
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* 17 -> cause bit for unimplemented operation
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* 16 -> cause bit for invalid exception
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* 15 -> cause bit for division by zero exception
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* 14 -> cause bit for overflow exception
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* 13 -> cause bit for underflow exception
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* 12 -> cause bit for inexact exception
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* 11 -> enable exception for invalid exception
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* 10 -> enable exception for division by zero exception
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* 9 -> enable exception for overflow exception
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* 8 -> enable exception for underflow exception
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* 7 -> enable exception for inexact exception
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* 6 -> flag invalid exception
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* 5 -> flag division by zero exception
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* 4 -> flag overflow exception
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* 3 -> flag underflow exception
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* 2 -> flag inexact exception
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* 1-0 -> rounding control
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*
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*
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* Rounding Control:
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* 00 - rounding to nearest (RN)
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* 01 - rounding toward zero (RZ)
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* 10 - rounding (up) toward plus infinity (RP)
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* 11 - rounding (down)toward minus infinity (RM)
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*/
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#ifndef _FENV_H_
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#define _FENV_H_
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#include <sys/types.h>
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__BEGIN_DECLS
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typedef __uint32_t fenv_t;
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typedef __uint32_t fexcept_t;
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typedef __uint32_t fenv_t;
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typedef __uint32_t fexcept_t;
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/* Exception flags */
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#define FE_INVALID 0x0001
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#define FE_DIVBYZERO 0x0002
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#define FE_OVERFLOW 0x0004
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#define FE_UNDERFLOW 0x0008
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#define FE_INEXACT 0x0010
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#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
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FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
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#define FE_INVALID 0x40
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#define FE_DIVBYZERO 0x20
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#define FE_OVERFLOW 0x10
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#define FE_UNDERFLOW 0x08
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#define FE_INEXACT 0x04
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#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
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FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
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#define _FCSR_CAUSE_SHIFT 10
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#define _ENABLE_SHIFT 5
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#define _FCSR_ENABLE_MASK (FE_ALL_EXCEPT << _ENABLE_SHIFT)
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/* Rounding modes */
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#define FE_TONEAREST 0x0000
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#define FE_TOWARDZERO 0x0001
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#define FE_UPWARD 0x0002
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#define FE_DOWNWARD 0x0003
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#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
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FE_UPWARD | FE_TOWARDZERO)
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#define FE_TONEAREST 0x0000
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#define FE_TOWARDZERO 0x0001
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#define FE_UPWARD 0x0002
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#define FE_DOWNWARD 0x0003
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#define _FCSR_RMODE_SHIFT 0
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#define _FCSR_RMASK 0x3
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/* Default floating-point environment */
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extern const fenv_t __fe_dfl_env;
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#define FE_DFL_ENV (&__fe_dfl_env)
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extern const fenv_t __fe_dfl_env;
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#define FE_DFL_ENV (&__fe_dfl_env)
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/* We need to be able to map status flag positions to mask flag positions */
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#define _FPUSW_SHIFT 16
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#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
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#ifdef ARM_HARD_FLOAT
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#define __rfs(__fpsr) __asm __volatile("rfs %0" : "=r" (*(__fpsr)))
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#define __wfs(__fpsr) __asm __volatile("wfs %0" : : "r" (__fpsr))
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#else
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#define __rfs(__fpsr)
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#define __wfs(__fpsr)
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static __inline int fegetenv(fenv_t* __envp) {
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fenv_t _fcsr = 0;
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#ifdef __mips_hard_float
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__asm__ __volatile__("cfc1 %0,$31" : "=r" (_fcsr));
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#endif
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static __inline int
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feclearexcept(int __excepts)
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{
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fexcept_t __fpsr;
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__rfs(&__fpsr);
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__fpsr &= ~__excepts;
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__wfs(__fpsr);
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return (0);
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*__envp = _fcsr;
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return 0;
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}
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static __inline int
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fegetexceptflag(fexcept_t *__flagp, int __excepts)
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{
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fexcept_t __fpsr;
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__rfs(&__fpsr);
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*__flagp = __fpsr & __excepts;
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return (0);
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static __inline int fesetenv(const fenv_t* __envp) {
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fenv_t _fcsr = *__envp;
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#ifdef __mips_hard_float
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__asm__ __volatile__("ctc1 %0,$31" : : "r" (_fcsr));
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#endif
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return 0;
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}
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static __inline int
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fesetexceptflag(const fexcept_t *__flagp, int __excepts)
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{
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fexcept_t __fpsr;
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__rfs(&__fpsr);
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__fpsr &= ~__excepts;
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__fpsr |= *__flagp & __excepts;
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__wfs(__fpsr);
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return (0);
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static __inline int feclearexcept(int __excepts) {
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fexcept_t __fcsr;
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fegetenv(&__fcsr);
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__excepts &= FE_ALL_EXCEPT;
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__fcsr &= ~(__excepts | (__excepts << _FCSR_CAUSE_SHIFT));
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fesetenv(&__fcsr);
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return 0;
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}
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static __inline int
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feraiseexcept(int __excepts)
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{
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fexcept_t __ex = __excepts;
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fesetexceptflag(&__ex, __excepts); /* XXX */
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return (0);
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static __inline int fegetexceptflag(fexcept_t* __flagp, int __excepts) {
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fexcept_t __fcsr;
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fegetenv(&__fcsr);
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*__flagp = __fcsr & __excepts & FE_ALL_EXCEPT;
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return 0;
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}
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static __inline int
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fetestexcept(int __excepts)
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{
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fexcept_t __fpsr;
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__rfs(&__fpsr);
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return (__fpsr & __excepts);
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static __inline int fesetexceptflag(const fexcept_t* __flagp, int __excepts) {
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fexcept_t __fcsr;
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fegetenv(&__fcsr);
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/* Ensure that flags are all legal */
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__excepts &= FE_ALL_EXCEPT;
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__fcsr &= ~__excepts;
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__fcsr |= *__flagp & __excepts;
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fesetenv(&__fcsr);
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return 0;
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}
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static __inline int
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fegetround(void)
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{
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/*
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* Apparently, the rounding mode is specified as part of the
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* instruction format on ARM, so the dynamic rounding mode is
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* indeterminate. Some FPUs may differ.
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*/
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return (-1);
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static __inline int feraiseexcept(int __excepts) {
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fexcept_t __fcsr;
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fegetenv(&__fcsr);
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/* Ensure that flags are all legal */
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__excepts &= FE_ALL_EXCEPT;
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/* Cause bit needs to be set as well for generating the exception*/
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__fcsr |= __excepts | (__excepts << _FCSR_CAUSE_SHIFT);
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fesetenv(&__fcsr);
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return 0;
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}
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static __inline int
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fesetround(int __round)
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{
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return (-1);
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static __inline int fetestexcept(int __excepts) {
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fexcept_t __FCSR;
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fegetenv(&__FCSR);
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return (__FCSR & __excepts & FE_ALL_EXCEPT);
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}
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static __inline int
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fegetenv(fenv_t *__envp)
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{
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__rfs(__envp);
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return (0);
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static __inline int fegetround(void) {
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fenv_t _fcsr;
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fegetenv(&_fcsr);
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return (_fcsr & _FCSR_RMASK);
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}
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static __inline int
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feholdexcept(fenv_t *__envp)
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{
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fenv_t __env;
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__rfs(&__env);
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*__envp = __env;
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__env &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
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__wfs(__env);
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return (0);
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static __inline int fesetround(int __round) {
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fenv_t _fcsr;
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fegetenv(&_fcsr);
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_fcsr &= ~_FCSR_RMASK;
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_fcsr |= (__round & _FCSR_RMASK ) ;
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fesetenv(&_fcsr);
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return 0;
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}
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static __inline int
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fesetenv(const fenv_t *__envp)
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{
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__wfs(*__envp);
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return (0);
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static __inline int feholdexcept(fenv_t* __envp) {
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fenv_t __env;
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fegetenv(&__env);
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*__envp = __env;
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__env &= ~(FE_ALL_EXCEPT | _FCSR_ENABLE_MASK);
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fesetenv(&__env);
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return 0;
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}
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static __inline int
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feupdateenv(const fenv_t *__envp)
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{
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fexcept_t __fpsr;
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__rfs(&__fpsr);
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__wfs(*__envp);
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feraiseexcept(__fpsr & FE_ALL_EXCEPT);
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return (0);
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static __inline int feupdateenv(const fenv_t* __envp) {
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fexcept_t __fcsr;
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fegetenv(&__fcsr);
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fesetenv(__envp);
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feraiseexcept(__fcsr & FE_ALL_EXCEPT);
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return 0;
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}
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#if __BSD_VISIBLE
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static __inline int
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feenableexcept(int __mask)
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{
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fenv_t __old_fpsr, __new_fpsr;
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__rfs(&__old_fpsr);
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__new_fpsr = __old_fpsr | (__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT;
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__wfs(__new_fpsr);
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return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
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static __inline int feenableexcept(int __mask) {
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fenv_t __old_fcsr, __new_fcsr;
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fegetenv(&__old_fcsr);
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__new_fcsr = __old_fcsr | (__mask & FE_ALL_EXCEPT) << _ENABLE_SHIFT;
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fesetenv(&__new_fcsr);
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return ((__old_fcsr >> _ENABLE_SHIFT) & FE_ALL_EXCEPT);
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}
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static __inline int
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fedisableexcept(int __mask)
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{
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fenv_t __old_fpsr, __new_fpsr;
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__rfs(&__old_fpsr);
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__new_fpsr = __old_fpsr & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT);
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__wfs(__new_fpsr);
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return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
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static __inline int fedisableexcept(int __mask) {
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fenv_t __old_fcsr, __new_fcsr;
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fegetenv(&__old_fcsr);
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__new_fcsr = __old_fcsr & ~((__mask & FE_ALL_EXCEPT) << _ENABLE_SHIFT);
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fesetenv(&__new_fcsr);
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return ((__old_fcsr >> _ENABLE_SHIFT) & FE_ALL_EXCEPT);
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}
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static __inline int
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fegetexcept(void)
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{
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fenv_t __fpsr;
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__rfs(&__fpsr);
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return ((__fpsr & _ENABLE_MASK) >> _FPUSW_SHIFT);
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static __inline int fegetexcept(void) {
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fenv_t __fcsr;
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fegetenv(&__fcsr);
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return ((__fcsr & _FCSR_ENABLE_MASK) >> _ENABLE_SHIFT);
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}
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#endif /* __BSD_VISIBLE */
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__END_DECLS
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#endif /* !_FENV_H_ */
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#endif /* !_FENV_H_ */
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