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Henrik Smiding fe6338da91 Adjust memcpy for ARM Cortex A9 cache line size

ARM Cortex A8 use 64 bytes and ARM Cortex A9 use 32 bytes cache line
size.

The following patch:
  Adds code to adjust memcpy cache line size to match A9 cache line
  size.
  Adds a flag to select between 32 bytes and 64 bytes cache line
  size.

  Copyright (C) ST-Ericsson SA 2010
    Modified neon implementation to fit Cortex A9 cache line size
    Author: Henrik Smiding henrik.smiding@stericsson.com for
            ST-Ericsson.

Change-Id: I8a55946bfb074e6ec0a14805ed65f73fcd0984a3
Signed-off-by: Christian Bejram <christian.bejram@stericsson.com>

2012-05-07 14:18:02 +02:00

libc

Adjust memcpy for ARM Cortex A9 cache line size

2012-05-07 14:18:02 +02:00

libdl

MIPS support to libm, libdl and libthread_db

2012-05-04 11:34:40 -07:00

libm

MIPS support to libm, libdl and libthread_db

2012-05-04 11:34:40 -07:00

libstdc++

libstdc++: Fix x86 thread-safe one-time-construction implementation.