Merge "update video/dsscomp.h"
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4f3465240a
@ -197,128 +197,129 @@ struct dss2_ovl_cfg {
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__u8 enabled;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u8 zonly;
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__u8 mgr_ix;
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} __attribute__ ((aligned(4)));
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enum omapdss_buffer_type {
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OMAP_DSS_BUFTYPE_SDMA,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_BUFTYPE_SDMA,
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OMAP_DSS_BUFTYPE_TILER_8BIT,
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OMAP_DSS_BUFTYPE_TILER_16BIT,
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OMAP_DSS_BUFTYPE_TILER_32BIT,
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OMAP_DSS_BUFTYPE_TILER_PAGE,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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OMAP_DSS_BUFTYPE_TILER_PAGE,
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};
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struct dss2_ovl_info {
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struct dss2_ovl_cfg cfg;
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union {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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union {
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struct {
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void *address;
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__u16 ba_type;
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__u16 uv_type;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u16 uv_type;
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};
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struct {
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__u32 ba;
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__u32 uv;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 uv;
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};
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};
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};
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struct dss2_mgr_info {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct dss2_mgr_info {
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__u32 ix;
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__u32 default_color;
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enum omap_dss_trans_key_type trans_key_type;
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__u32 trans_key;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 trans_key;
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struct omap_dss_cpr_coefs cpr_coefs;
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__u8 trans_enabled;
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__u8 interlaced;
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__u8 alpha_blending;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u8 alpha_blending;
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__u8 cpr_enabled;
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__u8 swap_rb;
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} __attribute__ ((aligned(4)));
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enum dsscomp_setup_mode {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum dsscomp_setup_mode {
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DSSCOMP_SETUP_MODE_APPLY = (1 << 0),
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DSSCOMP_SETUP_MODE_DISPLAY = (1 << 1),
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DSSCOMP_SETUP_MODE_CAPTURE = (1 << 2),
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DSSCOMP_SETUP_APPLY = DSSCOMP_SETUP_MODE_APPLY,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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DSSCOMP_SETUP_APPLY = DSSCOMP_SETUP_MODE_APPLY,
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DSSCOMP_SETUP_DISPLAY =
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DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_DISPLAY,
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DSSCOMP_SETUP_CAPTURE =
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DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_CAPTURE,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_CAPTURE,
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DSSCOMP_SETUP_DISPLAY_CAPTURE =
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DSSCOMP_SETUP_DISPLAY | DSSCOMP_SETUP_CAPTURE,
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};
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struct dsscomp_setup_mgr_data {
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct dsscomp_setup_mgr_data {
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__u32 sync_id;
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struct dss2_rect_t win;
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enum dsscomp_setup_mode mode;
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__u16 num_ovls;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u16 num_ovls;
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__u16 get_sync_obj;
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struct dss2_mgr_info mgr;
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struct dss2_ovl_info ovls[0];
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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struct dsscomp_check_ovl_data {
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enum dsscomp_setup_mode mode;
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struct dss2_mgr_info mgr;
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struct dss2_ovl_info ovl;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct dss2_ovl_info ovl;
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};
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struct dsscomp_setup_dispc_data {
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__u32 sync_id;
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struct dss2_rect_t win;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum dsscomp_setup_mode mode;
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__u16 num_ovls;
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__u16 num_mgrs;
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__u16 get_sync_obj;
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struct dss2_mgr_info mgr;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct dss2_mgr_info mgrs[3];
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struct dss2_ovl_info ovls[5];
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};
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struct dsscomp_wb_copy_data {
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struct dss2_ovl_info ovl, wb;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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struct dss2_ovl_info ovl, wb;
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};
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struct dsscomp_display_info {
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__u32 ix;
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__u32 overlays_available;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u32 overlays_available;
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__u32 overlays_owned;
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enum omap_channel channel;
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enum omap_dss_display_state state;
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__u8 enabled;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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__u8 enabled;
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struct omap_video_timings timings;
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struct s3d_disp_info s3d_info;
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struct dss2_mgr_info mgr;
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};
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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};
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enum dsscomp_wait_phase {
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DSSCOMP_WAIT_PROGRAMMED = 1,
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DSSCOMP_WAIT_DISPLAYED,
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DSSCOMP_WAIT_RELEASED,
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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DSSCOMP_WAIT_RELEASED,
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};
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struct dsscomp_wait_data {
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__u32 timeout_us;
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enum dsscomp_wait_phase phase;
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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enum dsscomp_wait_phase phase;
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};
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#define DSSCOMP_SETUP_MGR _IOW('O', 128, struct dsscomp_setup_mgr_data)
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#define DSSCOMP_CHECK_OVL _IOWR('O', 129, struct dsscomp_check_ovl_data)
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#define DSSCOMP_WB_COPY _IOW('O', 130, struct dsscomp_wb_copy_data)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define DSSCOMP_WB_COPY _IOW('O', 130, struct dsscomp_wb_copy_data)
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#define DSSCOMP_QUERY_DISPLAY _IOWR('O', 131, struct dsscomp_display_info)
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#define DSSCOMP_WAIT _IOW('O', 132, struct dsscomp_wait_data)
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#define DSSCOMP_SETUP_DISPC _IOW('O', 127, struct dsscomp_setup_dispc_data)
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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