Commit Graph

39 Commits

Author SHA1 Message Date
Greg Tucker
112dd72c01 build: Remove unneeded file types.h
The file types.h has long been misnamed and overlaps with
functionality in the test helper routines.

Change-Id: I774047d3a0074198b67a6b4e909f1e2ce1938195
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2021-06-10 09:35:43 -07:00
luo rixin
bee5180a15 erasure_code: Fix text relocation on aarch64
Here is the bug report on ceph. https://tracker.ceph.com/issues/48681

Change-Id: Ie1c60a71f28c1a169c8899a621be9bb455f5e244
Signed-off-by: luo rixin <luorixin@huawei.com>
2021-01-08 15:23:15 -07:00
H.J. Lu
cd888f01a4 x86: Add ENDBR32/ENDBR64 at function entries for Intel CET
To support Intel CET, all indirect branch targets must start with
ENDBR32/ENDBR64.  Here is a patch to define endbranch and add it to
function entries in x86 assembly codes which are indirect branch
targets as discovered by running testsuite on Intel CET machine and
visual inspection.

Verified with

$ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux
$ make -j8
$ make -j8 check

with both nasm and yasm on both CET and non-CET machines.

Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2020-05-26 09:16:49 -07:00
Greg Tucker
af13ed6136 ec: Fix second windows reg push for avx512
Change improper stack push in windows prolog.  Error was not reachable without
windows nasm support and so went undetected.

Change-Id: I8b715195d1c8efd173843c043d42fc610ddebd17
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2020-03-20 12:36:58 -07:00
Greg Tucker
ede04f0a1f build: Fix for windows to allow nasm use
Previously windows build could only use yasm because some procedural items such
as proc_start were not supported by nasm.  This adds a few macros and fixes so
nasm can be used to build on windows.

Change-Id: Ia05dc3ff482f33b0f915bb1be3c7df5e4a753b3a
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2020-03-17 18:05:46 -07:00
Greg Tucker
5ab40c79cc ec: Fix windows reg push for avx512
Push of registers overlapped xmm push.  Error was not reachable without windows
nasm support and so went undetected.

Change-Id: I0ffd66f6d32ac37ea03fe9b11924968aa50f8fa7
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2020-03-17 18:05:46 -07:00
Greg Tucker
472e7011e8 ec: Change use of windows macro save_xmm128 to vec
For builds under windows this could emit a non-vec mov that's not optional for
AVX versions.

Change-Id: I31e6ea3b62d48c5a13f6e83f8d684f0b5551087b
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2020-03-17 18:04:54 -07:00
Greg Tucker
794413ddd2 ec: Remove arch-specific redundant gf_nvect tests
The gf_{2-6}vect_dot_prod tests were kept in other_tests since the 5,6vect
functions were not strictly called by the higher level ec_encode_data() and
needed independent testing.  As this has now changed the extra tests can be
removed as redundant.

Change-Id: I8a95e31487b150a2a8f929c5586785524d951fde
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2020-03-06 13:45:59 -07:00
Hong Bo Peng
180c74aefd enable VSX SIMD in ISA-L for ppc64le
1) Implement the ErasureCode function in Altivec Intrinsics
  2) Coding style update

Change-Id: I2c81d035f4083e9b011dbf3b741f628813b68606
Thanks-to: Daniel Axtens <dja@axtens.net>
Signed-off-by: Hong Bo Peng <penghb@cn.ibm.com>
2020-02-20 09:40:43 -07:00
John Kariuki
5eeb33f69c ec: add AVX512 ec functions with 5 and 6 outputs
Added AVX512 optimized functions to calculate the
GF(2^8) vector dot product with 5 and 6 outputs
at a time. Also added GF(2^8) vector multiply
AVX512 optimized functions with 5 and 6 accumulate.

Change-Id: I6d2c080f4f4f8e4823ad9a9be2c65c3b5b3bb1f8
Signed-off-by: John Kariuki <John.K.Kariuki@intel.com>
2019-11-19 10:12:14 -07:00
Hang Li
02a86dfb3f erasure_code: modify eor way in aarch64 neon codes
Change-Id: I9fb9219c5f280ed88194ec63234af046a5a036ae
Signed-off-by: Hang Li <lihang48@hisilicon.com>
2019-11-01 15:31:33 -07:00
Hang Li
621cf92c52 erasure_code: modify perf benchmark loop
Change-Id: Ie45ceb3ac55ab943a155e2a3f9f6b765cd94d7a1
Signed-off-by: Hang Li <lihang48@hisilicon.com>
2019-10-30 10:34:40 -07:00
Zhou Xiong
d7848c1d05 Implement aarch64 neon for erasure code.
1.Replace below erasure code interfaces to arm neon interface by mbin_interface function.
	ec_encode_data
	gf_vect_mul
	gf_vect_dot_prod
	gf_vect_mad
	ec_encode_data_update

2.Utilise arm neon instrution to accelerate GF(2^8) set compute by 128bit registor.

Change-Id: Ib0ecbfbd1837d2b1f823d26815c896724d2d22e4
Signed-off-by: Zhou Xiong <zhouxiong13@huawei.com>
2019-10-25 11:09:03 -07:00
Bernd Schubert
d32d3f6902 Make variables in ec_base.h (file) static
ec_base.h has several variables, which were defined with
a global scope. Exactly those global variables caused issues
on linking a static compilation of libisal.a to a shared lib.
Adding -fPIC to CFLAGS somehow didn't help.
As all the variables in ec_base.h are only included
and used by a single C file, all of these can be
(file) static, which then will also helps the compiler to
make further optimizations. And which also solves the issue
to link the static libisal to a shared lib.

Also make the variables const, as these are constants and
must be modified.

Change-Id: I2b8141dabc1c7a528401f2778cdbdbed6c93c36b
Signed-off-by: Bernd Schubert <bschubert@ddn.com>
2019-10-11 15:39:56 -07:00
Roy Oursler
d3caab9c3a build: Avoid requiring AVX512 define when using dispatch functions
Change-Id: I76af2d6ab7eb61ae531bbc7427650d08737c20ab
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
2019-09-14 16:01:28 -07:00
Greg Tucker
4ac0e435eb ec: Fix incorrect min size stated for gf_vect_mad
Change-Id: If178913f01f0d500aa66ce0e8dd67aaba49a0871
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2019-07-16 15:41:34 -07:00
Yibo Cai
57eed2f02b aarch64: Cleanup build issues
This patch addresses one build failure and fixes several build warnings
for Arm (some for x86 too).

- Fix dynamic relocation link failure of ld.bfd 2.30 on Arm
  [log] relocation R_AARCH64_ADR_PREL_PG_HI21 against symbol `xor_gen_neon' which may bind externally can not be used when making a shared object

- Add arch dependent "other_tests" to exclude x86 specific tests on Arm
  [log] isa-l/erasure_code/gf_2vect_dot_prod_sse_test.c:181: undefined reference to `gf_2vect_dot_prod_sse'

- Check "fread" return value to fix gcc warnings on Arm and x86
  [log] warning: ignoring return value of ‘fread’, declared with attribute warn_unused_result [-Wunused-result]
        fread(in_buf, 1, in_size, in_file);
        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

- Fix issue of comparing "char" with "int" on Arm. "char" is unsigned
  on Arm by default, an unsigned char will never equal to EOF(-1).
  [Log] programs/igzip_cli.c:318:31: warning: comparison is always true due to limited range of data type [-Wtype-limits]
        while (tmp != '\n' && tmp != EOF)
                                  ^~

- Include <stdlib.h> to several files to fix build warnings on Arm
  [log] igzip/igzip_inflate_perf.c:339:5: warning: incompatible implicit declaration of built-in function ‘exit’
        exit(0);
        ^~~~

Change-Id: I82c1b63316b634b3d398ffba2ff815679d9051a8
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
2019-03-20 10:15:40 +08:00
Greg Tucker
3c009347b1 Fix a few c99isms in unit tests
Change-Id: Iea9ba619e337d5abea7ee791ddf3dd27e0f3e60f
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2019-03-19 15:02:40 -07:00
Roy Oursler
699bb5bd3f all: Revamp performance testing to be time based
Change-Id: I6260d28e4adc974d8db0a1c770e3eb922d87f8e4
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
2019-03-07 09:28:04 -07:00
Roy Oursler
3a78c4a205 ec: Remove gf_vect_mad_perf.c
Remove gf_vect_mad_perf.c as it is architecture specific and does not provide
useful information in its current format.

Change-Id: I7819679db491a9b5572128e4fc05d989b870d22d
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
2019-03-07 09:28:04 -07:00
Yibo Cai
7a44098a98 build: Add aarch64 support
Change-Id: If9594936a28355d89edd1a331b3b429dffa44184
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
2019-02-10 13:08:56 -07:00
Greg Tucker
2e212f28fa build: Fix for mac nasm lack of symbol types
Change-Id: I9ee86a3e32876d3860477c8365fc459d94a8920e
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2018-11-29 13:54:36 -07:00
Greg Tucker
09e787231b ec: Change gf_mad_test to use multi-binary function
Change-Id: Ibe484239b75514b5563dd043bb0e8c46d3bdac5e
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2018-10-09 17:55:56 -07:00
Greg Tucker
bee68480b8 ec: Remove references in lib source to types.h
Change-Id: I3e8db92626c92d21c2426bbad89a10fa10c3e002
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2018-06-21 14:39:08 -07:00
Daniel Verkamp
d9ec2c4c8a ec: use standard types in struct slver
This matches the definition of struct slver elsewhere in the code.

Removes the last use of [U]INT{8,16,32,64} types.

Change-Id: I70761ac27add1e19808f1cebd6a7ee69ebd08dee
Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
2018-03-29 09:34:21 -07:00
Jean-Yves VET
52bb322912 build: fix compilation with CPU not supporting SSE
This patch makes the project compile and run (tests and
performance tests as well) with CPUs which are not
supporting SSE instructions.

Signed-off-by: Jean-Yves Vet <jyvet@ddn.com>
2018-02-23 06:13:10 -05:00
Greg Tucker
cb4cea60da test: Remove redundant arch-specific tests
Change-Id: Ifdbac9d8a99888bfd7a12da5d47dd07b8f85481d
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-11-30 11:13:21 -07:00
Xiaodong Liu
3ab8239097 multibinary: move WRT_OPT macro to common header
Signed-off-by: Xiaodong Liu <xiaodong.liu@intel.com>
2017-08-18 14:24:57 -07:00
Roy Oursler
82a6ac65dc ec: Determine exact conditions where gf_gen_rs_matrix works
Add a program calculating some of the exact conditions where gf_gen_rs_matrix
works, add comments stating these bounds to gf_gen_rs_matrix, and fix erasure
code test that violates the bounds.

Change-Id: I1d0010b09fea97731bfd24f4f76e24609538b24f
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
2017-06-26 04:11:12 -04:00
Greg Tucker
fc1467deb2 Format only patch from iindent and remove_whitespace
Change-Id: I114bfcfa8750c7ba3a50ad2be9dd9e87cb7a1042
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-06-26 04:10:47 -04:00
Roy Oursler
4f2d148ae5 erasure_code: Limit efence test length
Change-Id: Ib3bb0fa2fbcbbb759af7ea54fef5ea24ee1ba7cd
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
2017-06-21 05:32:19 -04:00
Greg Tucker
5d9cf8cadf ec: Fixes for 32-bit build
Change-Id: Iac362f0d7282716a8502afcec939b0d1877a943f
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-30 17:56:07 -07:00
Greg Tucker
a0bfd8d02b ec: Add base function aliases
Change-Id: I36f1a7948e0009ca5f4f67437f4aa704e737a05a
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-30 17:40:16 -07:00
Greg Tucker
4ec9df4f8a ec: Group src by arch
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-06 16:13:48 -07:00
Xiaodong Liu
b34cb054fd build: Fix an include path to be srcdir relative
Allows configure to again build in an external directory.  When building ISAL in
an external path, assembler or compiler needs relative include paths.

Signed-off-by: Xiaodong Liu <xiaodong.liu@intel.com>
Reviewed-by: Greg Tucker <greg.b.tucker@intel.com>
2016-12-02 16:54:40 -07:00
Greg Tucker
f7ee664dc0 Remove warnings due to unexported functions
The avx512 functions are not directly exported and this could cause warnings
when unit tests try to link to them directly.

Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2016-02-25 17:32:34 -07:00
Greg Tucker
a5b324d2cd Add avx512 versions of ec_encode_data
- Includes gf_nvect_dot_prod, gf_nvect_mad functions
 - Change ec multibinary to use common macros
 - Autoconf checks for nasm or yasm support and picks if available
 - Leave out compile of any avx512 code if assembler not available

Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2016-02-25 17:32:34 -07:00
Greg Tucker
bc4dfc9bbc Convert files to build with nasm or yasm
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2016-02-25 17:32:34 -07:00
Greg Tucker
00c1efc109 Initial commit isa-l v2.14.1
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2016-02-24 14:54:34 -07:00