Some CPUs report "illegal instruction" error for the crc test because
they do not support the relevant optional feature . This can be fixed by
introducing CPU feature detection for AArch64 .
The difference with the x86 implementation is the dispatcher . It is based
on the glibc function `getauxval(AT_HWCAP)` and `getauxval(AT_HWCAP2)` , not
registers or instructions .
On a heterogeneous system (big.LITTLE) , it is dangerous to detect CPU
features using identification registers . And while it is possible to use
architectural feature registers from userspace on recent kernels, this
won't necessarily work with older platforms . Thus we use the HW_CAPs
exported from the kernel (and visible in getauxval) as the solution.
- According to kernel suggestion , getauxval should be used for this purpose .
- [CPU Feature detection](https://github.com/torvalds/linux/blob/master/Documentation/arm64/cpu-feature-registers.rst)
- According to AAPCS result/paramter registers should be saved/restore for function call
- [AAPCS](http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf)
- [GLibc](https://sourceware.org/git/gitweb.cgi?p=glibc.git;a=blob;f=sysdeps/aarch64/dl-trampoline.S)
Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>
Change-Id: Ic9abe0d2268ac95537e1abf10acc642fc58a5054
This patch addresses one build failure and fixes several build warnings
for Arm (some for x86 too).
- Fix dynamic relocation link failure of ld.bfd 2.30 on Arm
[log] relocation R_AARCH64_ADR_PREL_PG_HI21 against symbol `xor_gen_neon' which may bind externally can not be used when making a shared object
- Add arch dependent "other_tests" to exclude x86 specific tests on Arm
[log] isa-l/erasure_code/gf_2vect_dot_prod_sse_test.c:181: undefined reference to `gf_2vect_dot_prod_sse'
- Check "fread" return value to fix gcc warnings on Arm and x86
[log] warning: ignoring return value of ‘fread’, declared with attribute warn_unused_result [-Wunused-result]
fread(in_buf, 1, in_size, in_file);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- Fix issue of comparing "char" with "int" on Arm. "char" is unsigned
on Arm by default, an unsigned char will never equal to EOF(-1).
[Log] programs/igzip_cli.c:318:31: warning: comparison is always true due to limited range of data type [-Wtype-limits]
while (tmp != '\n' && tmp != EOF)
^~
- Include <stdlib.h> to several files to fix build warnings on Arm
[log] igzip/igzip_inflate_perf.c:339:5: warning: incompatible implicit declaration of built-in function ‘exit’
exit(0);
^~~~
Change-Id: I82c1b63316b634b3d398ffba2ff815679d9051a8
Signed-off-by: Yibo Cai <yibo.cai@arm.com>
If an application treats these functions as function pointers, and this
lib (isa-l) is compiled into solib, a segmentation fault may occur.
For example: Ubuntu 16.04 on arm64 platfrom will be crash, because the
linker does not know that this symbol is a function, so mark the function
type explicitly with %function to solves this issue.
Change-Id: Iba41b1f1367146d7dcce09203694b08b1cb8ec20
Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
Added multi-arch support to configure.ac.
Updated header files to only export sse and avx functions on x86
Change-Id: I4d1f8d0eccabad55ee887dc092a565c468f5c629
Signed-off-by: John Kariuki <John.K.Kariuki@intel.com>
If a user passes an invalid size for window bits it could have triggered an
undefined shift by larger than variable size.
Change-Id: Ib2999b094af075596be3333418667ae9b498e2ae
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
This patch introduces the base, avx and sse optimized zero detect memory function.
The zero detect memory function tests if a memory region is all zeroes. If all the
bytes in the memory region are zero, the function return a zero. Otherwise, if the
memory region has non zero bytes, the zero detect function returns a 1.
Change-Id: If965badf750377124d0067d09f888d0419554998
Signed-off-by: John Kariuki <John.K.Kariuki@intel.com>
Previously included just for struct alignment but all restrictions
have been removed.
Change-Id: I3fa7cbab86fce419b3b3bfccb48d9129bd77cf64
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
These can be replaced with the <stdint.h> types.
Additionally, the existing definitions weren't correct on some platforms
(e.g. IA-32, where 'long', used for INT64/UINT64, is only 32 bits).
Change-Id: I1d9235c693ca2dc0c51d085128cecc4effc165fd
Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
Move current level 2 compression to be level 3 and create a level 2
compression which is the same algorithm as level 1 but with a larger
hashtable.
Change-Id: I398a6017c2ff218dded24e229fb51c23ea69f314
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
Merge crc32_gzip_refl function definitions, base code, multi-binary
code into crc32.h, crc32_base,c and crc_multibinary.asm in order to
keep consistency. Add crc32_gzip_refl files into crc/Makefile.am
Original crc32_gzip_refl removed NOT operation, re-add it.
Change-Id: Ib0cbbeb1ab3c9fcafec324b392596d2514202424
Signed-off-by: Xiaodong Liu <xiaodong.liu@intel.com>
Add a program calculating some of the exact conditions where gf_gen_rs_matrix
works, add comments stating these bounds to gf_gen_rs_matrix, and fix erasure
code test that violates the bounds.
Change-Id: I1d0010b09fea97731bfd24f4f76e24609538b24f
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
