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igzip: implement gen_icf_map with assembly
Change-Id: I74e6200a732acfaac44b7f5a82bd4a2215ba1535 Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
This commit is contained in:
Zhiyuan Zhu
@@ -50,6 +50,7 @@ lsrc_aarch64 += igzip/aarch64/igzip_inflate_multibinary_arm64.S \
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igzip/aarch64/igzip_set_long_icf_fg.S \
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igzip/aarch64/encode_df.S \
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igzip/aarch64/isal_update_histogram.S \
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igzip/aarch64/gen_icf_map.S \
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igzip/aarch64/igzip_deflate_hash_aarch64.S \
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igzip/proc_heap_base.c
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266
igzip/aarch64/gen_icf_map.S
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266
igzip/aarch64/gen_icf_map.S
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@@ -0,0 +1,266 @@
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/**********************************************************************
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Copyright(c) 2019 Arm Corporation All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Arm Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**********************************************************************/
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.arch armv8-a+crc+crypto
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.text
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.align 2
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#include "lz0a_const_aarch64.h"
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#include "data_struct_aarch64.h"
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#include "huffman_aarch64.h"
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#include "bitbuf2_aarch64.h"
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#include "stdmac_aarch64.h"
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/*
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declare Macros
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*/
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.macro declare_generic_reg name:req,reg:req,default:req
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\name .req \default\reg
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w_\name .req w\reg
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x_\name .req x\reg
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.endm
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.macro tzbytecnt param0:req,param1:req
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rbit x_\param1, x_\param0
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cmp x_\param0, 0
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clz x_\param1, x_\param1
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mov w_\param0, 8
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lsr w_\param1, w_\param1, 3
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csel w_\param0, w_\param1, w_\param0, ne
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.endm
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.macro write_deflate_icf param0:req,param1:req,param2:req,param3:req
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orr w_\param1, w_\param1, w_\param3, lsl 19
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orr w_\param1, w_\param1, w_\param2, lsl 10
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str w_\param1, [x_\param0]
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.endm
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.align 2
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.global gen_icf_map_h1_aarch64
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.type gen_icf_map_h1_aarch64, %function
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/* arguments */
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declare_generic_reg stream_param, 0,x
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declare_generic_reg matches_icf_lookup_param, 1,x
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declare_generic_reg input_size_param, 2,x
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declare_generic_reg param0, 0,x
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declare_generic_reg param1, 1,x
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declare_generic_reg param2, 2,x
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declare_generic_reg param3, 3,x
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/* return */
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declare_generic_reg ret_val, 0,x
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/* variables */
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declare_generic_reg input_size, 3,x
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declare_generic_reg next_in, 4,x
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declare_generic_reg matches_icf_lookup, 6,x
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declare_generic_reg hash_table, 7,x
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declare_generic_reg end_in, 8,x
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declare_generic_reg file_start, 9,x
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declare_generic_reg hash_mask, 10,w
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declare_generic_reg hist_size, 11,w
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declare_generic_reg stream_saved, 12,x
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declare_generic_reg literal_32, 13,w
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declare_generic_reg literal_1, 14,w
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declare_generic_reg dist, 15,w
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declare_generic_reg tmp_has_hist, 0,w
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declare_generic_reg tmp_offset_hash_table, 1,x
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declare_generic_reg tmp0, 0,x
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declare_generic_reg tmp1, 1,x
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declare_generic_reg tmp2, 2,x
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declare_generic_reg tmp3, 3,x
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declare_generic_reg tmp5, 5,x
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/* constant */
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.equ ISAL_LOOK_AHEAD, 288
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.equ SHORTEST_MATCH, 4
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.equ LEN_OFFSET, 254
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/* mask */
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.equ mask_10bit, 1023
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.equ mask_lit_dist, 0x7800
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/* offset of struct isal_zstream */
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.equ offset_next_in, 0
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.equ offset_avail_in, 8
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.equ offset_total_in, 12
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.equ offset_next_out, 16
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.equ offset_avail_out, 24
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.equ offset_total_out, 28
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.equ offset_hufftables, 32
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.equ offset_level, 40
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.equ offset_level_buf_size, 44
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.equ offset_level_buf, 48
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.equ offset_end_of_stream, 56
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.equ offset_flush, 58
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.equ offset_gzip_flag, 60
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.equ offset_hist_bits, 62
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.equ offset_state, 64
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.equ offset_state_block_end, 72
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.equ offset_state_dist_mask, 76
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.equ offset_state_has_hist, 135
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/* offset of struct level_buf */
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.equ offset_hash_map_hash_table, 4712
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/*
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uint64_t gen_icf_map_h1_base(struct isal_zstream *stream,
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struct deflate_icf *matches_icf_lookup, uint64_t input_size)
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*/
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gen_icf_map_h1_aarch64:
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cmp input_size_param, (ISAL_LOOK_AHEAD-1) // 287
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bls .fast_exit
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stp x29, x30, [sp, -16]!
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mov stream_saved, stream_param
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mov matches_icf_lookup, matches_icf_lookup_param
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mov x29, sp
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ldrb tmp_has_hist, [stream_saved, offset_state_has_hist]
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mov tmp_offset_hash_table, offset_hash_map_hash_table
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ldr end_in, [stream_saved, offset_next_in]
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mov input_size, input_size_param
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ldr hash_table, [stream_saved, offset_level_buf]
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ldr w_file_start, [stream_saved, offset_total_in]
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ldp hist_size, hash_mask, [stream_saved, offset_state_dist_mask]
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add hash_table, hash_table, tmp_offset_hash_table
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sub file_start, end_in, file_start
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cbz tmp_has_hist, .igzip_no_hist
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b .while_check1
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.align 3
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.igzip_no_hist:
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ldrb w_tmp1, [end_in]
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add next_in, end_in, 1
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ldrh w_tmp0, [matches_icf_lookup]
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bfi w_tmp0, w_tmp1, 0, 10
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strh w_tmp0, [matches_icf_lookup]
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ldr w_tmp0, [matches_icf_lookup]
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and w_tmp0, w_tmp0, mask_10bit
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orr w_tmp0, w_tmp0, mask_lit_dist
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str w_tmp0, [matches_icf_lookup], 4
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ldr w_tmp0, [end_in]
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crc32cw w_tmp0, wzr, w_tmp0
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and w_tmp5, w_tmp0, hash_mask
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sub x_tmp1, end_in, file_start
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mov w_tmp2, 1
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mov x_tmp0, 1
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strh w_tmp1, [hash_table, x_tmp5, lsl 1]
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strb w_tmp2, [stream_saved, offset_state_has_hist]
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b .while_check2
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.while_check1:
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mov next_in, end_in
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mov x_tmp0, 0
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.while_check2:
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sub input_size, input_size, #288
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add end_in, end_in, input_size
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cmp next_in, end_in
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bcs .exit
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mov literal_32, 32
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mov literal_1, 1
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b .while_loop
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.align 3
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.new_match_found:
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clz w_tmp5, w_tmp2
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add w_tmp1, w_tmp0, LEN_OFFSET
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sub w_tmp5, literal_32, w_tmp5
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cmp dist, 2
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sub w_tmp5, w_tmp5, #2
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bls .skip_compute_dist_icf_code
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lsl w_tmp3, literal_1, w_tmp5
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sub w_tmp3, w_tmp3, #1
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lsr w_tmp0, w_tmp2, w_tmp5
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and w_tmp3, w_tmp3, w_tmp2
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add w_tmp2, w_tmp0, w_tmp5, lsl 1
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.skip_compute_dist_icf_code:
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mov param0, matches_icf_lookup
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write_deflate_icf param0,param1,param2,param3
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add next_in, next_in, 1
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add matches_icf_lookup, matches_icf_lookup, 4
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cmp next_in, end_in
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beq .save_with_exit
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.while_loop:
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ldr w_tmp0, [next_in]
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crc32cw w_tmp0, wzr, w_tmp0
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and w_tmp0, w_tmp0, hash_mask
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sub x_tmp1, next_in, file_start
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lsl x_tmp0, x_tmp0, 1
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sub w_tmp2, w_tmp1, #1
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ldrh w_tmp3, [hash_table, x_tmp0]
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strh w_tmp1, [hash_table, x_tmp0]
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sub w_tmp2, w_tmp2, w_tmp3
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and w_tmp2, w_tmp2, hist_size
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add dist, w_tmp2, 1
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ldr x_tmp0, [next_in]
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sub x_tmp1, next_in, x_dist, uxtw
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ldr x_tmp1, [x_tmp1]
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eor x_tmp0, x_tmp1, x_tmp0
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tzbytecnt param0,param1
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cmp w_tmp0, (SHORTEST_MATCH-1)
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mov w_tmp3, 0
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bhi .new_match_found
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ldrb w_param1, [next_in]
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mov x_param0, matches_icf_lookup
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mov w_param3, 0
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mov w_param2, 0x1e
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write_deflate_icf param0,param1,param2,param3
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add next_in, next_in, 1
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add matches_icf_lookup, matches_icf_lookup, 4
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cmp next_in, end_in
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bne .while_loop
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.save_with_exit:
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ldr ret_val, [stream_saved, offset_next_in]
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sub ret_val, next_in, ret_val
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.exit:
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ldp x29, x30, [sp], 16
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ret
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.align 3
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.fast_exit:
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mov ret_val, 0
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ret
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.size gen_icf_map_h1_aarch64, .-gen_icf_map_h1_aarch64
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@@ -132,6 +132,16 @@ DEFINE_INTERFACE_DISPATCHER(isal_update_histogram)
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return PROVIDER_BASIC(isal_update_histogram);
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}
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DEFINE_INTERFACE_DISPATCHER(gen_icf_map_lh1)
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{
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unsigned long auxval = getauxval(AT_HWCAP);
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if (auxval & HWCAP_CRC32) {
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return PROVIDER_INFO(gen_icf_map_h1_aarch64);
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}
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return PROVIDER_BASIC(gen_icf_map_h1);
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}
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DEFINE_INTERFACE_DISPATCHER(isal_deflate_hash_lvl0)
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{
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unsigned long auxval = getauxval(AT_HWCAP);
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@@ -39,7 +39,7 @@ mbin_interface isal_deflate_icf_finish_lvl3
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mbin_interface isal_update_histogram
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mbin_interface encode_deflate_icf
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mbin_interface set_long_icf_fg
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mbin_interface_base gen_icf_map_lh1 , gen_icf_map_h1_base
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mbin_interface gen_icf_map_lh1
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mbin_interface isal_deflate_hash_lvl0
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mbin_interface isal_deflate_hash_lvl1
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mbin_interface isal_deflate_hash_lvl2
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