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isa-l/crc/aarch64/Makefile.am

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crc: optimize crc with arm64 assembly Change-Id: I49166ee06b3ad24babb90aeb0b834d8aacfc2d03 Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
2019-06-03 03:09:33 +02:00
########################################################################
crc32:Add optimization implementation for Neoverse N1 This patch is base on reference(1) algorithm with some changes. - Redefine the block number to two. - That's due to only two pipe-line can be used in CRC32 calculate. - Redefine the block size: - The block size of CRC is 1536B and PMULL is 512B - Interleave CRC and PMULL instructions. The optimization parameters are calculated base on reference(2) References: - https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf - https://developer.arm.com/docs/swog309707/a Change-Id: I1c9e593d59b521f56e4b3c807b396c083c181636 Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>
2020-03-02 06:34:44 +01:00
# Copyright(c) 2020 Arm Corporation All rights reserved.
crc: optimize crc with arm64 assembly Change-Id: I49166ee06b3ad24babb90aeb0b834d8aacfc2d03 Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
2019-06-03 03:09:33 +02:00
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# * Neither the name of Arm Corporation nor the names of its
# contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#########################################################################
lsrc_aarch64 += \
multibinary: Add run-time cpu feature detect for aarch64 Some CPUs report "illegal instruction" error for the crc test because they do not support the relevant optional feature . This can be fixed by introducing CPU feature detection for AArch64 . The difference with the x86 implementation is the dispatcher . It is based on the glibc function `getauxval(AT_HWCAP)` and `getauxval(AT_HWCAP2)` , not registers or instructions . On a heterogeneous system (big.LITTLE) , it is dangerous to detect CPU features using identification registers . And while it is possible to use architectural feature registers from userspace on recent kernels, this won't necessarily work with older platforms . Thus we use the HW_CAPs exported from the kernel (and visible in getauxval) as the solution. - According to kernel suggestion , getauxval should be used for this purpose . - [CPU Feature detection](https://github.com/torvalds/linux/blob/master/Documentation/arm64/cpu-feature-registers.rst) - According to AAPCS result/paramter registers should be saved/restore for function call - [AAPCS](http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf) - [GLibc](https://sourceware.org/git/gitweb.cgi?p=glibc.git;a=blob;f=sysdeps/aarch64/dl-trampoline.S) Signed-off-by: Jerry Yu <jerry.h.yu@arm.com> Change-Id: Ic9abe0d2268ac95537e1abf10acc642fc58a5054
2019-05-13 12:41:06 +02:00
crc/aarch64/crc_multibinary_arm.S \
crc/aarch64/crc_aarch64_dispatcher.c
crc: optimize crc with arm64 assembly Change-Id: I49166ee06b3ad24babb90aeb0b834d8aacfc2d03 Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
2019-06-03 03:09:33 +02:00
lsrc_aarch64 += \
crc/aarch64/crc16_t10dif_pmull.S \
crc/aarch64/crc16_t10dif_copy_pmull.S \
crc/aarch64/crc32_iscsi_refl_pmull.S \
crc/aarch64/crc32_iscsi_refl_hw_fold.S \
crc/aarch64/crc32_ieee_norm_pmull.S \
crc/aarch64/crc32_gzip_refl_pmull.S \
crc/aarch64/crc32_gzip_refl_hw_fold.S \
crc/aarch64/crc64_ecma_refl_pmull.S \
crc/aarch64/crc64_ecma_norm_pmull.S \
crc/aarch64/crc64_iso_refl_pmull.S \
crc/aarch64/crc64_iso_norm_pmull.S \
crc/aarch64/crc64_jones_refl_pmull.S \
crc32:Add optimization implementation for Neoverse N1 This patch is base on reference(1) algorithm with some changes. - Redefine the block number to two. - That's due to only two pipe-line can be used in CRC32 calculate. - Redefine the block size: - The block size of CRC is 1536B and PMULL is 512B - Interleave CRC and PMULL instructions. The optimization parameters are calculated base on reference(2) References: - https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf - https://developer.arm.com/docs/swog309707/a Change-Id: I1c9e593d59b521f56e4b3c807b396c083c181636 Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>
2020-03-02 06:34:44 +01:00
crc/aarch64/crc64_jones_norm_pmull.S \
crc32: Implement default mix mode optimization Change-Id: Ib3bf04215cca491db522ec33905fe48df173cc2f Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
2020-04-26 15:26:05 +02:00
crc/aarch64/crc32_mix_default.S \
crc/aarch64/crc32c_mix_default.S \
crc32:Add optimization implementation for Neoverse N1 This patch is base on reference(1) algorithm with some changes. - Redefine the block number to two. - That's due to only two pipe-line can be used in CRC32 calculate. - Redefine the block size: - The block size of CRC is 1536B and PMULL is 512B - Interleave CRC and PMULL instructions. The optimization parameters are calculated base on reference(2) References: - https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf - https://developer.arm.com/docs/swog309707/a Change-Id: I1c9e593d59b521f56e4b3c807b396c083c181636 Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>
2020-03-02 06:34:44 +01:00
crc/aarch64/crc32_mix_neoverse_n1.S \
crc32:Optimize crc32/c for cortex-a72 Change-Id: Ib1658fd4b87b31d8ea6c93f697b50d9b409c186e Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>
2020-04-02 16:05:29 +02:00
crc/aarch64/crc32c_mix_neoverse_n1.S \
crc/aarch64/crc32_crc_ext_cortex_a72.S \
crc/aarch64/crc32c_crc_ext_cortex_a72.S
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