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Add Silvermont architecture cache sizes

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Adds Silvermont specific cache sizes for bionic optimizations.

Change-Id: Ib992f530b8c485121b2874470fd6bed2212adb0f
Signed-off-by: Henrik Smiding <henrik.smiding@intel.com>
This commit is contained in:
Henrik Smiding 2014-01-08 16:57:55 +01:00 committed by yijunx.zhu
parent c19972a4ca
commit 3bfa0fd32f
1 changed files with 7 additions and 0 deletions
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7
libc/arch-x86/string/cache.h
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@ -28,8 +28,15 @@ ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#if defined(__slm__)
/* Values are optimized for Silvermont */
#define SHARED_CACHE_SIZE (1024*1024) /* Silvermont L2 Cache */
#define DATA_CACHE_SIZE (24*1024) /* Silvermont L1 Data Cache */
#else
/* Values are optimized for Atom */ /* Values are optimized for Atom */
#define SHARED_CACHE_SIZE (512*1024) /* Atom L2 Cache */ #define SHARED_CACHE_SIZE (512*1024) /* Atom L2 Cache */
#define DATA_CACHE_SIZE (24*1024) /* Atom L1 Data Cache */ #define DATA_CACHE_SIZE (24*1024) /* Atom L1 Data Cache */
#endif
#define SHARED_CACHE_SIZE_HALF (SHARED_CACHE_SIZE / 2) #define SHARED_CACHE_SIZE_HALF (SHARED_CACHE_SIZE / 2)
#define DATA_CACHE_SIZE_HALF (DATA_CACHE_SIZE / 2) #define DATA_CACHE_SIZE_HALF (DATA_CACHE_SIZE / 2)