generic-library/bionic
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add Silvermont architecture cache sizes

Browse Source 
Adds Silvermont specific cache sizes for bionic optimizations.

Change-Id: Ib992f530b8c485121b2874470fd6bed2212adb0f
Signed-off-by: Henrik Smiding <henrik.smiding@intel.com>
This commit is contained in:
Henrik Smiding 2014-01-08 16:57:55 +01:00 committed by yijunx.zhu
parent c19972a4ca
commit 3bfa0fd32f
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
libc/arch-x86/string/cache.h
View File

@ -28,8 +28,15 @@ ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#if defined(__slm__)
/* Values are optimized for Silvermont */
#define SHARED_CACHE_SIZE (1024*1024) /* Silvermont L2 Cache */
#define DATA_CACHE_SIZE (24*1024) /* Silvermont L1 Data Cache */
#else
/* Values are optimized for Atom */
#define SHARED_CACHE_SIZE (512*1024) /* Atom L2 Cache */
#define DATA_CACHE_SIZE (24*1024) /* Atom L1 Data Cache */
#endif
#define SHARED_CACHE_SIZE_HALF (SHARED_CACHE_SIZE / 2)
#define DATA_CACHE_SIZE_HALF (DATA_CACHE_SIZE / 2)