Merge "MIPS: dspr2: Added optimization for MultARGBRow function"
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@ -79,6 +79,51 @@ static int DispatchAlpha(const uint8_t* alpha, int alpha_stride,
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return (alpha_mask != 0xff);
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}
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static void MultARGBRow(uint32_t* const ptr, int width, int inverse) {
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int x;
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const uint32_t c_00ffffff = 0x00ffffffu;
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const uint32_t c_ff000000 = 0xff000000u;
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const uint32_t c_8000000 = 0x00800000u;
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const uint32_t c_8000080 = 0x00800080u;
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for (x = 0; x < width; ++x) {
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const uint32_t argb = ptr[x];
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if (argb < 0xff000000u) { // alpha < 255
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if (argb <= 0x00ffffffu) { // alpha == 0
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ptr[x] = 0;
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} else {
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int temp0, temp1, temp2, temp3, alpha;
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__asm__ volatile (
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"srl %[alpha], %[argb], 24 \n\t"
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"replv.qb %[temp0], %[alpha] \n\t"
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"and %[temp0], %[temp0], %[c_00ffffff] \n\t"
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"beqz %[inverse], 0f \n\t"
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"divu $zero, %[c_ff000000], %[alpha] \n\t"
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"mflo %[temp0] \n\t"
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"0: \n\t"
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"andi %[temp1], %[argb], 0xff \n\t"
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"ext %[temp2], %[argb], 8, 8 \n\t"
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"ext %[temp3], %[argb], 16, 8 \n\t"
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"mul %[temp1], %[temp1], %[temp0] \n\t"
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"mul %[temp2], %[temp2], %[temp0] \n\t"
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"mul %[temp3], %[temp3], %[temp0] \n\t"
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"precrq.ph.w %[temp1], %[temp2], %[temp1] \n\t"
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"addu %[temp3], %[temp3], %[c_8000000] \n\t"
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"addu %[temp1], %[temp1], %[c_8000080] \n\t"
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"precrq.ph.w %[temp3], %[argb], %[temp3] \n\t"
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"precrq.qb.ph %[temp1], %[temp3], %[temp1] \n\t"
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: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),
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[temp3]"=&r"(temp3), [alpha]"=&r"(alpha)
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: [inverse]"r"(inverse), [c_00ffffff]"r"(c_00ffffff),
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[c_8000000]"r"(c_8000000), [c_8000080]"r"(c_8000080),
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[c_ff000000]"r"(c_ff000000), [argb]"r"(argb)
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: "memory", "hi", "lo"
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);
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ptr[x] = temp1;
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}
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}
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}
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}
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#endif // WEBP_USE_MIPS_DSP_R2
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//------------------------------------------------------------------------------
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@ -89,5 +134,6 @@ extern void WebPInitAlphaProcessingMIPSdspR2(void);
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void WebPInitAlphaProcessingMIPSdspR2(void) {
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#if defined(WEBP_USE_MIPS_DSP_R2)
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WebPDispatchAlpha = DispatchAlpha;
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WebPMultARGBRow = MultARGBRow;
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#endif
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}
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