94c52e4da8
When the license headers were updated, they accidentally contained trailing whitespace, so unfortunately we have to touch all the files again. Change-Id: I236c05fade06589e417179c0444cb39b09e4200d
97 lines
2.4 KiB
NASM
97 lines
2.4 KiB
NASM
;
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; Copyright (c) 2010 The VP8 project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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EXPORT |vp8_short_inv_walsh4x4_neon|
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EXPORT |vp8_short_inv_walsh4x4_1_neon|
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ARM
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REQUIRE8
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PRESERVE8
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AREA |.text|, CODE, READONLY ; name this block of code
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;short vp8_short_inv_walsh4x4_neon(short *input, short *output)
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|vp8_short_inv_walsh4x4_neon| PROC
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; read in all four lines of values: d0->d3
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vldm.64 r0, {q0, q1}
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; first for loop
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vadd.s16 d4, d0, d3 ;a = [0] + [12]
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vadd.s16 d5, d1, d2 ;b = [4] + [8]
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vsub.s16 d6, d1, d2 ;c = [4] - [8]
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vsub.s16 d7, d0, d3 ;d = [0] - [12]
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vadd.s16 d0, d4, d5 ;a + b
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vadd.s16 d1, d6, d7 ;c + d
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vsub.s16 d2, d4, d5 ;a - b
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vsub.s16 d3, d7, d6 ;d - c
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vtrn.32 d0, d2 ;d0: 0 1 8 9
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;d2: 2 3 10 11
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vtrn.32 d1, d3 ;d1: 4 5 12 13
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;d3: 6 7 14 15
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vtrn.16 d0, d1 ;d0: 0 4 8 12
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;d1: 1 5 9 13
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vtrn.16 d2, d3 ;d2: 2 6 10 14
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;d3: 3 7 11 15
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; second for loop
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vadd.s16 d4, d0, d3 ;a = [0] + [3]
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vadd.s16 d5, d1, d2 ;b = [1] + [2]
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vsub.s16 d6, d1, d2 ;c = [1] - [2]
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vsub.s16 d7, d0, d3 ;d = [0] - [3]
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vadd.s16 d0, d4, d5 ;e = a + b
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vadd.s16 d1, d6, d7 ;f = c + d
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vsub.s16 d2, d4, d5 ;g = a - b
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vsub.s16 d3, d7, d6 ;h = d - c
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vmov.i16 q2, #3
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vadd.i16 q0, q0, q2 ;e/f += 3
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vadd.i16 q1, q1, q2 ;g/h += 3
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vshr.s16 q0, q0, #3 ;e/f >> 3
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vshr.s16 q1, q1, #3 ;g/h >> 3
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vtrn.32 d0, d2
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vtrn.32 d1, d3
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vtrn.16 d0, d1
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vtrn.16 d2, d3
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vstmia.16 r1!, {q0}
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vstmia.16 r1!, {q1}
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bx lr
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ENDP ; |vp8_short_inv_walsh4x4_neon|
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;short vp8_short_inv_walsh4x4_1_neon(short *input, short *output)
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|vp8_short_inv_walsh4x4_1_neon| PROC
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; load a full line into a neon register
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vld1.16 {q0}, [r0]
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; extract first element and replicate
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vdup.16 q1, d0[0]
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; add 3 to all values
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vmov.i16 q2, #3
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vadd.i16 q3, q1, q2
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; right shift
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vshr.s16 q3, q3, #3
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; write it back
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vstmia.16 r1!, {q3}
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vstmia.16 r1!, {q3}
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bx lr
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ENDP ; |vp8_short_inv_walsh4x4_1_neon|
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END
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