Change 72141 introduced a new use of vp9_avg_4x4.
This call needs to switch to using vp9_highbd_avg_4x4
when performing high bitdepth encodes.
Change-Id: I6a8ba4b62f8a75d0a917b365a55245e2f0438ea1
When multiple intra modes are tested, the previous mode info
update process may overwrite the selected best intra mode and make
the final selection use an inter mode. This commit fixes this
issue by moving the mode_info reset outside the intra mode search
loop.
Change-Id: I15ed4288a6b3cb0832104a5e6d5d9a25cd1a5b2b
If vp9_pick_inter_mode works properly, it should at least check
one coding mode and hence get best_tx_size assigned a valid value.
There is no need to initialize best_tx_size with a legitimate
value before starting the mode search.
Change-Id: Ic0496cd89672ea9c2c512a9bd1da952190af9cba
Make the variable reduction_fac log2 based and explicitly use
right shift when computing intra_cost_penalty.
Change-Id: I208f1fb879a02debb3b3fc64f9fd06260dcf1c86
This reverts commit 91471d6aad285ff10e7582e485d8adadd1986fe2.
Fixes the compile issues if post_proc is enabled.
Change-Id: Ib40a15ce2c194f9b5adfa65a17ab01ddf60f5a59
Add vp9_iht8x8_add_neon.c
- vp9_iht8x8_64_add_neon
The assembly did not previously implement tx_type 0
BUG=716
Change-Id: Icfc99dd24f3d59047f9184a7d0c761ba7e3de934
Signed-off-by: James Yu <james.yu@linaro.org>
Add vp9_iht4x4_add_neon.c
- vp9_iht4x4_16_add_neon
The assembly did not previously implement tx_type 0
BUG=715
Change-Id: I60034d1568de034edba45c5cdd13f3d87dbc73b6
Signed-off-by: James Yu <james.yu@linaro.org>
Fails to compile. Bad calls to vp9_alloc_frame_buffer
and vp9_realloc_frame_buffer in postproc.c
This reverts commit 399823b6f50fb7465f62822d1395e2192e7b07fc.
Change-Id: I29f0e173f8e185d3a303cfdb17813e1eccb51e3a
Allows override of default target list. Also added missing usage info
for --extra-configure-args, and removed last vestiges of armv6 support.
Change-Id: Ic0f14fffa0cbaea1bed371d38ff65e035bbe3273
Add support for setting byte alignment on the Y, U, and V plane of the
reference buffers. The byte alignment must be a power of 2, from 32 to
1024. A value of 0 sets legacy alignment.
Change-Id: I7c1399622f7aa68e123646369216b32047dda73d
INLINE is used quite widely in vp9, this change improves performance
1-2% on most modern platforms.
Change-Id: I8a9974aab89fa588ea4923cc7eaf6199e344a528
the entire module is wrapped in CONFIG_VP9_POSTPROC which is forcibly
enabled with CONFIG_INTERNAL_STATS
+ a similar change in vp9_alloccommon.c
Change-Id: I374993297a9fba5bef2f0b71f984eba42f0995a3
set LIBVPX_RAND with --enable-vp9-postproc, previously only the vp8
config was checked. this fixes the build with --disable-postproc.
Change-Id: Ia61baded6aa0e44d6443ae4a3c85915f1054f053
Assembly tests should clear system state, as we have no
expectation of proper system state in between test runs..
Change-Id: I0f591996c1f17ef2a5a8572a6b445f757223a144
