7018 Commits

Author SHA1 Message Date
Frank Galligan
5fdd0f1fe0 Merge "Revert "Revert "Add support for setting byte alignment.""" 2014-12-16 15:14:17 -08:00
James Yu
ba05a4c640 VP9 common for ARMv8 by using NEON intrinsics 19
Delete vp9_dc_only_idct_add_neon.c

The function was merged with vp9_short_idct4x4_1_add (later
vp9_idct4x4_1_add) in d2de1ca and should have been deleted then.

Change-Id: Ie58ba3dd9dc7330a8f1238dd7dd71c9ed4639b94
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-16 11:14:12 -08:00
JackyChen
603cdcfce5 Merge "Fixed MFQE crash issue for highbit depth." 2014-12-16 11:12:03 -08:00
JackyChen
e7bad92689 Fixed MFQE crash issue for highbit depth.
Check the flags, no MFQE for highbit now. Will add highbit support
latter.

Change-Id: I548c27593e0f47ab7f4c92b45f14fb037dc86591
2014-12-16 10:07:38 -08:00
Jingning Han
581c8dbd33 Merge "Initialize best_tx_size with invalid value" 2014-12-16 10:01:03 -08:00
Yaowu Xu
b60ae45f36 Merge "Prevent decoder from using uninitialized entropy context." 2014-12-16 09:30:24 -08:00
Jingning Han
b47f9c5802 Merge "Use right shift to replace division in vp9_pick_inter_mode" 2014-12-16 09:26:51 -08:00
Debargha Mukherjee
4ebdb4a1b9 Merge "Fix for crash in highbitdepth rt mode" 2014-12-16 06:41:54 -08:00
Jim Bankoski
abc5a66770 Merge "Fix the comments." 2014-12-16 06:25:01 -08:00
Peter de Rivaz
e3d19bfc63 Fix for crash in highbitdepth rt mode
Change 72141 introduced a new use of vp9_avg_4x4.
This call needs to switch to using vp9_highbd_avg_4x4
when performing high bitdepth encodes.

Change-Id: I6a8ba4b62f8a75d0a917b365a55245e2f0438ea1
2014-12-16 10:55:49 +00:00
Johann
1d059fa23e Merge "VP9 common for ARMv8 by using NEON intrinsics 06" 2014-12-15 14:49:33 -08:00
Johann
37ea1e1218 Merge "VP9 common for ARMv8 by using NEON intrinsics 05" 2014-12-15 14:48:53 -08:00
Jingning Han
5c93dca3d3 Merge "Simplify rate-distortion modeling function" 2014-12-15 14:37:19 -08:00
Jingning Han
c2c7596fc7 Initialize best_tx_size with invalid value
If vp9_pick_inter_mode works properly, it should at least check
one coding mode and hence get best_tx_size assigned a valid value.
There is no need to initialize best_tx_size with a legitimate
value before starting the mode search.

Change-Id: Ic0496cd89672ea9c2c512a9bd1da952190af9cba
2014-12-15 12:58:34 -08:00
Jingning Han
83e2c62aba Use right shift to replace division in vp9_pick_inter_mode
Make the variable reduction_fac log2 based and explicitly use
right shift when computing intra_cost_penalty.

Change-Id: I208f1fb879a02debb3b3fc64f9fd06260dcf1c86
2014-12-15 12:48:07 -08:00
Frank Galligan
c4f7079ad4 Revert "Revert "Add support for setting byte alignment.""
This reverts commit 91471d6aad285ff10e7582e485d8adadd1986fe2.

Fixes the compile issues if post_proc is enabled.

Change-Id: Ib40a15ce2c194f9b5adfa65a17ab01ddf60f5a59
2014-12-15 12:20:37 -08:00
James Yu
4f856cd7fa VP9 common for ARMv8 by using NEON intrinsics 06
Add vp9_iht8x8_add_neon.c
- vp9_iht8x8_64_add_neon

The assembly did not previously implement tx_type 0
BUG=716

Change-Id: Icfc99dd24f3d59047f9184a7d0c761ba7e3de934
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-15 12:18:06 -08:00
James Yu
6b71013277 VP9 common for ARMv8 by using NEON intrinsics 05
Add vp9_iht4x4_add_neon.c
- vp9_iht4x4_16_add_neon

The assembly did not previously implement tx_type 0
BUG=715

Change-Id: I60034d1568de034edba45c5cdd13f3d87dbc73b6
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-15 12:16:19 -08:00
James Zern
8d558f2ca5 Merge "vp9/MACROBLOCKD: reorder struct members" 2014-12-15 11:54:51 -08:00
Jingning Han
eefe869291 Simplify rate-distortion modeling function
Use left shift to replace one multiplication. The computation
outcome remains identical.

Change-Id: I1e1737af0a245de0d2a2bde10f0c171477199fc1
2014-12-15 11:51:16 -08:00
Paul Wilkins
91471d6aad Revert "Add support for setting byte alignment."
Fails to compile. Bad calls to vp9_alloc_frame_buffer
and vp9_realloc_frame_buffer in postproc.c

This reverts commit 399823b6f50fb7465f62822d1395e2192e7b07fc.

Change-Id: I29f0e173f8e185d3a303cfdb17813e1eccb51e3a
2014-12-15 11:54:13 +00:00
James Zern
c58c579ec4 vp9/MACROBLOCKD: reorder struct members
improves locality of reference

Change-Id: I0639b98bf38879f918173b3a1b25dd93090e88b4
2014-12-12 18:01:24 -08:00
James Zern
089086bc25 Merge "Optimize bit_read_buffer." 2014-12-12 16:29:42 -08:00
Frank Galligan
9c2601eb68 Merge "Add support for setting byte alignment." 2014-12-12 15:47:11 -08:00
hkuang
3cecce916b Optimize bit_read_buffer.
Change-Id: Iee43c34909deec9787b29c1c33672213b9f049df
2014-12-12 14:38:12 -08:00
James Zern
89ee8923a8 Merge "Remove redundant loads on 1d16_v8 filter." 2014-12-12 14:32:52 -08:00
James Zern
f82d7fd854 Merge "Remove redundant loads on 1d8_v8 filter." 2014-12-12 14:32:26 -08:00
James Zern
4d40a046da Merge "vp9: move encoder-only member from common" 2014-12-12 14:28:55 -08:00
James Zern
2bf4b4852f Merge changes Id6421838,I37499329
* changes:
  vp9: make postproc members depend on CONFIG_VP9_POSTPROC
  vp9_postproc: remove redundant CONFIG_* checks
2014-12-12 14:27:56 -08:00
Marco
7f59cff53d Merge "Allow for 4x4 prediction blocks for key frame, speed 6." 2014-12-12 14:27:31 -08:00
James Zern
5ccff43292 Merge "vp9_loopfilter_mmx: remove some unused tables" 2014-12-12 14:25:53 -08:00
Frank Galligan
399823b6f5 Add support for setting byte alignment.
Add support for setting byte alignment on the Y, U, and V plane of the
reference buffers. The byte alignment must be a power of 2, from 32 to
1024. A value of 0 sets legacy alignment.

Change-Id: I7c1399622f7aa68e123646369216b32047dda73d
2014-12-12 13:34:36 -08:00
James Zern
6d1a63a02a Merge "Remove unnecessary dqcoeff memset." 2014-12-12 12:16:32 -08:00
Frank Galligan
6a24dbd71f Remove redundant loads on 1d16_v8 filter.
This CL showed about a 3% gain in performance on some systems.

Change-Id: Id27e7e0b8e69068aa364e67859436da852669250
2014-12-12 11:48:47 -08:00
Frank Galligan
44ee777905 Remove redundant loads on 1d8_v8 filter.
This CL showed a modest gain in performance on some systems.

Change-Id: Iad636a89a1a9804ab7a0dea302bf2c6a4d1653a4
2014-12-12 11:34:24 -08:00
James Zern
72ece1308b vp9: move encoder-only member from common
allow_comp_inter_inter VP9_COMMON -> VP9_COMP

Change-Id: I6d9dc25d1cdd7e2ab62f5be69cd9fa883d21dbb6
2014-12-12 11:17:44 -08:00
James Zern
ef06de33fe vp9: make postproc members depend on CONFIG_VP9_POSTPROC
Change-Id: Id64218386968cee3132269e4a0572650f20fd980
2014-12-12 11:17:17 -08:00
James Zern
890f7bedf3 vp9_postproc: remove redundant CONFIG_* checks
the entire module is wrapped in CONFIG_VP9_POSTPROC which is forcibly
enabled with CONFIG_INTERNAL_STATS

+ a similar change in vp9_alloccommon.c

Change-Id: I374993297a9fba5bef2f0b71f984eba42f0995a3
2014-12-12 11:17:16 -08:00
James Zern
d456ccbc9d vp9_loopfilter_mmx: remove some unused tables
Change-Id: I964d25cc91c8e4864d73b142d9c7a1b39cb6cfbb
2014-12-12 11:16:24 -08:00
Jim Bankoski
d916b0f22f Merge "vp9_dx_iface.c uses CONFIG_VP9_POSTPROC but config.h not included" 2014-12-12 11:10:17 -08:00
Jingning Han
3e0793b80b Merge "Fix PICK_MODE_CONTEXT index in non-RD coding mode" 2014-12-12 09:16:01 -08:00
Jim Bankoski
c67859f737 vp9_dx_iface.c uses CONFIG_VP9_POSTPROC but config.h not included
Change-Id: Id316b3786214bf1028992968955da917e3f2d4a3
2014-12-12 08:42:36 -08:00
Jingning Han
e2c2a65695 Fix PICK_MODE_CONTEXT index in non-RD coding mode
This commit fixes a bug in the PICK_MODE_CONTEXT index for
horizontal partition case. The compression performance change
is less than 0.01% level, since most blocks are selected to
use square block size in RTC coding mode.

Change-Id: I67effc18ae8795fccdd82a55f4efc609fa5cb3e1
2014-12-11 17:21:24 -08:00
JackyChen
3425d6c83e Merge "Multiframe Quality Enhancement(MFQE) in VP9." 2014-12-11 16:24:08 -08:00
Marco
7e99cd2a9b Allow for 4x4 prediction blocks for key frame, speed 6.
For key frame under variance source partition: 4x4 prediction blocks
may be selected when variance of 8x8 block is very high (threshold is set fairly high for now).

Testing on some RTC clips shows this helps to reduce some ringing artifacts on key frame.
Encoded key frame size increases about ~10%. Key frame PSNR increases about ~0.1-0.2dB.

Change-Id: I56e203fac32ea6ef69897fb3ea269c59cb50d174
2014-12-11 15:36:16 -08:00
Jingning Han
811c74cdfa Merge "Replace division with bit shift in choose_partitioning" 2014-12-11 13:30:03 -08:00
Debargha Mukherjee
dd33c656da Merge "Corrected optimization of 8x8 DCT code" 2014-12-11 12:28:45 -08:00
hkuang
3c7a06c3cc Remove unnecessary dqcoeff memset.
dqcoeff is set to be 0 on initialization. And set back to 0 after being
used everytime.

Change-Id: I32b8e149bba40a8d707849f737a8e49a691f319c
2014-12-11 12:27:25 -08:00
Jingning Han
d9892e846f Merge "Refactor choose_partitioning computing scheme" 2014-12-11 11:14:07 -08:00
Jingning Han
d5c396a902 Replace division with bit shift in choose_partitioning
This commit explicitly uses the bit shift operation instead of
division for computing block variance.

Change-Id: Id19c0ff27dd1d1ae4aceee6657e1aad0d406bd74
2014-12-11 11:06:57 -08:00