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Merge "Fit adst/dct's stage range into 32-bit in bd12" into nextgenv2

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This commit is contained in:
Angie Chiang
2016-04-18 18:40:28 +00:00
committed by Gerrit Code Review
parent cf3ef18fc4 02d23fbbf4
commit d72560e10d
4 changed files with 311 additions and 252 deletions
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27
vp10/common/idct.c
View File

@@ -1306,9 +1306,16 @@ void vp10_highbd_inv_txfm_add_4x4(const tran_low_t *input, uint8_t *dest,
&inv_txfm_2d_cfg_dct_dct_4, bd);
break;
case ADST_DCT:
vp10_inv_txfm2d_add_4x4(input, CONVERT_TO_SHORTPTR(dest), stride,
&inv_txfm_2d_cfg_adst_dct_4, bd);
break;
case DCT_ADST:
vp10_inv_txfm2d_add_4x4(input, CONVERT_TO_SHORTPTR(dest), stride,
&inv_txfm_2d_cfg_dct_adst_4, bd);
break;
case ADST_ADST:
vp10_highbd_iht4x4_16_add(input, dest, stride, tx_type, bd);
vp10_inv_txfm2d_add_4x4(input, CONVERT_TO_SHORTPTR(dest), stride,
&inv_txfm_2d_cfg_adst_adst_4, bd);
break;
#if CONFIG_EXT_TX
case FLIPADST_DCT:
@@ -1347,9 +1354,16 @@ void vp10_highbd_inv_txfm_add_8x8(const tran_low_t *input, uint8_t *dest,
&inv_txfm_2d_cfg_dct_dct_8, bd);
break;
case ADST_DCT:
vp10_inv_txfm2d_add_8x8(input, CONVERT_TO_SHORTPTR(dest), stride,
&inv_txfm_2d_cfg_adst_dct_8, bd);
break;
case DCT_ADST:
vp10_inv_txfm2d_add_8x8(input, CONVERT_TO_SHORTPTR(dest), stride,
&inv_txfm_2d_cfg_dct_adst_8, bd);
break;
case ADST_ADST:
vp10_highbd_iht8x8_64_add(input, dest, stride, tx_type, bd);
vp10_inv_txfm2d_add_8x8(input, CONVERT_TO_SHORTPTR(dest), stride,
&inv_txfm_2d_cfg_adst_adst_8, bd);
break;
#if CONFIG_EXT_TX
case FLIPADST_DCT:
@@ -1388,9 +1402,16 @@ void vp10_highbd_inv_txfm_add_16x16(const tran_low_t *input, uint8_t *dest,
&inv_txfm_2d_cfg_dct_dct_16, bd);
break;
case ADST_DCT:
vp10_inv_txfm2d_add_16x16(input, CONVERT_TO_SHORTPTR(dest), stride,
&inv_txfm_2d_cfg_adst_dct_16, bd);
break;
case DCT_ADST:
vp10_inv_txfm2d_add_16x16(input, CONVERT_TO_SHORTPTR(dest), stride,
&inv_txfm_2d_cfg_dct_adst_16, bd);
break;
case ADST_ADST:
vp10_highbd_iht16x16_256_add(input, dest, stride, tx_type, bd);
vp10_inv_txfm2d_add_16x16(input, CONVERT_TO_SHORTPTR(dest), stride,
&inv_txfm_2d_cfg_adst_adst_16, bd);
break;
#if CONFIG_EXT_TX
case FLIPADST_DCT:

243
vp10/common/vp10_fwd_txfm2d_cfg.h
View File

@@ -123,17 +123,18 @@ static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_dct_64 = {
TXFM_TYPE_DCT64}; // .txfm_type_row
// ---------------- config fwd_dct_adst_4 ----------------
static const int8_t fwd_shift_dct_adst_4[3] = {5, -2, -1};
static const int8_t fwd_stage_range_col_dct_adst_4[4] = {16, 17, 18, 18};
static const int8_t fwd_stage_range_row_dct_adst_4[6] = {16, 16, 16,
17, 17, 17};
static const int8_t fwd_cos_bit_col_dct_adst_4[4] = {15, 15, 14, 14};
static const int8_t fwd_cos_bit_row_dct_adst_4[6] = {15, 15, 15, 15, 15, 15};
static const int8_t fwd_shift_dct_adst_4[3] = {2, 0, 0};
static const int8_t fwd_stage_range_col_dct_adst_4[4] = {15, 16, 17, 17};
static const int8_t fwd_stage_range_row_dct_adst_4[6] = {17, 17, 17,
18, 18, 18};
static const int8_t fwd_cos_bit_col_dct_adst_4[4] = {13, 13, 13, 13};
static const int8_t fwd_cos_bit_row_dct_adst_4[6] = {13, 13, 13, 13, 13, 13};
static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_adst_4 = {
4, // .txfm_size
4, // .stage_num_col
6, // .stage_num_row
4, // .txfm_size
4, // .stage_num_col
6, // .stage_num_row
// 0, // .log_scale
fwd_shift_dct_adst_4, // .shift
fwd_stage_range_col_dct_adst_4, // .stage_range_col
fwd_stage_range_row_dct_adst_4, // .stage_range_row
@@ -143,19 +144,20 @@ static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_adst_4 = {
TXFM_TYPE_ADST4}; // .txfm_type_row
// ---------------- config fwd_dct_adst_8 ----------------
static const int8_t fwd_shift_dct_adst_8[3] = {7, -3, -3};
static const int8_t fwd_stage_range_col_dct_adst_8[6] = {18, 19, 20,
21, 21, 21};
static const int8_t fwd_shift_dct_adst_8[3] = {3, -1, -1};
static const int8_t fwd_stage_range_col_dct_adst_8[6] = {16, 17, 18,
19, 19, 19};
static const int8_t fwd_stage_range_row_dct_adst_8[8] = {18, 18, 18, 19,
19, 20, 20, 20};
static const int8_t fwd_cos_bit_col_dct_adst_8[6] = {14, 13, 12, 11, 11, 11};
static const int8_t fwd_cos_bit_row_dct_adst_8[8] = {14, 14, 14, 13,
static const int8_t fwd_cos_bit_col_dct_adst_8[6] = {13, 13, 13, 13, 13, 13};
static const int8_t fwd_cos_bit_row_dct_adst_8[8] = {13, 13, 13, 13,
13, 12, 12, 12};
static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_adst_8 = {
8, // .txfm_size
6, // .stage_num_col
8, // .stage_num_row
8, // .txfm_size
6, // .stage_num_col
8, // .stage_num_row
// 0, // .log_scale
fwd_shift_dct_adst_8, // .shift
fwd_stage_range_col_dct_adst_8, // .stage_range_col
fwd_stage_range_row_dct_adst_8, // .stage_range_row
@@ -165,20 +167,21 @@ static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_adst_8 = {
TXFM_TYPE_ADST8}; // .txfm_type_row
// ---------------- config fwd_dct_adst_16 ----------------
static const int8_t fwd_shift_dct_adst_16[3] = {4, -1, -3};
static const int8_t fwd_shift_dct_adst_16[3] = {2, -2, 0};
static const int8_t fwd_stage_range_col_dct_adst_16[8] = {15, 16, 17, 18,
19, 19, 19, 19};
static const int8_t fwd_stage_range_row_dct_adst_16[10] = {18, 18, 18, 19, 19,
20, 20, 21, 21, 21};
static const int8_t fwd_cos_bit_col_dct_adst_16[8] = {15, 15, 15, 14,
static const int8_t fwd_stage_range_row_dct_adst_16[10] = {17, 17, 17, 18, 18,
19, 19, 20, 20, 20};
static const int8_t fwd_cos_bit_col_dct_adst_16[8] = {13, 13, 13, 13,
13, 13, 13, 13};
static const int8_t fwd_cos_bit_row_dct_adst_16[10] = {14, 14, 14, 13, 13,
12, 12, 11, 11, 11};
static const int8_t fwd_cos_bit_row_dct_adst_16[10] = {13, 13, 13, 13, 13,
13, 13, 12, 12, 12};
static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_adst_16 = {
16, // .txfm_size
8, // .stage_num_col
10, // .stage_num_row
16, // .txfm_size
8, // .stage_num_col
10, // .stage_num_row
// 0, // .log_scale
fwd_shift_dct_adst_16, // .shift
fwd_stage_range_col_dct_adst_16, // .stage_range_col
fwd_stage_range_row_dct_adst_16, // .stage_range_row
@@ -188,20 +191,21 @@ static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_adst_16 = {
TXFM_TYPE_ADST16}; // .txfm_type_row
// ---------------- config fwd_dct_adst_32 ----------------
static const int8_t fwd_shift_dct_adst_32[3] = {3, -1, -3};
static const int8_t fwd_stage_range_col_dct_adst_32[10] = {14, 15, 16, 17, 18,
19, 19, 19, 19, 19};
static const int8_t fwd_shift_dct_adst_32[3] = {2, -4, 0};
static const int8_t fwd_stage_range_col_dct_adst_32[10] = {15, 16, 17, 18, 19,
20, 20, 20, 20, 20};
static const int8_t fwd_stage_range_row_dct_adst_32[12] = {
18, 18, 18, 19, 19, 20, 20, 21, 21, 22, 22, 22};
static const int8_t fwd_cos_bit_col_dct_adst_32[10] = {15, 15, 15, 15, 14,
13, 13, 13, 13, 13};
static const int8_t fwd_cos_bit_row_dct_adst_32[12] = {14, 14, 14, 13, 13, 12,
12, 11, 11, 10, 10, 10};
16, 16, 16, 17, 17, 18, 18, 19, 19, 20, 20, 20};
static const int8_t fwd_cos_bit_col_dct_adst_32[10] = {13, 13, 13, 13, 13,
12, 12, 12, 12, 12};
static const int8_t fwd_cos_bit_row_dct_adst_32[12] = {13, 13, 13, 13, 13, 13,
13, 13, 13, 12, 12, 12};
static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_adst_32 = {
32, // .txfm_size
10, // .stage_num_col
12, // .stage_num_row
32, // .txfm_size
10, // .stage_num_col
12, // .stage_num_row
// 1, // .log_scale
fwd_shift_dct_adst_32, // .shift
fwd_stage_range_col_dct_adst_32, // .stage_range_col
fwd_stage_range_row_dct_adst_32, // .stage_range_row
@@ -209,20 +213,20 @@ static const TXFM_2D_CFG fwd_txfm_2d_cfg_dct_adst_32 = {
fwd_cos_bit_row_dct_adst_32, // .cos_bit_row
TXFM_TYPE_DCT32, // .txfm_type_col
TXFM_TYPE_ADST32}; // .txfm_type_row
// ---------------- config fwd_adst_adst_4 ----------------
static const int8_t fwd_shift_adst_adst_4[3] = {6, 1, -5};
static const int8_t fwd_stage_range_col_adst_adst_4[6] = {17, 17, 18,
19, 19, 19};
static const int8_t fwd_stage_range_row_adst_adst_4[6] = {20, 20, 20,
21, 21, 21};
static const int8_t fwd_cos_bit_col_adst_adst_4[6] = {15, 15, 14, 13, 13, 13};
static const int8_t fwd_cos_bit_row_adst_adst_4[6] = {12, 12, 12, 11, 11, 11};
static const int8_t fwd_shift_adst_adst_4[3] = {2, 0, 0};
static const int8_t fwd_stage_range_col_adst_adst_4[6] = {15, 15, 16,
17, 17, 17};
static const int8_t fwd_stage_range_row_adst_adst_4[6] = {17, 17, 17,
18, 18, 18};
static const int8_t fwd_cos_bit_col_adst_adst_4[6] = {13, 13, 13, 13, 13, 13};
static const int8_t fwd_cos_bit_row_adst_adst_4[6] = {13, 13, 13, 13, 13, 13};
static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_adst_4 = {
4, // .txfm_size
6, // .stage_num_col
6, // .stage_num_row
4, // .txfm_size
6, // .stage_num_col
6, // .stage_num_row
// 0, // .log_scale
fwd_shift_adst_adst_4, // .shift
fwd_stage_range_col_adst_adst_4, // .stage_range_col
fwd_stage_range_row_adst_adst_4, // .stage_range_row
@@ -233,19 +237,20 @@ static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_adst_4 = {
// ---------------- config fwd_adst_adst_8 ----------------
static const int8_t fwd_shift_adst_adst_8[3] = {3, -1, -1};
static const int8_t fwd_stage_range_col_adst_adst_8[8] = {14, 14, 15, 16,
16, 17, 17, 17};
static const int8_t fwd_stage_range_row_adst_adst_8[8] = {16, 16, 16, 17,
17, 18, 18, 18};
static const int8_t fwd_cos_bit_col_adst_adst_8[8] = {15, 15, 15, 15,
15, 15, 15, 15};
static const int8_t fwd_cos_bit_row_adst_adst_8[8] = {15, 15, 15, 15,
15, 14, 14, 14};
static const int8_t fwd_stage_range_col_adst_adst_8[8] = {16, 16, 17, 18,
18, 19, 19, 19};
static const int8_t fwd_stage_range_row_adst_adst_8[8] = {18, 18, 18, 19,
19, 20, 20, 20};
static const int8_t fwd_cos_bit_col_adst_adst_8[8] = {13, 13, 13, 13,
13, 13, 13, 13};
static const int8_t fwd_cos_bit_row_adst_adst_8[8] = {13, 13, 13, 13,
13, 12, 12, 12};
static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_adst_8 = {
8, // .txfm_size
8, // .stage_num_col
8, // .stage_num_row
8, // .txfm_size
8, // .stage_num_col
8, // .stage_num_row
// 0, // .log_scale
fwd_shift_adst_adst_8, // .shift
fwd_stage_range_col_adst_adst_8, // .stage_range_col
fwd_stage_range_row_adst_adst_8, // .stage_range_row
@@ -255,20 +260,21 @@ static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_adst_8 = {
TXFM_TYPE_ADST8}; // .txfm_type_row
// ---------------- config fwd_adst_adst_16 ----------------
static const int8_t fwd_shift_adst_adst_16[3] = {2, 0, -2};
static const int8_t fwd_stage_range_col_adst_adst_16[10] = {13, 13, 14, 15, 15,
16, 16, 17, 17, 17};
static const int8_t fwd_shift_adst_adst_16[3] = {2, -2, 0};
static const int8_t fwd_stage_range_col_adst_adst_16[10] = {15, 15, 16, 17, 17,
18, 18, 19, 19, 19};
static const int8_t fwd_stage_range_row_adst_adst_16[10] = {17, 17, 17, 18, 18,
19, 19, 20, 20, 20};
static const int8_t fwd_cos_bit_col_adst_adst_16[10] = {15, 15, 15, 15, 15,
15, 15, 15, 15, 15};
static const int8_t fwd_cos_bit_row_adst_adst_16[10] = {15, 15, 15, 14, 14,
static const int8_t fwd_cos_bit_col_adst_adst_16[10] = {13, 13, 13, 13, 13,
13, 13, 13, 13, 13};
static const int8_t fwd_cos_bit_row_adst_adst_16[10] = {13, 13, 13, 13, 13,
13, 13, 12, 12, 12};
static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_adst_16 = {
16, // .txfm_size
10, // .stage_num_col
10, // .stage_num_row
16, // .txfm_size
10, // .stage_num_col
10, // .stage_num_row
// 0, // .log_scale
fwd_shift_adst_adst_16, // .shift
fwd_stage_range_col_adst_adst_16, // .stage_range_col
fwd_stage_range_row_adst_adst_16, // .stage_range_row
@@ -278,20 +284,21 @@ static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_adst_16 = {
TXFM_TYPE_ADST16}; // .txfm_type_row
// ---------------- config fwd_adst_adst_32 ----------------
static const int8_t fwd_shift_adst_adst_32[3] = {4, -2, -3};
static const int8_t fwd_shift_adst_adst_32[3] = {2, -4, 0};
static const int8_t fwd_stage_range_col_adst_adst_32[12] = {
15, 15, 16, 17, 17, 18, 18, 19, 19, 20, 20, 20};
static const int8_t fwd_stage_range_row_adst_adst_32[12] = {
18, 18, 18, 19, 19, 20, 20, 21, 21, 22, 22, 22};
static const int8_t fwd_cos_bit_col_adst_adst_32[12] = {15, 15, 15, 15, 15, 14,
14, 13, 13, 12, 12, 12};
static const int8_t fwd_cos_bit_row_adst_adst_32[12] = {14, 14, 14, 13, 13, 12,
12, 11, 11, 10, 10, 10};
16, 16, 16, 17, 17, 18, 18, 19, 19, 20, 20, 20};
static const int8_t fwd_cos_bit_col_adst_adst_32[12] = {13, 13, 13, 13, 13, 13,
13, 13, 13, 12, 12, 12};
static const int8_t fwd_cos_bit_row_adst_adst_32[12] = {13, 13, 13, 13, 13, 13,
13, 13, 13, 12, 12, 12};
static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_adst_32 = {
32, // .txfm_size
12, // .stage_num_col
12, // .stage_num_row
32, // .txfm_size
12, // .stage_num_col
12, // .stage_num_row
// 1, // .log_scale
fwd_shift_adst_adst_32, // .shift
fwd_stage_range_col_adst_adst_32, // .stage_range_col
fwd_stage_range_row_adst_adst_32, // .stage_range_row
@@ -301,17 +308,18 @@ static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_adst_32 = {
TXFM_TYPE_ADST32}; // .txfm_type_row
// ---------------- config fwd_adst_dct_4 ----------------
static const int8_t fwd_shift_adst_dct_4[3] = {5, -4, 1};
static const int8_t fwd_stage_range_col_adst_dct_4[6] = {16, 16, 17,
18, 18, 18};
static const int8_t fwd_stage_range_row_adst_dct_4[4] = {14, 15, 15, 15};
static const int8_t fwd_cos_bit_col_adst_dct_4[6] = {15, 15, 15, 14, 14, 14};
static const int8_t fwd_cos_bit_row_adst_dct_4[4] = {15, 15, 15, 15};
static const int8_t fwd_shift_adst_dct_4[3] = {2, 0, 0};
static const int8_t fwd_stage_range_col_adst_dct_4[6] = {15, 15, 16,
17, 17, 17};
static const int8_t fwd_stage_range_row_adst_dct_4[4] = {17, 18, 18, 18};
static const int8_t fwd_cos_bit_col_adst_dct_4[6] = {13, 13, 13, 13, 13, 13};
static const int8_t fwd_cos_bit_row_adst_dct_4[4] = {13, 13, 13, 13};
static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_dct_4 = {
4, // .txfm_size
6, // .stage_num_col
4, // .stage_num_row
4, // .txfm_size
6, // .stage_num_col
4, // .stage_num_row
// 0, // .log_scale
fwd_shift_adst_dct_4, // .shift
fwd_stage_range_col_adst_dct_4, // .stage_range_col
fwd_stage_range_row_adst_dct_4, // .stage_range_row
@@ -321,19 +329,20 @@ static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_dct_4 = {
TXFM_TYPE_DCT4}; // .txfm_type_row
// ---------------- config fwd_adst_dct_8 ----------------
static const int8_t fwd_shift_adst_dct_8[3] = {5, 1, -5};
static const int8_t fwd_shift_adst_dct_8[3] = {3, -1, -1};
static const int8_t fwd_stage_range_col_adst_dct_8[8] = {16, 16, 17, 18,
18, 19, 19, 19};
static const int8_t fwd_stage_range_row_adst_dct_8[6] = {20, 21, 22,
22, 22, 22};
static const int8_t fwd_cos_bit_col_adst_dct_8[8] = {15, 15, 15, 14,
14, 13, 13, 13};
static const int8_t fwd_cos_bit_row_adst_dct_8[6] = {12, 11, 10, 10, 10, 10};
static const int8_t fwd_stage_range_row_adst_dct_8[6] = {18, 19, 20,
20, 20, 20};
static const int8_t fwd_cos_bit_col_adst_dct_8[8] = {13, 13, 13, 13,
13, 13, 13, 13};
static const int8_t fwd_cos_bit_row_adst_dct_8[6] = {13, 13, 12, 12, 12, 12};
static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_dct_8 = {
8, // .txfm_size
8, // .stage_num_col
6, // .stage_num_row
8, // .txfm_size
8, // .stage_num_col
6, // .stage_num_row
// 0, // .log_scale
fwd_shift_adst_dct_8, // .shift
fwd_stage_range_col_adst_dct_8, // .stage_range_col
fwd_stage_range_row_adst_dct_8, // .stage_range_row
@@ -343,20 +352,21 @@ static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_dct_8 = {
TXFM_TYPE_DCT8}; // .txfm_type_row
// ---------------- config fwd_adst_dct_16 ----------------
static const int8_t fwd_shift_adst_dct_16[3] = {4, -3, -1};
static const int8_t fwd_shift_adst_dct_16[3] = {2, -2, 0};
static const int8_t fwd_stage_range_col_adst_dct_16[10] = {15, 15, 16, 17, 17,
18, 18, 19, 19, 19};
static const int8_t fwd_stage_range_row_adst_dct_16[8] = {16, 17, 18, 19,
19, 19, 19, 19};
static const int8_t fwd_cos_bit_col_adst_dct_16[10] = {15, 15, 15, 15, 15,
14, 14, 13, 13, 13};
static const int8_t fwd_cos_bit_row_adst_dct_16[8] = {15, 15, 14, 13,
13, 13, 13, 13};
static const int8_t fwd_stage_range_row_adst_dct_16[8] = {17, 18, 19, 20,
20, 20, 20, 20};
static const int8_t fwd_cos_bit_col_adst_dct_16[10] = {13, 13, 13, 13, 13,
13, 13, 13, 13, 13};
static const int8_t fwd_cos_bit_row_adst_dct_16[8] = {13, 13, 13, 12,
12, 12, 12, 12};
static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_dct_16 = {
16, // .txfm_size
10, // .stage_num_col
8, // .stage_num_row
16, // .txfm_size
10, // .stage_num_col
8, // .stage_num_row
// 0, // .log_scale
fwd_shift_adst_dct_16, // .shift
fwd_stage_range_col_adst_dct_16, // .stage_range_col
fwd_stage_range_row_adst_dct_16, // .stage_range_row
@@ -366,20 +376,21 @@ static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_dct_16 = {
TXFM_TYPE_DCT16}; // .txfm_type_row
// ---------------- config fwd_adst_dct_32 ----------------
static const int8_t fwd_shift_adst_dct_32[3] = {5, -4, -2};
static const int8_t fwd_shift_adst_dct_32[3] = {2, -4, 0};
static const int8_t fwd_stage_range_col_adst_dct_32[12] = {
16, 16, 17, 18, 18, 19, 19, 20, 20, 21, 21, 21};
static const int8_t fwd_stage_range_row_adst_dct_32[10] = {17, 18, 19, 20, 21,
21, 21, 21, 21, 21};
static const int8_t fwd_cos_bit_col_adst_dct_32[12] = {15, 15, 15, 14, 14, 13,
13, 12, 12, 11, 11, 11};
static const int8_t fwd_cos_bit_row_adst_dct_32[10] = {15, 14, 13, 12, 11,
11, 11, 11, 11, 11};
15, 15, 16, 17, 17, 18, 18, 19, 19, 20, 20, 20};
static const int8_t fwd_stage_range_row_adst_dct_32[10] = {16, 17, 18, 19, 20,
20, 20, 20, 20, 20};
static const int8_t fwd_cos_bit_col_adst_dct_32[12] = {13, 13, 13, 13, 13, 13,
13, 13, 13, 12, 12, 12};
static const int8_t fwd_cos_bit_row_adst_dct_32[10] = {13, 13, 13, 13, 12,
12, 12, 12, 12, 12};
static const TXFM_2D_CFG fwd_txfm_2d_cfg_adst_dct_32 = {
32, // .txfm_size
12, // .stage_num_col
10, // .stage_num_row
32, // .txfm_size
12, // .stage_num_col
10, // .stage_num_row
// 1, // .log_scale
fwd_shift_adst_dct_32, // .shift
fwd_stage_range_col_adst_dct_32, // .stage_range_col
fwd_stage_range_row_adst_dct_32, // .stage_range_row

260
vp10/common/vp10_inv_txfm2d_cfg.h
View File

@@ -123,17 +123,18 @@ static const TXFM_2D_CFG inv_txfm_2d_cfg_dct_dct_64 = {
TXFM_TYPE_DCT64}; // .txfm_type_row
// ---------------- config inv_dct_adst_4 ----------------
static const int8_t inv_shift_dct_adst_4[2] = {1, -5};
static const int8_t inv_stage_range_col_dct_adst_4[4] = {17, 17, 16, 16};
static const int8_t inv_stage_range_row_dct_adst_4[6] = {16, 16, 16,
16, 16, 16};
static const int8_t inv_cos_bit_col_dct_adst_4[4] = {15, 15, 15, 15};
static const int8_t inv_cos_bit_row_dct_adst_4[6] = {15, 15, 15, 15, 15, 15};
static const int8_t inv_shift_dct_adst_4[2] = {0, -4};
static const int8_t inv_stage_range_col_dct_adst_4[4] = {18, 18, 17, 17};
static const int8_t inv_stage_range_row_dct_adst_4[6] = {18, 18, 18,
18, 18, 18};
static const int8_t inv_cos_bit_col_dct_adst_4[4] = {13, 13, 13, 13};
static const int8_t inv_cos_bit_row_dct_adst_4[6] = {13, 13, 13, 13, 13, 13};
static const TXFM_2D_CFG inv_txfm_2d_cfg_dct_adst_4 = {
4, // .txfm_size
4, // .stage_num_col
6, // .stage_num_row
4, // .txfm_size
4, // .stage_num_col
6, // .stage_num_row
// 0, // .log_scale
inv_shift_dct_adst_4, // .shift
inv_stage_range_col_dct_adst_4, // .stage_range_col
inv_stage_range_row_dct_adst_4, // .stage_range_row
@@ -143,19 +144,20 @@ static const TXFM_2D_CFG inv_txfm_2d_cfg_dct_adst_4 = {
TXFM_TYPE_ADST4}; // .txfm_type_row
// ---------------- config inv_dct_adst_8 ----------------
static const int8_t inv_shift_dct_adst_8[2] = {-1, -4};
static const int8_t inv_stage_range_col_dct_adst_8[6] = {16, 16, 16,
16, 15, 15};
static const int8_t inv_stage_range_row_dct_adst_8[8] = {17, 17, 17, 17,
17, 17, 17, 17};
static const int8_t inv_cos_bit_col_dct_adst_8[6] = {15, 15, 15, 15, 15, 15};
static const int8_t inv_cos_bit_row_dct_adst_8[8] = {15, 15, 15, 15,
15, 15, 15, 15};
static const int8_t inv_shift_dct_adst_8[2] = {1, -6};
static const int8_t inv_stage_range_col_dct_adst_8[6] = {20, 20, 20,
20, 19, 19};
static const int8_t inv_stage_range_row_dct_adst_8[8] = {19, 19, 19, 19,
19, 19, 19, 19};
static const int8_t inv_cos_bit_col_dct_adst_8[6] = {12, 12, 12, 12, 12, 13};
static const int8_t inv_cos_bit_row_dct_adst_8[8] = {13, 13, 13, 13,
13, 13, 13, 13};
static const TXFM_2D_CFG inv_txfm_2d_cfg_dct_adst_8 = {
8, // .txfm_size
6, // .stage_num_col
8, // .stage_num_row
8, // .txfm_size
6, // .stage_num_col
8, // .stage_num_row
// 0, // .log_scale
inv_shift_dct_adst_8, // .shift
inv_stage_range_col_dct_adst_8, // .stage_range_col
inv_stage_range_row_dct_adst_8, // .stage_range_row
@@ -165,20 +167,21 @@ static const TXFM_2D_CFG inv_txfm_2d_cfg_dct_adst_8 = {
TXFM_TYPE_ADST8}; // .txfm_type_row
// ---------------- config inv_dct_adst_16 ----------------
static const int8_t inv_shift_dct_adst_16[2] = {1, -7};
static const int8_t inv_shift_dct_adst_16[2] = {-1, -5};
static const int8_t inv_stage_range_col_dct_adst_16[8] = {19, 19, 19, 19,
19, 19, 18, 18};
static const int8_t inv_stage_range_row_dct_adst_16[10] = {18, 18, 18, 18, 18,
18, 18, 18, 18, 18};
static const int8_t inv_stage_range_row_dct_adst_16[10] = {20, 20, 20, 20, 20,
20, 20, 20, 20, 20};
static const int8_t inv_cos_bit_col_dct_adst_16[8] = {13, 13, 13, 13,
13, 13, 13, 14};
static const int8_t inv_cos_bit_row_dct_adst_16[10] = {14, 14, 14, 14, 14,
14, 14, 14, 14, 14};
13, 13, 13, 13};
static const int8_t inv_cos_bit_row_dct_adst_16[10] = {12, 12, 12, 12, 12,
12, 12, 12, 12, 12};
static const TXFM_2D_CFG inv_txfm_2d_cfg_dct_adst_16 = {
16, // .txfm_size
8, // .stage_num_col
10, // .stage_num_row
16, // .txfm_size
8, // .stage_num_col
10, // .stage_num_row
// 0, // .log_scale
inv_shift_dct_adst_16, // .shift
inv_stage_range_col_dct_adst_16, // .stage_range_col
inv_stage_range_row_dct_adst_16, // .stage_range_row
@@ -188,20 +191,21 @@ static const TXFM_2D_CFG inv_txfm_2d_cfg_dct_adst_16 = {
TXFM_TYPE_ADST16}; // .txfm_type_row
// ---------------- config inv_dct_adst_32 ----------------
static const int8_t inv_shift_dct_adst_32[2] = {-1, -6};
static const int8_t inv_stage_range_col_dct_adst_32[10] = {18, 18, 18, 18, 18,
18, 18, 18, 17, 17};
static const int8_t inv_shift_dct_adst_32[2] = {-1, -5};
static const int8_t inv_stage_range_col_dct_adst_32[10] = {19, 19, 19, 19, 19,
19, 19, 19, 18, 18};
static const int8_t inv_stage_range_row_dct_adst_32[12] = {
19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19};
static const int8_t inv_cos_bit_col_dct_adst_32[10] = {14, 14, 14, 14, 14,
14, 14, 14, 14, 15};
static const int8_t inv_cos_bit_row_dct_adst_32[12] = {13, 13, 13, 13, 13, 13,
13, 13, 13, 13, 13, 13};
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20};
static const int8_t inv_cos_bit_col_dct_adst_32[10] = {13, 13, 13, 13, 13,
13, 13, 13, 13, 13};
static const int8_t inv_cos_bit_row_dct_adst_32[12] = {12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12};
static const TXFM_2D_CFG inv_txfm_2d_cfg_dct_adst_32 = {
32, // .txfm_size
10, // .stage_num_col
12, // .stage_num_row
32, // .txfm_size
10, // .stage_num_col
12, // .stage_num_row
// 1, // .log_scale
inv_shift_dct_adst_32, // .shift
inv_stage_range_col_dct_adst_32, // .stage_range_col
inv_stage_range_row_dct_adst_32, // .stage_range_row
@@ -212,17 +216,18 @@ static const TXFM_2D_CFG inv_txfm_2d_cfg_dct_adst_32 = {
// ---------------- config inv_adst_adst_4 ----------------
static const int8_t inv_shift_adst_adst_4[2] = {0, -4};
static const int8_t inv_stage_range_col_adst_adst_4[6] = {16, 16, 16,
16, 15, 15};
static const int8_t inv_stage_range_row_adst_adst_4[6] = {16, 16, 16,
16, 16, 16};
static const int8_t inv_cos_bit_col_adst_adst_4[6] = {15, 15, 15, 15, 15, 15};
static const int8_t inv_cos_bit_row_adst_adst_4[6] = {15, 15, 15, 15, 15, 15};
static const int8_t inv_stage_range_col_adst_adst_4[6] = {18, 18, 18,
18, 17, 17};
static const int8_t inv_stage_range_row_adst_adst_4[6] = {18, 18, 18,
18, 18, 18};
static const int8_t inv_cos_bit_col_adst_adst_4[6] = {13, 13, 13, 13, 13, 13};
static const int8_t inv_cos_bit_row_adst_adst_4[6] = {13, 13, 13, 13, 13, 13};
static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_adst_4 = {
4, // .txfm_size
6, // .stage_num_col
6, // .stage_num_row
4, // .txfm_size
6, // .stage_num_col
6, // .stage_num_row
// 0, // .log_scale
inv_shift_adst_adst_4, // .shift
inv_stage_range_col_adst_adst_4, // .stage_range_col
inv_stage_range_row_adst_adst_4, // .stage_range_row
@@ -232,20 +237,21 @@ static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_adst_4 = {
TXFM_TYPE_ADST4}; // .txfm_type_row
// ---------------- config inv_adst_adst_8 ----------------
static const int8_t inv_shift_adst_adst_8[2] = {-1, -4};
static const int8_t inv_stage_range_col_adst_adst_8[8] = {16, 16, 16, 16,
16, 16, 15, 15};
static const int8_t inv_stage_range_row_adst_adst_8[8] = {17, 17, 17, 17,
17, 17, 17, 17};
static const int8_t inv_cos_bit_col_adst_adst_8[8] = {15, 15, 15, 15,
15, 15, 15, 15};
static const int8_t inv_cos_bit_row_adst_adst_8[8] = {15, 15, 15, 15,
15, 15, 15, 15};
static const int8_t inv_shift_adst_adst_8[2] = {1, -6};
static const int8_t inv_stage_range_col_adst_adst_8[8] = {20, 20, 20, 20,
20, 20, 19, 19};
static const int8_t inv_stage_range_row_adst_adst_8[8] = {19, 19, 19, 19,
19, 19, 19, 19};
static const int8_t inv_cos_bit_col_adst_adst_8[8] = {12, 12, 12, 12,
12, 12, 12, 13};
static const int8_t inv_cos_bit_row_adst_adst_8[8] = {13, 13, 13, 13,
13, 13, 13, 13};
static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_adst_8 = {
8, // .txfm_size
8, // .stage_num_col
8, // .stage_num_row
8, // .txfm_size
8, // .stage_num_col
8, // .stage_num_row
// 0, // .log_scale
inv_shift_adst_adst_8, // .shift
inv_stage_range_col_adst_adst_8, // .stage_range_col
inv_stage_range_row_adst_adst_8, // .stage_range_row
@@ -255,20 +261,21 @@ static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_adst_8 = {
TXFM_TYPE_ADST8}; // .txfm_type_row
// ---------------- config inv_adst_adst_16 ----------------
static const int8_t inv_shift_adst_adst_16[2] = {0, -6};
static const int8_t inv_stage_range_col_adst_adst_16[10] = {18, 18, 18, 18, 18,
18, 18, 18, 17, 17};
static const int8_t inv_stage_range_row_adst_adst_16[10] = {18, 18, 18, 18, 18,
18, 18, 18, 18, 18};
static const int8_t inv_cos_bit_col_adst_adst_16[10] = {14, 14, 14, 14, 14,
14, 14, 14, 14, 15};
static const int8_t inv_cos_bit_row_adst_adst_16[10] = {14, 14, 14, 14, 14,
14, 14, 14, 14, 14};
static const int8_t inv_shift_adst_adst_16[2] = {-1, -5};
static const int8_t inv_stage_range_col_adst_adst_16[10] = {19, 19, 19, 19, 19,
19, 19, 19, 18, 18};
static const int8_t inv_stage_range_row_adst_adst_16[10] = {20, 20, 20, 20, 20,
20, 20, 20, 20, 20};
static const int8_t inv_cos_bit_col_adst_adst_16[10] = {13, 13, 13, 13, 13,
13, 13, 13, 13, 13};
static const int8_t inv_cos_bit_row_adst_adst_16[10] = {12, 12, 12, 12, 12,
12, 12, 12, 12, 12};
static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_adst_16 = {
16, // .txfm_size
10, // .stage_num_col
10, // .stage_num_row
16, // .txfm_size
10, // .stage_num_col
10, // .stage_num_row
// 0, // .log_scale
inv_shift_adst_adst_16, // .shift
inv_stage_range_col_adst_adst_16, // .stage_range_col
inv_stage_range_row_adst_adst_16, // .stage_range_row
@@ -278,20 +285,21 @@ static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_adst_16 = {
TXFM_TYPE_ADST16}; // .txfm_type_row
// ---------------- config inv_adst_adst_32 ----------------
static const int8_t inv_shift_adst_adst_32[2] = {-1, -6};
static const int8_t inv_shift_adst_adst_32[2] = {-1, -5};
static const int8_t inv_stage_range_col_adst_adst_32[12] = {
18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 17, 17};
19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 18, 18};
static const int8_t inv_stage_range_row_adst_adst_32[12] = {
19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 19};
static const int8_t inv_cos_bit_col_adst_adst_32[12] = {14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 15};
static const int8_t inv_cos_bit_row_adst_adst_32[12] = {13, 13, 13, 13, 13, 13,
20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20};
static const int8_t inv_cos_bit_col_adst_adst_32[12] = {13, 13, 13, 13, 13, 13,
13, 13, 13, 13, 13, 13};
static const int8_t inv_cos_bit_row_adst_adst_32[12] = {12, 12, 12, 12, 12, 12,
12, 12, 12, 12, 12, 12};
static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_adst_32 = {
32, // .txfm_size
12, // .stage_num_col
12, // .stage_num_row
32, // .txfm_size
12, // .stage_num_col
12, // .stage_num_row
// 1, // .log_scale
inv_shift_adst_adst_32, // .shift
inv_stage_range_col_adst_adst_32, // .stage_range_col
inv_stage_range_row_adst_adst_32, // .stage_range_row
@@ -301,17 +309,18 @@ static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_adst_32 = {
TXFM_TYPE_ADST32}; // .txfm_type_row
// ---------------- config inv_adst_dct_4 ----------------
static const int8_t inv_shift_adst_dct_4[2] = {1, -5};
static const int8_t inv_stage_range_col_adst_dct_4[6] = {17, 17, 17,
17, 16, 16};
static const int8_t inv_stage_range_row_adst_dct_4[4] = {16, 16, 16, 16};
static const int8_t inv_cos_bit_col_adst_dct_4[6] = {15, 15, 15, 15, 15, 15};
static const int8_t inv_cos_bit_row_adst_dct_4[4] = {15, 15, 15, 15};
static const int8_t inv_shift_adst_dct_4[2] = {0, -4};
static const int8_t inv_stage_range_col_adst_dct_4[6] = {18, 18, 18,
18, 17, 17};
static const int8_t inv_stage_range_row_adst_dct_4[4] = {18, 18, 18, 18};
static const int8_t inv_cos_bit_col_adst_dct_4[6] = {13, 13, 13, 13, 13, 13};
static const int8_t inv_cos_bit_row_adst_dct_4[4] = {13, 13, 13, 13};
static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_dct_4 = {
4, // .txfm_size
6, // .stage_num_col
4, // .stage_num_row
4, // .txfm_size
6, // .stage_num_col
4, // .stage_num_row
// 0, // .log_scale
inv_shift_adst_dct_4, // .shift
inv_stage_range_col_adst_dct_4, // .stage_range_col
inv_stage_range_row_adst_dct_4, // .stage_range_row
@@ -321,19 +330,20 @@ static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_dct_4 = {
TXFM_TYPE_DCT4}; // .txfm_type_row
// ---------------- config inv_adst_dct_8 ----------------
static const int8_t inv_shift_adst_dct_8[2] = {-1, -4};
static const int8_t inv_stage_range_col_adst_dct_8[8] = {16, 16, 16, 16,
16, 16, 15, 15};
static const int8_t inv_stage_range_row_adst_dct_8[6] = {17, 17, 17,
17, 17, 17};
static const int8_t inv_cos_bit_col_adst_dct_8[8] = {15, 15, 15, 15,
15, 15, 15, 15};
static const int8_t inv_cos_bit_row_adst_dct_8[6] = {15, 15, 15, 15, 15, 15};
static const int8_t inv_shift_adst_dct_8[2] = {1, -6};
static const int8_t inv_stage_range_col_adst_dct_8[8] = {20, 20, 20, 20,
20, 20, 19, 19};
static const int8_t inv_stage_range_row_adst_dct_8[6] = {19, 19, 19,
19, 19, 19};
static const int8_t inv_cos_bit_col_adst_dct_8[8] = {12, 12, 12, 12,
12, 12, 12, 13};
static const int8_t inv_cos_bit_row_adst_dct_8[6] = {13, 13, 13, 13, 13, 13};
static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_dct_8 = {
8, // .txfm_size
8, // .stage_num_col
6, // .stage_num_row
8, // .txfm_size
8, // .stage_num_col
6, // .stage_num_row
// 0, // .log_scale
inv_shift_adst_dct_8, // .shift
inv_stage_range_col_adst_dct_8, // .stage_range_col
inv_stage_range_row_adst_dct_8, // .stage_range_row
@@ -344,19 +354,20 @@ static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_dct_8 = {
// ---------------- config inv_adst_dct_16 ----------------
static const int8_t inv_shift_adst_dct_16[2] = {-1, -5};
static const int8_t inv_stage_range_col_adst_dct_16[10] = {17, 17, 17, 17, 17,
17, 17, 17, 16, 16};
static const int8_t inv_stage_range_row_adst_dct_16[8] = {18, 18, 18, 18,
18, 18, 18, 18};
static const int8_t inv_cos_bit_col_adst_dct_16[10] = {15, 15, 15, 15, 15,
15, 15, 15, 15, 15};
static const int8_t inv_cos_bit_row_adst_dct_16[8] = {14, 14, 14, 14,
14, 14, 14, 14};
static const int8_t inv_stage_range_col_adst_dct_16[10] = {19, 19, 19, 19, 19,
19, 19, 19, 18, 18};
static const int8_t inv_stage_range_row_adst_dct_16[8] = {20, 20, 20, 20,
20, 20, 20, 20};
static const int8_t inv_cos_bit_col_adst_dct_16[10] = {13, 13, 13, 13, 13,
13, 13, 13, 13, 13};
static const int8_t inv_cos_bit_row_adst_dct_16[8] = {12, 12, 12, 12,
12, 12, 12, 12};
static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_dct_16 = {
16, // .txfm_size
10, // .stage_num_col
8, // .stage_num_row
16, // .txfm_size
10, // .stage_num_col
8, // .stage_num_row
// 0, // .log_scale
inv_shift_adst_dct_16, // .shift
inv_stage_range_col_adst_dct_16, // .stage_range_col
inv_stage_range_row_adst_dct_16, // .stage_range_row
@@ -366,20 +377,21 @@ static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_dct_16 = {
TXFM_TYPE_DCT16}; // .txfm_type_row
// ---------------- config inv_adst_dct_32 ----------------
static const int8_t inv_shift_adst_dct_32[2] = {-1, -6};
static const int8_t inv_shift_adst_dct_32[2] = {-1, -5};
static const int8_t inv_stage_range_col_adst_dct_32[12] = {
18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 17, 17};
static const int8_t inv_stage_range_row_adst_dct_32[10] = {19, 19, 19, 19, 19,
19, 19, 19, 19, 19};
static const int8_t inv_cos_bit_col_adst_dct_32[12] = {14, 14, 14, 14, 14, 14,
14, 14, 14, 14, 14, 15};
static const int8_t inv_cos_bit_row_adst_dct_32[10] = {13, 13, 13, 13, 13,
13, 13, 13, 13, 13};
19, 19, 19, 19, 19, 19, 19, 19, 19, 19, 18, 18};
static const int8_t inv_stage_range_row_adst_dct_32[10] = {20, 20, 20, 20, 20,
20, 20, 20, 20, 20};
static const int8_t inv_cos_bit_col_adst_dct_32[12] = {13, 13, 13, 13, 13, 13,
13, 13, 13, 13, 13, 13};
static const int8_t inv_cos_bit_row_adst_dct_32[10] = {12, 12, 12, 12, 12,
12, 12, 12, 12, 12};
static const TXFM_2D_CFG inv_txfm_2d_cfg_adst_dct_32 = {
32, // .txfm_size
12, // .stage_num_col
10, // .stage_num_row
32, // .txfm_size
12, // .stage_num_col
10, // .stage_num_row
// 1, // .log_scale
inv_shift_adst_dct_32, // .shift
inv_stage_range_col_adst_dct_32, // .stage_range_col
inv_stage_range_row_adst_dct_32, // .stage_range_row

33
vp10/encoder/hybrid_fwd_txfm.c
View File

@@ -199,9 +199,16 @@ void vp10_highbd_fwd_txfm_4x4(const int16_t *src_diff, tran_low_t *coeff,
&fwd_txfm_2d_cfg_dct_dct_4, bd);
break;
case ADST_DCT:
vp10_fwd_txfm2d_4x4(src_diff, coeff, diff_stride,
&fwd_txfm_2d_cfg_adst_dct_4, bd);
break;
case DCT_ADST:
vp10_fwd_txfm2d_4x4(src_diff, coeff, diff_stride,
&fwd_txfm_2d_cfg_dct_adst_4, bd);
break;
case ADST_ADST:
vp10_highbd_fht4x4_c(src_diff, coeff, diff_stride, tx_type);
vp10_fwd_txfm2d_4x4(src_diff, coeff, diff_stride,
&fwd_txfm_2d_cfg_adst_adst_4, bd);
break;
#if CONFIG_EXT_TX
case FLIPADST_DCT:
@@ -239,12 +246,16 @@ static void highbd_fwd_txfm_8x8(const int16_t *src_diff, tran_low_t *coeff,
&fwd_txfm_2d_cfg_dct_dct_8, bd);
break;
case ADST_DCT:
vp10_fwd_txfm2d_8x8(src_diff, coeff, diff_stride,
&fwd_txfm_2d_cfg_adst_dct_8, bd);
break;
case DCT_ADST:
vp10_fwd_txfm2d_8x8(src_diff, coeff, diff_stride,
&fwd_txfm_2d_cfg_dct_adst_8, bd);
break;
case ADST_ADST:
if (fwd_txfm_opt == FWD_TXFM_OPT_NORMAL)
vp10_highbd_fht8x8(src_diff, coeff, diff_stride, tx_type);
else // FWD_TXFM_OPT_DC
vpx_highbd_fdct8x8_1(src_diff, coeff, diff_stride);
vp10_fwd_txfm2d_8x8(src_diff, coeff, diff_stride,
&fwd_txfm_2d_cfg_adst_adst_8, bd);
break;
#if CONFIG_EXT_TX
case FLIPADST_DCT:
@@ -283,12 +294,16 @@ static void highbd_fwd_txfm_16x16(const int16_t *src_diff, tran_low_t *coeff,
&fwd_txfm_2d_cfg_dct_dct_16, bd);
break;
case ADST_DCT:
vp10_fwd_txfm2d_16x16(src_diff, coeff, diff_stride,
&fwd_txfm_2d_cfg_adst_dct_16, bd);
break;
case DCT_ADST:
vp10_fwd_txfm2d_16x16(src_diff, coeff, diff_stride,
&fwd_txfm_2d_cfg_dct_adst_16, bd);
break;
case ADST_ADST:
if (fwd_txfm_opt == FWD_TXFM_OPT_NORMAL)
vp10_highbd_fht16x16(src_diff, coeff, diff_stride, tx_type);
else // FWD_TXFM_OPT_DC
vpx_highbd_fdct16x16_1(src_diff, coeff, diff_stride);
vp10_fwd_txfm2d_16x16(src_diff, coeff, diff_stride,
&fwd_txfm_2d_cfg_adst_adst_16, bd);
break;
#if CONFIG_EXT_TX
case FLIPADST_DCT: