Merge "keep values in registers during quantization"
This commit is contained in:
Johann
254
vp8/encoder/x86/quantize_sse4.asm
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254
vp8/encoder/x86/quantize_sse4.asm
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;
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license and patent
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; grant that can be found in the LICENSE file in the root of the source
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; tree. All contributing project authors may be found in the AUTHORS
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; file in the root of the source tree.
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;
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%include "vpx_ports/x86_abi_support.asm"
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%include "asm_enc_offsets.asm"
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; void vp8_regular_quantize_b_sse4 | arg
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; (BLOCK *b, | 0
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; BLOCKD *d) | 1
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global sym(vp8_regular_quantize_b_sse4)
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sym(vp8_regular_quantize_b_sse4):
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%if ABI_IS_32BIT
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push rbp
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mov rbp, rsp
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GET_GOT rbx
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push rdi
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push rsi
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ALIGN_STACK 16, rax
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%define qcoeff 0 ; 32
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%define stack_size 32
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sub rsp, stack_size
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%else
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%ifidn __OUTPUT_FORMAT__,x64
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SAVE_XMM 8, u
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push rdi
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push rsi
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%endif
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%endif
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; end prolog
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%if ABI_IS_32BIT
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mov rdi, arg(0) ; BLOCK *b
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mov rsi, arg(1) ; BLOCKD *d
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%else
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%ifidn __OUTPUT_FORMAT__,x64
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mov rdi, rcx ; BLOCK *b
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mov rsi, rdx ; BLOCKD *d
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%else
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;mov rdi, rdi ; BLOCK *b
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;mov rsi, rsi ; BLOCKD *d
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%endif
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%endif
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mov rax, [rdi + vp8_block_coeff]
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mov rcx, [rdi + vp8_block_zbin]
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mov rdx, [rdi + vp8_block_round]
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movd xmm7, [rdi + vp8_block_zbin_extra]
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; z
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movdqa xmm0, [rax]
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movdqa xmm1, [rax + 16]
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; duplicate zbin_oq_value
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pshuflw xmm7, xmm7, 0
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punpcklwd xmm7, xmm7
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movdqa xmm2, xmm0
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movdqa xmm3, xmm1
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; sz
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psraw xmm0, 15
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psraw xmm1, 15
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; (z ^ sz)
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pxor xmm2, xmm0
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pxor xmm3, xmm1
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; x = abs(z)
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psubw xmm2, xmm0
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psubw xmm3, xmm1
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; zbin
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movdqa xmm4, [rcx]
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movdqa xmm5, [rcx + 16]
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; *zbin_ptr + zbin_oq_value
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paddw xmm4, xmm7
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paddw xmm5, xmm7
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movdqa xmm6, xmm2
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movdqa xmm7, xmm3
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; x - (*zbin_ptr + zbin_oq_value)
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psubw xmm6, xmm4
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psubw xmm7, xmm5
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; round
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movdqa xmm4, [rdx]
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movdqa xmm5, [rdx + 16]
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mov rax, [rdi + vp8_block_quant_shift]
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mov rcx, [rdi + vp8_block_quant]
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mov rdx, [rdi + vp8_block_zrun_zbin_boost]
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; x + round
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paddw xmm2, xmm4
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paddw xmm3, xmm5
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; quant
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movdqa xmm4, [rcx]
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movdqa xmm5, [rcx + 16]
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; y = x * quant_ptr >> 16
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pmulhw xmm4, xmm2
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pmulhw xmm5, xmm3
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; y += x
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paddw xmm2, xmm4
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paddw xmm3, xmm5
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pxor xmm4, xmm4
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%if ABI_IS_32BIT
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movdqa [rsp + qcoeff], xmm4
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movdqa [rsp + qcoeff + 16], xmm4
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%else
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pxor xmm8, xmm8
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%endif
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; quant_shift
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movdqa xmm5, [rax]
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; zrun_zbin_boost
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mov rax, rdx
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%macro ZIGZAG_LOOP 5
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; x
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pextrw ecx, %4, %2
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; if (x >= zbin)
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sub cx, WORD PTR[rdx] ; x - zbin
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lea rdx, [rdx + 2] ; zbin_boost_ptr++
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jl rq_zigzag_loop_%1 ; x < zbin
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pextrw edi, %3, %2 ; y
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; downshift by quant_shift[rc]
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pextrb ecx, xmm5, %1 ; quant_shift[rc]
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sar edi, cl ; also sets Z bit
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je rq_zigzag_loop_%1 ; !y
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%if ABI_IS_32BIT
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mov WORD PTR[rsp + qcoeff + %1 *2], di
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%else
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pinsrw %5, edi, %2 ; qcoeff[rc]
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%endif
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mov rdx, rax ; reset to b->zrun_zbin_boost
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rq_zigzag_loop_%1:
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%endmacro
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; in vp8_default_zig_zag1d order: see vp8/common/entropy.c
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ZIGZAG_LOOP 0, 0, xmm2, xmm6, xmm4
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ZIGZAG_LOOP 1, 1, xmm2, xmm6, xmm4
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ZIGZAG_LOOP 4, 4, xmm2, xmm6, xmm4
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ZIGZAG_LOOP 8, 0, xmm3, xmm7, xmm8
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ZIGZAG_LOOP 5, 5, xmm2, xmm6, xmm4
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ZIGZAG_LOOP 2, 2, xmm2, xmm6, xmm4
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ZIGZAG_LOOP 3, 3, xmm2, xmm6, xmm4
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ZIGZAG_LOOP 6, 6, xmm2, xmm6, xmm4
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ZIGZAG_LOOP 9, 1, xmm3, xmm7, xmm8
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ZIGZAG_LOOP 12, 4, xmm3, xmm7, xmm8
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ZIGZAG_LOOP 13, 5, xmm3, xmm7, xmm8
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ZIGZAG_LOOP 10, 2, xmm3, xmm7, xmm8
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ZIGZAG_LOOP 7, 7, xmm2, xmm6, xmm4
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ZIGZAG_LOOP 11, 3, xmm3, xmm7, xmm8
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ZIGZAG_LOOP 14, 6, xmm3, xmm7, xmm8
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ZIGZAG_LOOP 15, 7, xmm3, xmm7, xmm8
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mov rcx, [rsi + vp8_blockd_dequant]
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mov rdi, [rsi + vp8_blockd_dqcoeff]
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%if ABI_IS_32BIT
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movdqa xmm4, [rsp + qcoeff]
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movdqa xmm5, [rsp + qcoeff + 16]
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%else
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%define xmm5 xmm8
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%endif
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; y ^ sz
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pxor xmm4, xmm0
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pxor xmm5, xmm1
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; x = (y ^ sz) - sz
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psubw xmm4, xmm0
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psubw xmm5, xmm1
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; dequant
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movdqa xmm0, [rcx]
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movdqa xmm1, [rcx + 16]
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mov rcx, [rsi + vp8_blockd_qcoeff]
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pmullw xmm0, xmm4
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pmullw xmm1, xmm5
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; store qcoeff
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movdqa [rcx], xmm4
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movdqa [rcx + 16], xmm5
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; store dqcoeff
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movdqa [rdi], xmm0
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movdqa [rdi + 16], xmm1
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; select the last value (in zig_zag order) for EOB
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pxor xmm6, xmm6
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pcmpeqw xmm4, xmm6
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pcmpeqw xmm5, xmm6
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packsswb xmm4, xmm5
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pshufb xmm4, [GLOBAL(zig_zag1d)]
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pmovmskb edx, xmm4
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xor rdi, rdi
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mov eax, -1
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xor dx, ax
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bsr eax, edx
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sub edi, edx
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sar edi, 31
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add eax, 1
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and eax, edi
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mov [rsi + vp8_blockd_eob], eax
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; begin epilog
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%if ABI_IS_32BIT
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add rsp, stack_size
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pop rsp
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pop rsi
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pop rdi
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RESTORE_GOT
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pop rbp
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%else
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%undef xmm5
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%ifidn __OUTPUT_FORMAT__,x64
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pop rsi
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pop rdi
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RESTORE_XMM
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%endif
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%endif
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ret
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SECTION_RODATA
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align 16
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; vp8/common/entropy.c: vp8_default_zig_zag1d
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zig_zag1d:
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db 0, 1, 4, 8, 5, 2, 3, 6, 9, 12, 13, 10, 7, 11, 14, 15
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@@ -51,4 +51,17 @@ extern prototype_quantize_block(vp8_fast_quantize_b_ssse3);
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#endif /* HAVE_SSSE3 */
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#if HAVE_SSE4_1
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extern prototype_quantize_block(vp8_regular_quantize_b_sse4);
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#if !CONFIG_RUNTIME_CPU_DETECT
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#undef vp8_quantize_quantb
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#define vp8_quantize_quantb vp8_regular_quantize_b_sse4
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#endif /* !CONFIG_RUNTIME_CPU_DETECT */
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#endif /* HAVE_SSE4_1 */
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#endif /* QUANTIZE_X86_H */
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@@ -313,6 +313,8 @@ void vp8_arch_x86_encoder_init(VP8_COMP *cpi)
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cpi->rtcd.variance.sad8x8x8 = vp8_sad8x8x8_sse4;
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cpi->rtcd.variance.sad4x4x8 = vp8_sad4x4x8_sse4;
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cpi->rtcd.search.full_search = vp8_full_search_sadx8;
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cpi->rtcd.quantize.quantb = vp8_regular_quantize_b_sse4;
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}
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#endif
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@@ -117,6 +117,7 @@ VP8_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/variance_ssse3.c
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VP8_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/variance_impl_ssse3.asm
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VP8_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/quantize_ssse3.asm
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VP8_CX_SRCS-$(HAVE_SSE4_1) += encoder/x86/sad_sse4.asm
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VP8_CX_SRCS-$(HAVE_SSE4_1) += encoder/x86/quantize_sse4.asm
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VP8_CX_SRCS-$(ARCH_X86)$(ARCH_X86_64) += encoder/x86/quantize_mmx.asm
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VP8_CX_SRCS-$(ARCH_X86)$(ARCH_X86_64) += encoder/x86/encodeopt.asm
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VP8_CX_SRCS-$(ARCH_X86_64) += encoder/x86/ssim_opt.asm
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