Merge "Add support for v256 intrinsics" into nextgenv2
This commit is contained in:
Yaowu Xu
@@ -394,9 +394,13 @@ DSP_SRCS-yes += simd/v64_intrinsics.h
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DSP_SRCS-yes += simd/v64_intrinsics_c.h
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DSP_SRCS-yes += simd/v128_intrinsics.h
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DSP_SRCS-yes += simd/v128_intrinsics_c.h
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DSP_SRCS-yes += simd/v256_intrinsics.h
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DSP_SRCS-yes += simd/v256_intrinsics_c.h
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DSP_SRCS-$(HAVE_SSE2) += simd/v64_intrinsics_x86.h
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DSP_SRCS-$(HAVE_SSE2) += simd/v128_intrinsics_x86.h
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DSP_SRCS-$(HAVE_SSE2) += simd/v256_intrinsics_x86.h
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DSP_SRCS-$(HAVE_NEON) += simd/v64_intrinsics_arm.h
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DSP_SRCS-$(HAVE_NEON) += simd/v128_intrinsics_arm.h
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DSP_SRCS-$(HAVE_NEON) += simd/v256_intrinsics_arm.h
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$(eval $(call rtcd_h_template,aom_dsp_rtcd,aom_dsp/aom_dsp_rtcd_defs.pl))
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@@ -22,11 +22,11 @@
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#include "./aom_simd_inline.h"
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#if HAVE_NEON
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#include "simd/v128_intrinsics_arm.h"
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#include "simd/v256_intrinsics_arm.h"
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#elif HAVE_SSE2
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#include "simd/v128_intrinsics_x86.h"
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#include "simd/v256_intrinsics_x86.h"
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#else
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#include "simd/v128_intrinsics.h"
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#include "simd/v256_intrinsics.h"
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#endif
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#endif // AOM_DSP_AOM_AOM_SIMD_H_
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274
aom_dsp/simd/v256_intrinsics.h
Normal file
274
aom_dsp/simd/v256_intrinsics.h
Normal file
@@ -0,0 +1,274 @@
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/*
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* Copyright (c) 2016, Alliance for Open Media. All rights reserved
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*
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* This source code is subject to the terms of the BSD 2 Clause License and
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* the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
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* was not distributed with this source code in the LICENSE file, you can
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* obtain it at www.aomedia.org/license/software. If the Alliance for Open
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* Media Patent License 1.0 was not distributed with this source code in the
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* PATENTS file, you can obtain it at www.aomedia.org/license/patent.
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*/
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#ifndef _V256_INTRINSICS_H
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#define _V256_INTRINSICS_H
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "./v256_intrinsics_c.h"
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#include "./v128_intrinsics.h"
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#include "./v64_intrinsics.h"
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/* Fallback to plain, unoptimised C. */
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typedef c_v256 v256;
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SIMD_INLINE uint32_t v256_low_u32(v256 a) { return c_v256_low_u32(a); }
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SIMD_INLINE v64 v256_low_v64(v256 a) { return c_v256_low_v64(a); }
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SIMD_INLINE v128 v256_low_v128(v256 a) { return c_v256_low_v128(a); }
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SIMD_INLINE v128 v256_high_v128(v256 a) { return c_v256_high_v128(a); }
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SIMD_INLINE v256 v256_from_v128(v128 hi, v128 lo) {
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return c_v256_from_v128(hi, lo);
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}
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SIMD_INLINE v256 v256_from_64(uint64_t a, uint64_t b, uint64_t c, uint64_t d) {
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return c_v256_from_64(a, b, c, d);
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}
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SIMD_INLINE v256 v256_from_v64(v64 a, v64 b, v64 c, v64 d) {
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return c_v256_from_v64(a, b, c, d);
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}
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SIMD_INLINE v256 v256_load_unaligned(const void *p) {
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return c_v256_load_unaligned(p);
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}
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SIMD_INLINE v256 v256_load_aligned(const void *p) {
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return c_v256_load_aligned(p);
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}
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SIMD_INLINE void v256_store_unaligned(void *p, v256 a) {
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c_v256_store_unaligned(p, a);
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}
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SIMD_INLINE void v256_store_aligned(void *p, v256 a) {
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c_v256_store_aligned(p, a);
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}
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SIMD_INLINE v256 v256_align(v256 a, v256 b, const unsigned int c) {
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return c_v256_align(a, b, c);
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}
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SIMD_INLINE v256 v256_zero() { return c_v256_zero(); }
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SIMD_INLINE v256 v256_dup_8(uint8_t x) { return c_v256_dup_8(x); }
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SIMD_INLINE v256 v256_dup_16(uint16_t x) { return c_v256_dup_16(x); }
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SIMD_INLINE v256 v256_dup_32(uint32_t x) { return c_v256_dup_32(x); }
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typedef uint32_t sad256_internal;
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SIMD_INLINE sad256_internal v256_sad_u8_init() { return c_v256_sad_u8_init(); }
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SIMD_INLINE sad256_internal v256_sad_u8(sad256_internal s, v256 a, v256 b) {
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return c_v256_sad_u8(s, a, b);
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}
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SIMD_INLINE uint32_t v256_sad_u8_sum(sad256_internal s) {
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return c_v256_sad_u8_sum(s);
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}
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typedef uint32_t ssd256_internal;
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SIMD_INLINE ssd256_internal v256_ssd_u8_init() { return c_v256_ssd_u8_init(); }
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SIMD_INLINE ssd256_internal v256_ssd_u8(ssd256_internal s, v256 a, v256 b) {
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return c_v256_ssd_u8(s, a, b);
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}
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SIMD_INLINE uint32_t v256_ssd_u8_sum(ssd256_internal s) {
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return c_v256_ssd_u8_sum(s);
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}
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SIMD_INLINE int64_t v256_dotp_s16(v256 a, v256 b) {
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return c_v256_dotp_s16(a, b);
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}
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SIMD_INLINE uint64_t v256_hadd_u8(v256 a) { return c_v256_hadd_u8(a); }
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SIMD_INLINE v256 v256_or(v256 a, v256 b) { return c_v256_or(a, b); }
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SIMD_INLINE v256 v256_xor(v256 a, v256 b) { return c_v256_xor(a, b); }
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SIMD_INLINE v256 v256_and(v256 a, v256 b) { return c_v256_and(a, b); }
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SIMD_INLINE v256 v256_andn(v256 a, v256 b) { return c_v256_andn(a, b); }
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SIMD_INLINE v256 v256_add_8(v256 a, v256 b) { return c_v256_add_8(a, b); }
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SIMD_INLINE v256 v256_add_16(v256 a, v256 b) { return c_v256_add_16(a, b); }
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SIMD_INLINE v256 v256_sadd_s16(v256 a, v256 b) { return c_v256_sadd_s16(a, b); }
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SIMD_INLINE v256 v256_add_32(v256 a, v256 b) { return c_v256_add_32(a, b); }
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SIMD_INLINE v256 v256_padd_s16(v256 a) { return c_v256_padd_s16(a); }
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SIMD_INLINE v256 v256_sub_8(v256 a, v256 b) { return c_v256_sub_8(a, b); }
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SIMD_INLINE v256 v256_ssub_u8(v256 a, v256 b) { return c_v256_ssub_u8(a, b); }
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SIMD_INLINE v256 v256_ssub_s8(v256 a, v256 b) { return c_v256_ssub_s8(a, b); }
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SIMD_INLINE v256 v256_sub_16(v256 a, v256 b) { return c_v256_sub_16(a, b); }
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SIMD_INLINE v256 v256_ssub_s16(v256 a, v256 b) { return c_v256_ssub_s16(a, b); }
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SIMD_INLINE v256 v256_sub_32(v256 a, v256 b) { return c_v256_sub_32(a, b); }
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SIMD_INLINE v256 v256_abs_s16(v256 a) { return c_v256_abs_s16(a); }
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SIMD_INLINE v256 v256_mul_s16(v128 a, v128 b) { return c_v256_mul_s16(a, b); }
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SIMD_INLINE v256 v256_mullo_s16(v256 a, v256 b) {
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return c_v256_mullo_s16(a, b);
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}
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SIMD_INLINE v256 v256_mulhi_s16(v256 a, v256 b) {
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return c_v256_mulhi_s16(a, b);
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}
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SIMD_INLINE v256 v256_mullo_s32(v256 a, v256 b) {
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return c_v256_mullo_s32(a, b);
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}
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SIMD_INLINE v256 v256_madd_s16(v256 a, v256 b) { return c_v256_madd_s16(a, b); }
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SIMD_INLINE v256 v256_madd_us8(v256 a, v256 b) { return c_v256_madd_us8(a, b); }
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SIMD_INLINE v256 v256_avg_u8(v256 a, v256 b) { return c_v256_avg_u8(a, b); }
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SIMD_INLINE v256 v256_rdavg_u8(v256 a, v256 b) { return c_v256_rdavg_u8(a, b); }
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SIMD_INLINE v256 v256_avg_u16(v256 a, v256 b) { return c_v256_avg_u16(a, b); }
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SIMD_INLINE v256 v256_min_u8(v256 a, v256 b) { return c_v256_min_u8(a, b); }
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SIMD_INLINE v256 v256_max_u8(v256 a, v256 b) { return c_v256_max_u8(a, b); }
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SIMD_INLINE v256 v256_min_s8(v256 a, v256 b) { return c_v256_min_s8(a, b); }
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SIMD_INLINE v256 v256_max_s8(v256 a, v256 b) { return c_v256_max_s8(a, b); }
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SIMD_INLINE v256 v256_min_s16(v256 a, v256 b) { return c_v256_min_s16(a, b); }
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SIMD_INLINE v256 v256_max_s16(v256 a, v256 b) { return c_v256_max_s16(a, b); }
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SIMD_INLINE v256 v256_ziplo_8(v256 a, v256 b) { return c_v256_ziplo_8(a, b); }
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SIMD_INLINE v256 v256_ziphi_8(v256 a, v256 b) { return c_v256_ziphi_8(a, b); }
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SIMD_INLINE v256 v256_ziplo_16(v256 a, v256 b) { return c_v256_ziplo_16(a, b); }
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SIMD_INLINE v256 v256_ziphi_16(v256 a, v256 b) { return c_v256_ziphi_16(a, b); }
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SIMD_INLINE v256 v256_ziplo_32(v256 a, v256 b) { return c_v256_ziplo_32(a, b); }
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SIMD_INLINE v256 v256_ziphi_32(v256 a, v256 b) { return c_v256_ziphi_32(a, b); }
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SIMD_INLINE v256 v256_ziplo_64(v256 a, v256 b) { return c_v256_ziplo_64(a, b); }
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SIMD_INLINE v256 v256_ziphi_64(v256 a, v256 b) { return c_v256_ziphi_64(a, b); }
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SIMD_INLINE v256 v256_ziplo_128(v256 a, v256 b) {
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return c_v256_ziplo_128(a, b);
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}
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SIMD_INLINE v256 v256_ziphi_128(v256 a, v256 b) {
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return c_v256_ziphi_128(a, b);
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}
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SIMD_INLINE v256 v256_zip_8(v128 a, v128 b) { return c_v256_zip_8(a, b); }
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SIMD_INLINE v256 v256_zip_16(v128 a, v128 b) { return c_v256_zip_16(a, b); }
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SIMD_INLINE v256 v256_zip_32(v128 a, v128 b) { return c_v256_zip_32(a, b); }
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SIMD_INLINE v256 v256_unziplo_8(v256 a, v256 b) {
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return c_v256_unziplo_8(a, b);
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}
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SIMD_INLINE v256 v256_unziphi_8(v256 a, v256 b) {
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return c_v256_unziphi_8(a, b);
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}
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SIMD_INLINE v256 v256_unziplo_16(v256 a, v256 b) {
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return c_v256_unziplo_16(a, b);
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}
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SIMD_INLINE v256 v256_unziphi_16(v256 a, v256 b) {
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return c_v256_unziphi_16(a, b);
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}
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SIMD_INLINE v256 v256_unziplo_32(v256 a, v256 b) {
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return c_v256_unziplo_32(a, b);
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}
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SIMD_INLINE v256 v256_unziphi_32(v256 a, v256 b) {
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return c_v256_unziphi_32(a, b);
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}
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SIMD_INLINE v256 v256_unpack_u8_s16(v128 a) { return c_v256_unpack_u8_s16(a); }
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SIMD_INLINE v256 v256_unpacklo_u8_s16(v256 a) {
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return c_v256_unpacklo_u8_s16(a);
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}
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SIMD_INLINE v256 v256_unpackhi_u8_s16(v256 a) {
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return c_v256_unpackhi_u8_s16(a);
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}
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SIMD_INLINE v256 v256_pack_s32_s16(v256 a, v256 b) {
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return c_v256_pack_s32_s16(a, b);
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}
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SIMD_INLINE v256 v256_pack_s16_u8(v256 a, v256 b) {
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return c_v256_pack_s16_u8(a, b);
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}
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SIMD_INLINE v256 v256_pack_s16_s8(v256 a, v256 b) {
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return c_v256_pack_s16_s8(a, b);
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}
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SIMD_INLINE v256 v256_unpack_u16_s32(v128 a) {
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return c_v256_unpack_u16_s32(a);
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}
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SIMD_INLINE v256 v256_unpack_s16_s32(v128 a) {
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return c_v256_unpack_s16_s32(a);
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}
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SIMD_INLINE v256 v256_unpacklo_u16_s32(v256 a) {
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return c_v256_unpacklo_u16_s32(a);
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}
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SIMD_INLINE v256 v256_unpacklo_s16_s32(v256 a) {
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return c_v256_unpacklo_s16_s32(a);
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}
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SIMD_INLINE v256 v256_unpackhi_u16_s32(v256 a) {
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return c_v256_unpackhi_u16_s32(a);
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}
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SIMD_INLINE v256 v256_unpackhi_s16_s32(v256 a) {
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return c_v256_unpackhi_s16_s32(a);
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}
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SIMD_INLINE v256 v256_shuffle_8(v256 a, v256 pattern) {
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return c_v256_shuffle_8(a, pattern);
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}
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SIMD_INLINE v256 v256_pshuffle_8(v256 a, v256 pattern) {
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return c_v256_pshuffle_8(a, pattern);
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}
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SIMD_INLINE v256 v256_cmpgt_s8(v256 a, v256 b) { return c_v256_cmpgt_s8(a, b); }
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SIMD_INLINE v256 v256_cmplt_s8(v256 a, v256 b) { return c_v256_cmplt_s8(a, b); }
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SIMD_INLINE v256 v256_cmpeq_8(v256 a, v256 b) { return c_v256_cmpeq_8(a, b); }
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SIMD_INLINE v256 v256_cmpgt_s16(v256 a, v256 b) {
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return c_v256_cmpgt_s16(a, b);
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}
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SIMD_INLINE v256 v256_cmplt_s16(v256 a, v256 b) {
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return c_v256_cmplt_s16(a, b);
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}
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SIMD_INLINE v256 v256_cmpeq_16(v256 a, v256 b) { return c_v256_cmpeq_16(a, b); }
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SIMD_INLINE v256 v256_shl_8(v256 a, unsigned int c) {
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return c_v256_shl_8(a, c);
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}
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SIMD_INLINE v256 v256_shr_u8(v256 a, unsigned int c) {
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return c_v256_shr_u8(a, c);
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}
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SIMD_INLINE v256 v256_shr_s8(v256 a, unsigned int c) {
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return c_v256_shr_s8(a, c);
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}
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SIMD_INLINE v256 v256_shl_16(v256 a, unsigned int c) {
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return c_v256_shl_16(a, c);
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}
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SIMD_INLINE v256 v256_shr_u16(v256 a, unsigned int c) {
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return c_v256_shr_u16(a, c);
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}
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SIMD_INLINE v256 v256_shr_s16(v256 a, unsigned int c) {
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return c_v256_shr_s16(a, c);
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}
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SIMD_INLINE v256 v256_shl_32(v256 a, unsigned int c) {
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return c_v256_shl_32(a, c);
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}
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SIMD_INLINE v256 v256_shr_u32(v256 a, unsigned int c) {
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return c_v256_shr_u32(a, c);
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}
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SIMD_INLINE v256 v256_shr_s32(v256 a, unsigned int c) {
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return c_v256_shr_s32(a, c);
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}
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SIMD_INLINE v256 v256_shr_n_byte(v256 a, const unsigned int n) {
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return c_v256_shr_n_byte(a, n);
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}
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SIMD_INLINE v256 v256_shl_n_byte(v256 a, const unsigned int n) {
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return c_v256_shl_n_byte(a, n);
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}
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SIMD_INLINE v256 v256_shl_n_8(v256 a, const unsigned int n) {
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return c_v256_shl_n_8(a, n);
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}
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SIMD_INLINE v256 v256_shl_n_16(v256 a, const unsigned int n) {
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return c_v256_shl_n_16(a, n);
|
||||
}
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SIMD_INLINE v256 v256_shl_n_32(v256 a, const unsigned int n) {
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return c_v256_shl_n_32(a, n);
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}
|
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SIMD_INLINE v256 v256_shr_n_u8(v256 a, const unsigned int n) {
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||||
return c_v256_shr_n_u8(a, n);
|
||||
}
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SIMD_INLINE v256 v256_shr_n_u16(v256 a, const unsigned int n) {
|
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return c_v256_shr_n_u16(a, n);
|
||||
}
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SIMD_INLINE v256 v256_shr_n_u32(v256 a, const unsigned int n) {
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return c_v256_shr_n_u32(a, n);
|
||||
}
|
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SIMD_INLINE v256 v256_shr_n_s8(v256 a, const unsigned int n) {
|
||||
return c_v256_shr_n_s8(a, n);
|
||||
}
|
||||
SIMD_INLINE v256 v256_shr_n_s16(v256 a, const unsigned int n) {
|
||||
return c_v256_shr_n_s16(a, n);
|
||||
}
|
||||
SIMD_INLINE v256 v256_shr_n_s32(v256 a, const unsigned int n) {
|
||||
return c_v256_shr_n_s32(a, n);
|
||||
}
|
||||
|
||||
#endif /* _V256_INTRINSICS_H */
|
||||
17
aom_dsp/simd/v256_intrinsics_arm.h
Normal file
17
aom_dsp/simd/v256_intrinsics_arm.h
Normal file
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (c) 2016, Alliance for Open Media. All rights reserved
|
||||
*
|
||||
* This source code is subject to the terms of the BSD 2 Clause License and
|
||||
* the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
|
||||
* was not distributed with this source code in the LICENSE file, you can
|
||||
* obtain it at www.aomedia.org/license/software. If the Alliance for Open
|
||||
* Media Patent License 1.0 was not distributed with this source code in the
|
||||
* PATENTS file, you can obtain it at www.aomedia.org/license/patent.
|
||||
*/
|
||||
|
||||
#ifndef _V256_INTRINSICS_H
|
||||
#define _V256_INTRINSICS_H
|
||||
|
||||
#include "./v256_intrinsics_v128.h"
|
||||
|
||||
#endif /* _V256_INTRINSICS_H */
|
||||
701
aom_dsp/simd/v256_intrinsics_c.h
Normal file
701
aom_dsp/simd/v256_intrinsics_c.h
Normal file
@@ -0,0 +1,701 @@
|
||||
/*
|
||||
* Copyright (c) 2016, Alliance for Open Media. All rights reserved
|
||||
*
|
||||
* This source code is subject to the terms of the BSD 2 Clause License and
|
||||
* the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
|
||||
* was not distributed with this source code in the LICENSE file, you can
|
||||
* obtain it at www.aomedia.org/license/software. If the Alliance for Open
|
||||
* Media Patent License 1.0 was not distributed with this source code in the
|
||||
* PATENTS file, you can obtain it at www.aomedia.org/license/patent.
|
||||
*/
|
||||
|
||||
#ifndef _V256_INTRINSICS_C_H
|
||||
#define _V256_INTRINSICS_C_H
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "./v128_intrinsics_c.h"
|
||||
#include "./aom_config.h"
|
||||
|
||||
typedef union {
|
||||
uint8_t u8[32];
|
||||
uint16_t u16[16];
|
||||
uint32_t u32[8];
|
||||
uint64_t u64[4];
|
||||
int8_t s8[32];
|
||||
int16_t s16[16];
|
||||
int32_t s32[8];
|
||||
int64_t s64[4];
|
||||
c_v64 v64[4];
|
||||
c_v128 v128[2];
|
||||
} c_v256;
|
||||
|
||||
SIMD_INLINE uint32_t c_v256_low_u32(c_v256 a) { return a.u32[0]; }
|
||||
|
||||
SIMD_INLINE c_v64 c_v256_low_v64(c_v256 a) { return a.v64[0]; }
|
||||
|
||||
SIMD_INLINE c_v128 c_v256_low_v128(c_v256 a) { return a.v128[0]; }
|
||||
|
||||
SIMD_INLINE c_v128 c_v256_high_v128(c_v256 a) { return a.v128[1]; }
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_from_v128(c_v128 hi, c_v128 lo) {
|
||||
c_v256 t;
|
||||
t.v128[1] = hi;
|
||||
t.v128[0] = lo;
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_from_64(uint64_t a, uint64_t b, uint64_t c,
|
||||
uint64_t d) {
|
||||
c_v256 t;
|
||||
t.u64[3] = a;
|
||||
t.u64[2] = b;
|
||||
t.u64[1] = c;
|
||||
t.u64[0] = d;
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_from_v64(c_v64 a, c_v64 b, c_v64 c, c_v64 d) {
|
||||
c_v256 t;
|
||||
t.u64[3] = a.u64;
|
||||
t.u64[2] = b.u64;
|
||||
t.u64[1] = c.u64;
|
||||
t.u64[0] = d.u64;
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_load_unaligned(const void *p) {
|
||||
c_v256 t;
|
||||
uint8_t *pp = (uint8_t *)p;
|
||||
uint8_t *q = (uint8_t *)&t;
|
||||
int c;
|
||||
for (c = 0; c < 32; c++) q[c] = pp[c];
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_load_aligned(const void *p) {
|
||||
if (simd_check && (uintptr_t)p & 31) {
|
||||
fprintf(stderr, "Error: unaligned v256 load at %p\n", p);
|
||||
abort();
|
||||
}
|
||||
return c_v256_load_unaligned(p);
|
||||
}
|
||||
|
||||
SIMD_INLINE void c_v256_store_unaligned(void *p, c_v256 a) {
|
||||
uint8_t *pp = (uint8_t *)p;
|
||||
uint8_t *q = (uint8_t *)&a;
|
||||
int c;
|
||||
for (c = 0; c < 32; c++) pp[c] = q[c];
|
||||
}
|
||||
|
||||
SIMD_INLINE void c_v256_store_aligned(void *p, c_v256 a) {
|
||||
if (simd_check && (uintptr_t)p & 31) {
|
||||
fprintf(stderr, "Error: unaligned v256 store at %p\n", p);
|
||||
abort();
|
||||
}
|
||||
c_v256_store_unaligned(p, a);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_zero() {
|
||||
c_v256 t;
|
||||
t.u64[3] = t.u64[2] = t.u64[1] = t.u64[0] = 0;
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_dup_8(uint8_t x) {
|
||||
c_v256 t;
|
||||
t.v64[3] = t.v64[2] = t.v64[1] = t.v64[0] = c_v64_dup_8(x);
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_dup_16(uint16_t x) {
|
||||
c_v256 t;
|
||||
t.v64[3] = t.v64[2] = t.v64[1] = t.v64[0] = c_v64_dup_16(x);
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_dup_32(uint32_t x) {
|
||||
c_v256 t;
|
||||
t.v64[3] = t.v64[2] = t.v64[1] = t.v64[0] = c_v64_dup_32(x);
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE int64_t c_v256_dotp_s16(c_v256 a, c_v256 b) {
|
||||
return c_v128_dotp_s16(a.v128[1], b.v128[1]) +
|
||||
c_v128_dotp_s16(a.v128[0], b.v128[0]);
|
||||
}
|
||||
|
||||
SIMD_INLINE uint64_t c_v256_hadd_u8(c_v256 a) {
|
||||
return c_v128_hadd_u8(a.v128[1]) + c_v128_hadd_u8(a.v128[0]);
|
||||
}
|
||||
|
||||
typedef uint32_t c_sad256_internal;
|
||||
|
||||
SIMD_INLINE c_sad128_internal c_v256_sad_u8_init() { return 0; }
|
||||
|
||||
/* Implementation dependent return value. Result must be finalised with
|
||||
v256_sad_u8_sum().
|
||||
The result for more than 16 v256_sad_u8() calls is undefined. */
|
||||
SIMD_INLINE c_sad128_internal c_v256_sad_u8(c_sad256_internal s, c_v256 a,
|
||||
c_v256 b) {
|
||||
int c;
|
||||
for (c = 0; c < 32; c++)
|
||||
s += a.u8[c] > b.u8[c] ? a.u8[c] - b.u8[c] : b.u8[c] - a.u8[c];
|
||||
return s;
|
||||
}
|
||||
|
||||
SIMD_INLINE uint32_t c_v256_sad_u8_sum(c_sad256_internal s) { return s; }
|
||||
|
||||
typedef uint32_t c_ssd256_internal;
|
||||
|
||||
SIMD_INLINE c_ssd256_internal c_v256_ssd_u8_init() { return 0; }
|
||||
|
||||
/* Implementation dependent return value. Result must be finalised with
|
||||
* v256_ssd_u8_sum(). */
|
||||
SIMD_INLINE c_ssd256_internal c_v256_ssd_u8(c_ssd256_internal s, c_v256 a,
|
||||
c_v256 b) {
|
||||
int c;
|
||||
for (c = 0; c < 32; c++) s += (a.u8[c] - b.u8[c]) * (a.u8[c] - b.u8[c]);
|
||||
return s;
|
||||
}
|
||||
|
||||
SIMD_INLINE uint32_t c_v256_ssd_u8_sum(c_ssd256_internal s) { return s; }
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_or(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_or(a.v128[1], b.v128[1]),
|
||||
c_v128_or(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_xor(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_xor(a.v128[1], b.v128[1]),
|
||||
c_v128_xor(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_and(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_and(a.v128[1], b.v128[1]),
|
||||
c_v128_and(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_andn(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_andn(a.v128[1], b.v128[1]),
|
||||
c_v128_andn(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_add_8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_add_8(a.v128[1], b.v128[1]),
|
||||
c_v128_add_8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_add_16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_add_16(a.v128[1], b.v128[1]),
|
||||
c_v128_add_16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_sadd_s16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_sadd_s16(a.v128[1], b.v128[1]),
|
||||
c_v128_sadd_s16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_add_32(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_add_32(a.v128[1], b.v128[1]),
|
||||
c_v128_add_32(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_padd_s16(c_v256 a) {
|
||||
c_v256 t;
|
||||
t.s32[0] = (int32_t)a.s16[0] + (int32_t)a.s16[1];
|
||||
t.s32[1] = (int32_t)a.s16[2] + (int32_t)a.s16[3];
|
||||
t.s32[2] = (int32_t)a.s16[4] + (int32_t)a.s16[5];
|
||||
t.s32[3] = (int32_t)a.s16[6] + (int32_t)a.s16[7];
|
||||
t.s32[4] = (int32_t)a.s16[8] + (int32_t)a.s16[9];
|
||||
t.s32[5] = (int32_t)a.s16[10] + (int32_t)a.s16[11];
|
||||
t.s32[6] = (int32_t)a.s16[12] + (int32_t)a.s16[13];
|
||||
t.s32[7] = (int32_t)a.s16[14] + (int32_t)a.s16[15];
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_sub_8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_sub_8(a.v128[1], b.v128[1]),
|
||||
c_v128_sub_8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ssub_u8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_ssub_u8(a.v128[1], b.v128[1]),
|
||||
c_v128_ssub_u8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ssub_s8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_ssub_s8(a.v128[1], b.v128[1]),
|
||||
c_v128_ssub_s8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_sub_16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_sub_16(a.v128[1], b.v128[1]),
|
||||
c_v128_sub_16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ssub_s16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_ssub_s16(a.v128[1], b.v128[1]),
|
||||
c_v128_ssub_s16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_sub_32(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_sub_32(a.v128[1], b.v128[1]),
|
||||
c_v128_sub_32(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_abs_s16(c_v256 a) {
|
||||
return c_v256_from_v128(c_v128_abs_s16(a.v128[1]), c_v128_abs_s16(a.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_mul_s16(c_v128 a, c_v128 b) {
|
||||
c_v128 lo_bits = c_v128_mullo_s16(a, b);
|
||||
c_v128 hi_bits = c_v128_mulhi_s16(a, b);
|
||||
return c_v256_from_v128(c_v128_ziphi_16(hi_bits, lo_bits),
|
||||
c_v128_ziplo_16(hi_bits, lo_bits));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_mullo_s16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_mullo_s16(a.v128[1], b.v128[1]),
|
||||
c_v128_mullo_s16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_mulhi_s16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_mulhi_s16(a.v128[1], b.v128[1]),
|
||||
c_v128_mulhi_s16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_mullo_s32(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_mullo_s32(a.v128[1], b.v128[1]),
|
||||
c_v128_mullo_s32(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_madd_s16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_madd_s16(a.v128[1], b.v128[1]),
|
||||
c_v128_madd_s16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_madd_us8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_madd_us8(a.v128[1], b.v128[1]),
|
||||
c_v128_madd_us8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_avg_u8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_avg_u8(a.v128[1], b.v128[1]),
|
||||
c_v128_avg_u8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_rdavg_u8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_rdavg_u8(a.v128[1], b.v128[1]),
|
||||
c_v128_rdavg_u8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_avg_u16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_avg_u16(a.v128[1], b.v128[1]),
|
||||
c_v128_avg_u16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_min_u8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_min_u8(a.v128[1], b.v128[1]),
|
||||
c_v128_min_u8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_max_u8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_max_u8(a.v128[1], b.v128[1]),
|
||||
c_v128_max_u8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_min_s8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_min_s8(a.v128[1], b.v128[1]),
|
||||
c_v128_min_s8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_max_s8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_max_s8(a.v128[1], b.v128[1]),
|
||||
c_v128_max_s8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_min_s16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_min_s16(a.v128[1], b.v128[1]),
|
||||
c_v128_min_s16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_max_s16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_max_s16(a.v128[1], b.v128[1]),
|
||||
c_v128_max_s16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ziplo_8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_ziphi_8(a.v128[0], b.v128[0]),
|
||||
c_v128_ziplo_8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ziphi_8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_ziphi_8(a.v128[1], b.v128[1]),
|
||||
c_v128_ziplo_8(a.v128[1], b.v128[1]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ziplo_16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_ziphi_16(a.v128[0], b.v128[0]),
|
||||
c_v128_ziplo_16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ziphi_16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_ziphi_16(a.v128[1], b.v128[1]),
|
||||
c_v128_ziplo_16(a.v128[1], b.v128[1]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ziplo_32(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_ziphi_32(a.v128[0], b.v128[0]),
|
||||
c_v128_ziplo_32(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ziphi_32(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_ziphi_32(a.v128[1], b.v128[1]),
|
||||
c_v128_ziplo_32(a.v128[1], b.v128[1]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ziplo_64(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_ziphi_64(a.v128[0], b.v128[0]),
|
||||
c_v128_ziplo_64(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ziphi_64(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_ziphi_64(a.v128[1], b.v128[1]),
|
||||
c_v128_ziplo_64(a.v128[1], b.v128[1]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ziplo_128(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(a.v128[0], b.v128[0]);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_ziphi_128(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(a.v128[1], b.v128[1]);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_zip_8(c_v128 a, c_v128 b) {
|
||||
return c_v256_from_v128(c_v128_ziphi_8(a, b), c_v128_ziplo_8(a, b));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_zip_16(c_v128 a, c_v128 b) {
|
||||
return c_v256_from_v128(c_v128_ziphi_16(a, b), c_v128_ziplo_16(a, b));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_zip_32(c_v128 a, c_v128 b) {
|
||||
return c_v256_from_v128(c_v128_ziphi_32(a, b), c_v128_ziplo_32(a, b));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 _c_v256_unzip_8(c_v256 a, c_v256 b, int mode) {
|
||||
c_v256 t;
|
||||
int i;
|
||||
if (mode) {
|
||||
for (i = 0; i < 16; i++) {
|
||||
t.u8[i] = a.u8[i * 2 + 1];
|
||||
t.u8[i + 16] = b.u8[i * 2 + 1];
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < 16; i++) {
|
||||
t.u8[i] = b.u8[i * 2];
|
||||
t.u8[i + 16] = a.u8[i * 2];
|
||||
}
|
||||
}
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unziplo_8(c_v256 a, c_v256 b) {
|
||||
return CONFIG_BIG_ENDIAN ? _c_v256_unzip_8(a, b, 1)
|
||||
: _c_v256_unzip_8(a, b, 0);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unziphi_8(c_v256 a, c_v256 b) {
|
||||
return CONFIG_BIG_ENDIAN ? _c_v256_unzip_8(b, a, 0)
|
||||
: _c_v256_unzip_8(b, a, 1);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 _c_v256_unzip_16(c_v256 a, c_v256 b, int mode) {
|
||||
c_v256 t;
|
||||
int i;
|
||||
if (mode) {
|
||||
for (i = 0; i < 8; i++) {
|
||||
t.u16[i] = a.u16[i * 2 + 1];
|
||||
t.u16[i + 8] = b.u16[i * 2 + 1];
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < 8; i++) {
|
||||
t.u16[i] = b.u16[i * 2];
|
||||
t.u16[i + 8] = a.u16[i * 2];
|
||||
}
|
||||
}
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unziplo_16(c_v256 a, c_v256 b) {
|
||||
return CONFIG_BIG_ENDIAN ? _c_v256_unzip_16(a, b, 1)
|
||||
: _c_v256_unzip_16(a, b, 0);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unziphi_16(c_v256 a, c_v256 b) {
|
||||
return CONFIG_BIG_ENDIAN ? _c_v256_unzip_16(b, a, 0)
|
||||
: _c_v256_unzip_16(b, a, 1);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 _c_v256_unzip_32(c_v256 a, c_v256 b, int mode) {
|
||||
c_v256 t;
|
||||
if (mode) {
|
||||
t.u32[7] = b.u32[7];
|
||||
t.u32[6] = b.u32[5];
|
||||
t.u32[5] = b.u32[3];
|
||||
t.u32[4] = b.u32[1];
|
||||
t.u32[3] = a.u32[7];
|
||||
t.u32[2] = a.u32[5];
|
||||
t.u32[1] = a.u32[3];
|
||||
t.u32[0] = a.u32[1];
|
||||
} else {
|
||||
t.u32[7] = a.u32[6];
|
||||
t.u32[6] = a.u32[4];
|
||||
t.u32[5] = a.u32[2];
|
||||
t.u32[4] = a.u32[0];
|
||||
t.u32[3] = b.u32[6];
|
||||
t.u32[2] = b.u32[4];
|
||||
t.u32[1] = b.u32[2];
|
||||
t.u32[0] = b.u32[0];
|
||||
}
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unziplo_32(c_v256 a, c_v256 b) {
|
||||
return CONFIG_BIG_ENDIAN ? _c_v256_unzip_32(a, b, 1)
|
||||
: _c_v256_unzip_32(a, b, 0);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unziphi_32(c_v256 a, c_v256 b) {
|
||||
return CONFIG_BIG_ENDIAN ? _c_v256_unzip_32(b, a, 0)
|
||||
: _c_v256_unzip_32(b, a, 1);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unpack_u8_s16(c_v128 a) {
|
||||
return c_v256_from_v128(c_v128_unpackhi_u8_s16(a), c_v128_unpacklo_u8_s16(a));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unpacklo_u8_s16(c_v256 a) {
|
||||
return c_v256_from_v128(c_v128_unpackhi_u8_s16(a.v128[0]),
|
||||
c_v128_unpacklo_u8_s16(a.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unpackhi_u8_s16(c_v256 a) {
|
||||
return c_v256_from_v128(c_v128_unpackhi_u8_s16(a.v128[1]),
|
||||
c_v128_unpacklo_u8_s16(a.v128[1]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_pack_s32_s16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_pack_s32_s16(a.v128[1], a.v128[0]),
|
||||
c_v128_pack_s32_s16(b.v128[1], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_pack_s16_u8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_pack_s16_u8(a.v128[1], a.v128[0]),
|
||||
c_v128_pack_s16_u8(b.v128[1], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_pack_s16_s8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_pack_s16_s8(a.v128[1], a.v128[0]),
|
||||
c_v128_pack_s16_s8(b.v128[1], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unpack_u16_s32(c_v128 a) {
|
||||
return c_v256_from_v128(c_v128_unpackhi_u16_s32(a),
|
||||
c_v128_unpacklo_u16_s32(a));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unpack_s16_s32(c_v128 a) {
|
||||
return c_v256_from_v128(c_v128_unpackhi_s16_s32(a),
|
||||
c_v128_unpacklo_s16_s32(a));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unpacklo_u16_s32(c_v256 a) {
|
||||
return c_v256_from_v128(c_v128_unpackhi_u16_s32(a.v128[0]),
|
||||
c_v128_unpacklo_u16_s32(a.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unpacklo_s16_s32(c_v256 a) {
|
||||
return c_v256_from_v128(c_v128_unpackhi_s16_s32(a.v128[0]),
|
||||
c_v128_unpacklo_s16_s32(a.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unpackhi_u16_s32(c_v256 a) {
|
||||
return c_v256_from_v128(c_v128_unpackhi_u16_s32(a.v128[1]),
|
||||
c_v128_unpacklo_u16_s32(a.v128[1]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_unpackhi_s16_s32(c_v256 a) {
|
||||
return c_v256_from_v128(c_v128_unpackhi_s16_s32(a.v128[1]),
|
||||
c_v128_unpacklo_s16_s32(a.v128[1]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shuffle_8(c_v256 a, c_v256 pattern) {
|
||||
c_v256 t;
|
||||
int c;
|
||||
for (c = 0; c < 32; c++) {
|
||||
if (pattern.u8[c] & ~31) {
|
||||
fprintf(stderr, "Undefined v256_shuffle_8 index %d/%d\n", pattern.u8[c],
|
||||
c);
|
||||
abort();
|
||||
}
|
||||
t.u8[c] = a.u8[CONFIG_BIG_ENDIAN ? 31 - (pattern.u8[c] & 31)
|
||||
: pattern.u8[c] & 31];
|
||||
}
|
||||
return t;
|
||||
}
|
||||
|
||||
// Pairwise / dual-lane shuffle: shuffle two 128 bit lates.
|
||||
SIMD_INLINE c_v256 c_v256_pshuffle_8(c_v256 a, c_v256 pattern) {
|
||||
return c_v256_from_v128(
|
||||
c_v128_shuffle_8(c_v256_high_v128(a), c_v256_high_v128(pattern)),
|
||||
c_v128_shuffle_8(c_v256_low_v128(a), c_v256_low_v128(pattern)));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_cmpgt_s8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_cmpgt_s8(a.v128[1], b.v128[1]),
|
||||
c_v128_cmpgt_s8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_cmplt_s8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_cmplt_s8(a.v128[1], b.v128[1]),
|
||||
c_v128_cmplt_s8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_cmpeq_8(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_cmpeq_8(a.v128[1], b.v128[1]),
|
||||
c_v128_cmpeq_8(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_cmpgt_s16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_cmpgt_s16(a.v128[1], b.v128[1]),
|
||||
c_v128_cmpgt_s16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_cmplt_s16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_cmplt_s16(a.v128[1], b.v128[1]),
|
||||
c_v128_cmplt_s16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_cmpeq_16(c_v256 a, c_v256 b) {
|
||||
return c_v256_from_v128(c_v128_cmpeq_16(a.v128[1], b.v128[1]),
|
||||
c_v128_cmpeq_16(a.v128[0], b.v128[0]));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shl_n_byte(c_v256 a, const unsigned int n) {
|
||||
if (n < 16)
|
||||
return c_v256_from_v128(c_v128_or(c_v128_shl_n_byte(a.v128[1], n),
|
||||
c_v128_shr_n_byte(a.v128[0], 16 - n)),
|
||||
c_v128_shl_n_byte(a.v128[0], n));
|
||||
else if (n > 16)
|
||||
return c_v256_from_v128(c_v128_shl_n_byte(a.v128[0], n - 16),
|
||||
c_v128_zero());
|
||||
else
|
||||
return c_v256_from_v128(c_v256_low_v128(a), c_v128_zero());
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_n_byte(c_v256 a, const unsigned int n) {
|
||||
if (n < 16)
|
||||
return c_v256_from_v128(c_v128_shr_n_byte(a.v128[1], n),
|
||||
c_v128_or(c_v128_shr_n_byte(a.v128[0], n),
|
||||
c_v128_shl_n_byte(a.v128[1], 16 - n)));
|
||||
else if (n > 16)
|
||||
return c_v256_from_v128(c_v128_zero(),
|
||||
c_v128_shr_n_byte(a.v128[1], n - 16));
|
||||
else
|
||||
return c_v256_from_v128(c_v128_zero(), c_v256_high_v128(a));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_align(c_v256 a, c_v256 b, const unsigned int c) {
|
||||
if (simd_check && c > 31) {
|
||||
fprintf(stderr, "Error: undefined alignment %d\n", c);
|
||||
abort();
|
||||
}
|
||||
return c ? c_v256_or(c_v256_shr_n_byte(b, c), c_v256_shl_n_byte(a, 32 - c))
|
||||
: b;
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shl_8(c_v256 a, const unsigned int c) {
|
||||
return c_v256_from_v128(c_v128_shl_8(a.v128[1], c),
|
||||
c_v128_shl_8(a.v128[0], c));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_u8(c_v256 a, const unsigned int c) {
|
||||
return c_v256_from_v128(c_v128_shr_u8(a.v128[1], c),
|
||||
c_v128_shr_u8(a.v128[0], c));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_s8(c_v256 a, const unsigned int c) {
|
||||
return c_v256_from_v128(c_v128_shr_s8(a.v128[1], c),
|
||||
c_v128_shr_s8(a.v128[0], c));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shl_16(c_v256 a, const unsigned int c) {
|
||||
return c_v256_from_v128(c_v128_shl_16(a.v128[1], c),
|
||||
c_v128_shl_16(a.v128[0], c));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_u16(c_v256 a, const unsigned int c) {
|
||||
return c_v256_from_v128(c_v128_shr_u16(a.v128[1], c),
|
||||
c_v128_shr_u16(a.v128[0], c));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_s16(c_v256 a, const unsigned int c) {
|
||||
return c_v256_from_v128(c_v128_shr_s16(a.v128[1], c),
|
||||
c_v128_shr_s16(a.v128[0], c));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shl_32(c_v256 a, const unsigned int c) {
|
||||
return c_v256_from_v128(c_v128_shl_32(a.v128[1], c),
|
||||
c_v128_shl_32(a.v128[0], c));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_u32(c_v256 a, const unsigned int c) {
|
||||
return c_v256_from_v128(c_v128_shr_u32(a.v128[1], c),
|
||||
c_v128_shr_u32(a.v128[0], c));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_s32(c_v256 a, const unsigned int c) {
|
||||
return c_v256_from_v128(c_v128_shr_s32(a.v128[1], c),
|
||||
c_v128_shr_s32(a.v128[0], c));
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shl_n_8(c_v256 a, const unsigned int n) {
|
||||
return c_v256_shl_8(a, n);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shl_n_16(c_v256 a, const unsigned int n) {
|
||||
return c_v256_shl_16(a, n);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shl_n_32(c_v256 a, const unsigned int n) {
|
||||
return c_v256_shl_32(a, n);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_n_u8(c_v256 a, const unsigned int n) {
|
||||
return c_v256_shr_u8(a, n);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_n_u16(c_v256 a, const unsigned int n) {
|
||||
return c_v256_shr_u16(a, n);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_n_u32(c_v256 a, const unsigned int n) {
|
||||
return c_v256_shr_u32(a, n);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_n_s8(c_v256 a, const unsigned int n) {
|
||||
return c_v256_shr_s8(a, n);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_n_s16(c_v256 a, const unsigned int n) {
|
||||
return c_v256_shr_s16(a, n);
|
||||
}
|
||||
|
||||
SIMD_INLINE c_v256 c_v256_shr_n_s32(c_v256 a, const unsigned int n) {
|
||||
return c_v256_shr_s32(a, n);
|
||||
}
|
||||
|
||||
#endif /* _V256_INTRINSICS_C_H */
|
||||
525
aom_dsp/simd/v256_intrinsics_v128.h
Normal file
525
aom_dsp/simd/v256_intrinsics_v128.h
Normal file
@@ -0,0 +1,525 @@
|
||||
/*
|
||||
* Copyright (c) 2016, Alliance for Open Media. All rights reserved
|
||||
*
|
||||
* This source code is subject to the terms of the BSD 2 Clause License and
|
||||
* the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
|
||||
* was not distributed with this source code in the LICENSE file, you can
|
||||
* obtain it at www.aomedia.org/license/software. If the Alliance for Open
|
||||
* Media Patent License 1.0 was not distributed with this source code in the
|
||||
* PATENTS file, you can obtain it at www.aomedia.org/license/patent.
|
||||
*/
|
||||
|
||||
#ifndef _V256_INTRINSICS_V128_H
|
||||
#define _V256_INTRINSICS_V128_H
|
||||
|
||||
#if HAVE_NEON
|
||||
#include "./v128_intrinsics_arm.h"
|
||||
#elif HAVE_SSE2
|
||||
#include "./v128_intrinsics_x86.h"
|
||||
#else
|
||||
#include "./v128_intrinsics.h"
|
||||
#endif
|
||||
|
||||
typedef struct { v128 lo, hi; } v256;
|
||||
|
||||
SIMD_INLINE uint32_t v256_low_u32(v256 a) { return v128_low_u32(a.lo); }
|
||||
|
||||
SIMD_INLINE v64 v256_low_v64(v256 a) { return v128_low_v64(a.lo); }
|
||||
|
||||
SIMD_INLINE v128 v256_low_v128(v256 a) { return a.lo; }
|
||||
|
||||
SIMD_INLINE v128 v256_high_v128(v256 a) { return a.hi; }
|
||||
|
||||
SIMD_INLINE v256 v256_from_v128(v128 hi, v128 lo) {
|
||||
v256 t;
|
||||
t.hi = hi;
|
||||
t.lo = lo;
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_from_64(uint64_t a, uint64_t b, uint64_t c, uint64_t d) {
|
||||
return v256_from_v128(v128_from_64(a, b), v128_from_64(c, d));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_from_v64(v64 a, v64 b, v64 c, v64 d) {
|
||||
return v256_from_v128(v128_from_v64(a, b), v128_from_v64(c, d));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_load_unaligned(const void *p) {
|
||||
return v256_from_v128(v128_load_unaligned((uint8_t *)p + 16),
|
||||
v128_load_unaligned(p));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_load_aligned(const void *p) {
|
||||
return v256_from_v128(v128_load_aligned((uint8_t *)p + 16),
|
||||
v128_load_aligned(p));
|
||||
}
|
||||
|
||||
SIMD_INLINE void v256_store_unaligned(void *p, v256 a) {
|
||||
v128_store_unaligned(p, a.lo);
|
||||
v128_store_unaligned((uint8_t *)p + 16, a.hi);
|
||||
}
|
||||
|
||||
SIMD_INLINE void v256_store_aligned(void *p, v256 a) {
|
||||
v128_store_aligned(p, a.lo);
|
||||
v128_store_aligned((uint8_t *)p + 16, a.hi);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_zero() {
|
||||
return v256_from_v128(v128_zero(), v128_zero());
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_dup_8(uint8_t x) {
|
||||
v128 t = v128_dup_8(x);
|
||||
return v256_from_v128(t, t);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_dup_16(uint16_t x) {
|
||||
v128 t = v128_dup_16(x);
|
||||
return v256_from_v128(t, t);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_dup_32(uint32_t x) {
|
||||
v128 t = v128_dup_32(x);
|
||||
return v256_from_v128(t, t);
|
||||
}
|
||||
|
||||
SIMD_INLINE int64_t v256_dotp_s16(v256 a, v256 b) {
|
||||
return v128_dotp_s16(a.hi, b.hi) + v128_dotp_s16(a.lo, b.lo);
|
||||
}
|
||||
|
||||
SIMD_INLINE uint64_t v256_hadd_u8(v256 a) {
|
||||
return v128_hadd_u8(a.hi) + v128_hadd_u8(a.lo);
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
sad128_internal hi;
|
||||
sad128_internal lo;
|
||||
} sad256_internal;
|
||||
|
||||
SIMD_INLINE sad256_internal v256_sad_u8_init() {
|
||||
sad256_internal t;
|
||||
t.hi = v128_sad_u8_init();
|
||||
t.lo = v128_sad_u8_init();
|
||||
return t;
|
||||
}
|
||||
|
||||
/* Implementation dependent return value. Result must be finalised with
|
||||
v256_sad_u8_sum().
|
||||
The result for more than 16 v256_sad_u8() calls is undefined. */
|
||||
SIMD_INLINE sad256_internal v256_sad_u8(sad256_internal s, v256 a, v256 b) {
|
||||
sad256_internal t;
|
||||
t.hi = v128_sad_u8(s.hi, a.hi, b.hi);
|
||||
t.lo = v128_sad_u8(s.lo, a.lo, b.lo);
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE uint32_t v256_sad_u8_sum(sad256_internal s) {
|
||||
return v128_sad_u8_sum(s.hi) + v128_sad_u8_sum(s.lo);
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
ssd128_internal hi;
|
||||
ssd128_internal lo;
|
||||
} ssd256_internal;
|
||||
|
||||
SIMD_INLINE ssd256_internal v256_ssd_u8_init() {
|
||||
ssd256_internal t;
|
||||
t.hi = v128_ssd_u8_init();
|
||||
t.lo = v128_ssd_u8_init();
|
||||
return t;
|
||||
}
|
||||
|
||||
/* Implementation dependent return value. Result must be finalised with
|
||||
* v256_ssd_u8_sum(). */
|
||||
SIMD_INLINE ssd256_internal v256_ssd_u8(ssd256_internal s, v256 a, v256 b) {
|
||||
ssd256_internal t;
|
||||
t.hi = v128_ssd_u8(s.hi, a.hi, b.hi);
|
||||
t.lo = v128_ssd_u8(s.lo, a.lo, b.lo);
|
||||
return t;
|
||||
}
|
||||
|
||||
SIMD_INLINE uint32_t v256_ssd_u8_sum(ssd256_internal s) {
|
||||
return v128_ssd_u8_sum(s.hi) + v128_ssd_u8_sum(s.lo);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_or(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_or(a.hi, b.hi), v128_or(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_xor(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_xor(a.hi, b.hi), v128_xor(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_and(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_and(a.hi, b.hi), v128_and(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_andn(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_andn(a.hi, b.hi), v128_andn(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_add_8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_add_8(a.hi, b.hi), v128_add_8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_add_16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_add_16(a.hi, b.hi), v128_add_16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_sadd_s16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_sadd_s16(a.hi, b.hi), v128_sadd_s16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_add_32(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_add_32(a.hi, b.hi), v128_add_32(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_padd_s16(v256 a) {
|
||||
return v256_from_v128(v128_padd_s16(a.hi), v128_padd_s16(a.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_sub_8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_sub_8(a.hi, b.hi), v128_sub_8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ssub_u8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ssub_u8(a.hi, b.hi), v128_ssub_u8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ssub_s8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ssub_s8(a.hi, b.hi), v128_ssub_s8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_sub_16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_sub_16(a.hi, b.hi), v128_sub_16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ssub_s16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ssub_s16(a.hi, b.hi), v128_ssub_s16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_sub_32(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_sub_32(a.hi, b.hi), v128_sub_32(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_abs_s16(v256 a) {
|
||||
return v256_from_v128(v128_abs_s16(a.hi), v128_abs_s16(a.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_mul_s16(v128 a, v128 b) {
|
||||
v128 lo_bits = v128_mullo_s16(a, b);
|
||||
v128 hi_bits = v128_mulhi_s16(a, b);
|
||||
return v256_from_v128(v128_ziphi_16(hi_bits, lo_bits),
|
||||
v128_ziplo_16(hi_bits, lo_bits));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_mullo_s16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_mullo_s16(a.hi, b.hi), v128_mullo_s16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_mulhi_s16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_mulhi_s16(a.hi, b.hi), v128_mulhi_s16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_mullo_s32(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_mullo_s32(a.hi, b.hi), v128_mullo_s32(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_madd_s16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_madd_s16(a.hi, b.hi), v128_madd_s16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_madd_us8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_madd_us8(a.hi, b.hi), v128_madd_us8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_avg_u8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_avg_u8(a.hi, b.hi), v128_avg_u8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_rdavg_u8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_rdavg_u8(a.hi, b.hi), v128_rdavg_u8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_avg_u16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_avg_u16(a.hi, b.hi), v128_avg_u16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_min_u8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_min_u8(a.hi, b.hi), v128_min_u8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_max_u8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_max_u8(a.hi, b.hi), v128_max_u8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_min_s8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_min_s8(a.hi, b.hi), v128_min_s8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_max_s8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_max_s8(a.hi, b.hi), v128_max_s8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_min_s16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_min_s16(a.hi, b.hi), v128_min_s16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_max_s16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_max_s16(a.hi, b.hi), v128_max_s16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziplo_8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_8(a.lo, b.lo), v128_ziplo_8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziphi_8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_8(a.hi, b.hi), v128_ziplo_8(a.hi, b.hi));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziplo_16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_16(a.lo, b.lo), v128_ziplo_16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziphi_16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_16(a.hi, b.hi), v128_ziplo_16(a.hi, b.hi));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziplo_32(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_32(a.lo, b.lo), v128_ziplo_32(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziphi_32(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_32(a.hi, b.hi), v128_ziplo_32(a.hi, b.hi));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziplo_64(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_64(a.lo, b.lo), v128_ziplo_64(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziphi_64(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_64(a.hi, b.hi), v128_ziplo_64(a.hi, b.hi));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziplo_128(v256 a, v256 b) {
|
||||
return v256_from_v128(a.lo, b.lo);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziphi_128(v256 a, v256 b) {
|
||||
return v256_from_v128(a.hi, b.hi);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_zip_8(v128 a, v128 b) {
|
||||
return v256_from_v128(v128_ziphi_8(a, b), v128_ziplo_8(a, b));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_zip_16(v128 a, v128 b) {
|
||||
return v256_from_v128(v128_ziphi_16(a, b), v128_ziplo_16(a, b));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_zip_32(v128 a, v128 b) {
|
||||
return v256_from_v128(v128_ziphi_32(a, b), v128_ziplo_32(a, b));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unziplo_8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_unziplo_8(a.hi, a.lo), v128_unziplo_8(b.hi, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unziphi_8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_unziphi_8(a.hi, a.lo), v128_unziphi_8(b.hi, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unziplo_16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_unziplo_16(a.hi, a.lo),
|
||||
v128_unziplo_16(b.hi, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unziphi_16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_unziphi_16(a.hi, a.lo),
|
||||
v128_unziphi_16(b.hi, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unziplo_32(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_unziplo_32(a.hi, a.lo),
|
||||
v128_unziplo_32(b.hi, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unziphi_32(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_unziphi_32(a.hi, a.lo),
|
||||
v128_unziphi_32(b.hi, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpack_u8_s16(v128 a) {
|
||||
return v256_from_v128(v128_unpackhi_u8_s16(a), v128_unpacklo_u8_s16(a));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpacklo_u8_s16(v256 a) {
|
||||
return v256_from_v128(v128_unpackhi_u8_s16(a.lo), v128_unpacklo_u8_s16(a.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpackhi_u8_s16(v256 a) {
|
||||
return v256_from_v128(v128_unpackhi_u8_s16(a.hi), v128_unpacklo_u8_s16(a.hi));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_pack_s32_s16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_pack_s32_s16(a.hi, a.lo),
|
||||
v128_pack_s32_s16(b.hi, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_pack_s16_u8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_pack_s16_u8(a.hi, a.lo),
|
||||
v128_pack_s16_u8(b.hi, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_pack_s16_s8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_pack_s16_s8(a.hi, a.lo),
|
||||
v128_pack_s16_s8(b.hi, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpack_u16_s32(v128 a) {
|
||||
return v256_from_v128(v128_unpackhi_u16_s32(a), v128_unpacklo_u16_s32(a));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpack_s16_s32(v128 a) {
|
||||
return v256_from_v128(v128_unpackhi_s16_s32(a), v128_unpacklo_s16_s32(a));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpacklo_u16_s32(v256 a) {
|
||||
return v256_from_v128(v128_unpackhi_u16_s32(a.lo),
|
||||
v128_unpacklo_u16_s32(a.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpacklo_s16_s32(v256 a) {
|
||||
return v256_from_v128(v128_unpackhi_s16_s32(a.lo),
|
||||
v128_unpacklo_s16_s32(a.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpackhi_u16_s32(v256 a) {
|
||||
return v256_from_v128(v128_unpackhi_u16_s32(a.hi),
|
||||
v128_unpacklo_u16_s32(a.hi));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpackhi_s16_s32(v256 a) {
|
||||
return v256_from_v128(v128_unpackhi_s16_s32(a.hi),
|
||||
v128_unpacklo_s16_s32(a.hi));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shuffle_8(v256 a, v256 pattern) {
|
||||
v128 c16 = v128_dup_8(16);
|
||||
v128 maskhi = v128_cmplt_s8(pattern.hi, c16);
|
||||
v128 masklo = v128_cmplt_s8(pattern.lo, c16);
|
||||
return v256_from_v128(
|
||||
v128_or(
|
||||
v128_and(v128_shuffle_8(a.lo, pattern.hi), maskhi),
|
||||
v128_andn(v128_shuffle_8(a.hi, v128_sub_8(pattern.hi, c16)), maskhi)),
|
||||
v128_or(v128_and(v128_shuffle_8(a.lo, pattern.lo), masklo),
|
||||
v128_andn(v128_shuffle_8(a.hi, v128_sub_8(pattern.lo, c16)),
|
||||
masklo)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_pshuffle_8(v256 a, v256 pattern) {
|
||||
return v256_from_v128(
|
||||
v128_shuffle_8(v256_high_v128(a), v256_high_v128(pattern)),
|
||||
v128_shuffle_8(v256_low_v128(a), v256_low_v128(pattern)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_cmpgt_s8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_cmpgt_s8(a.hi, b.hi), v128_cmpgt_s8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_cmplt_s8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_cmplt_s8(a.hi, b.hi), v128_cmplt_s8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_cmpeq_8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_cmpeq_8(a.hi, b.hi), v128_cmpeq_8(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_cmpgt_s16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_cmpgt_s16(a.hi, b.hi), v128_cmpgt_s16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_cmplt_s16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_cmplt_s16(a.hi, b.hi), v128_cmplt_s16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_cmpeq_16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_cmpeq_16(a.hi, b.hi), v128_cmpeq_16(a.lo, b.lo));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shl_8(v256 a, const unsigned int c) {
|
||||
return v256_from_v128(v128_shl_8(a.hi, c), v128_shl_8(a.lo, c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shr_u8(v256 a, const unsigned int c) {
|
||||
return v256_from_v128(v128_shr_u8(a.hi, c), v128_shr_u8(a.lo, c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shr_s8(v256 a, const unsigned int c) {
|
||||
return v256_from_v128(v128_shr_s8(a.hi, c), v128_shr_s8(a.lo, c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shl_16(v256 a, const unsigned int c) {
|
||||
return v256_from_v128(v128_shl_16(a.hi, c), v128_shl_16(a.lo, c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shr_u16(v256 a, const unsigned int c) {
|
||||
return v256_from_v128(v128_shr_u16(a.hi, c), v128_shr_u16(a.lo, c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shr_s16(v256 a, const unsigned int c) {
|
||||
return v256_from_v128(v128_shr_s16(a.hi, c), v128_shr_s16(a.lo, c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shl_32(v256 a, const unsigned int c) {
|
||||
return v256_from_v128(v128_shl_32(a.hi, c), v128_shl_32(a.lo, c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shr_u32(v256 a, const unsigned int c) {
|
||||
return v256_from_v128(v128_shr_u32(a.hi, c), v128_shr_u32(a.lo, c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shr_s32(v256 a, const unsigned int c) {
|
||||
return v256_from_v128(v128_shr_s32(a.hi, c), v128_shr_s32(a.lo, c));
|
||||
}
|
||||
|
||||
/* These intrinsics require immediate values, so we must use #defines
|
||||
to enforce that. */
|
||||
#define v256_shl_n_byte(a, n) \
|
||||
((n) < 16 ? v256_from_v128(v128_or(v128_shl_n_byte(a.hi, n), \
|
||||
v128_shr_n_byte(a.lo, 16 - (n))), \
|
||||
v128_shl_n_byte(a.lo, (n))) \
|
||||
: v256_from_v128((n) > 16 ? v128_shl_n_byte(a.lo, (n)-16) : a.lo, \
|
||||
v128_zero()))
|
||||
|
||||
#define v256_shr_n_byte(a, n) \
|
||||
((n) < 16 ? v256_from_v128(v128_shr_n_byte(a.hi, n), \
|
||||
v128_or(v128_shr_n_byte(a.lo, n), \
|
||||
v128_shl_n_byte(a.hi, 16 - (n)))) \
|
||||
: v256_from_v128(v128_zero(), \
|
||||
(n) > 16 ? v128_shr_n_byte(a.hi, (n)-16) : a.hi))
|
||||
|
||||
#define v256_align(a, b, c) \
|
||||
((c) ? v256_or(v256_shr_n_byte(b, c), v256_shl_n_byte(a, 32 - (c))) : b)
|
||||
|
||||
#define v256_shl_n_8(a, n) \
|
||||
v256_from_v128(v128_shl_n_8(a.hi, n), v128_shl_n_8(a.lo, n))
|
||||
#define v256_shl_n_16(a, n) \
|
||||
v256_from_v128(v128_shl_n_16(a.hi, n), v128_shl_n_16(a.lo, n))
|
||||
#define v256_shl_n_32(a, n) \
|
||||
v256_from_v128(v128_shl_n_32(a.hi, n), v128_shl_n_32(a.lo, n))
|
||||
#define v256_shr_n_u8(a, n) \
|
||||
v256_from_v128(v128_shr_n_u8(a.hi, n), v128_shr_n_u8(a.lo, n))
|
||||
#define v256_shr_n_u16(a, n) \
|
||||
v256_from_v128(v128_shr_n_u16(a.hi, n), v128_shr_n_u16(a.lo, n))
|
||||
#define v256_shr_n_u32(a, n) \
|
||||
v256_from_v128(v128_shr_n_u32(a.hi, n), v128_shr_n_u32(a.lo, n))
|
||||
#define v256_shr_n_s8(a, n) \
|
||||
v256_from_v128(v128_shr_n_s8(a.hi, n), v128_shr_n_s8(a.lo, n))
|
||||
#define v256_shr_n_s16(a, n) \
|
||||
v256_from_v128(v128_shr_n_s16(a.hi, n), v128_shr_n_s16(a.lo, n))
|
||||
#define v256_shr_n_s32(a, n) \
|
||||
v256_from_v128(v128_shr_n_s32(a.hi, n), v128_shr_n_s32(a.lo, n))
|
||||
|
||||
#endif /* _V256_INTRINSICS_V128_H */
|
||||
528
aom_dsp/simd/v256_intrinsics_x86.h
Normal file
528
aom_dsp/simd/v256_intrinsics_x86.h
Normal file
@@ -0,0 +1,528 @@
|
||||
/*
|
||||
* Copyright (c) 2016, Alliance for Open Media. All rights reserved
|
||||
*
|
||||
* This source code is subject to the terms of the BSD 2 Clause License and
|
||||
* the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
|
||||
* was not distributed with this source code in the LICENSE file, you can
|
||||
* obtain it at www.aomedia.org/license/software. If the Alliance for Open
|
||||
* Media Patent License 1.0 was not distributed with this source code in the
|
||||
* PATENTS file, you can obtain it at www.aomedia.org/license/patent.
|
||||
*/
|
||||
|
||||
#ifndef _V256_INTRINSICS_H
|
||||
#define _V256_INTRINSICS_H
|
||||
|
||||
#if !defined(__AVX2__)
|
||||
|
||||
#include "./v256_intrinsics_v128.h"
|
||||
|
||||
#else
|
||||
|
||||
// The _m256i type seems to cause problems for g++'s mangling prior to
|
||||
// version 5, but adding -fabi-version=0 fixes this.
|
||||
#if !defined(__clang__) && __GNUC__ < 5 && defined(__AVX2__) && \
|
||||
defined(__cplusplus)
|
||||
#pragma GCC optimize "-fabi-version=0"
|
||||
#endif
|
||||
|
||||
#include <immintrin.h>
|
||||
#include "./v128_intrinsics_x86.h"
|
||||
|
||||
typedef __m256i v256;
|
||||
|
||||
SIMD_INLINE uint32_t v256_low_u32(v256 a) {
|
||||
return (uint32_t)_mm_cvtsi128_si32(_mm256_extracti128_si256(a, 0));
|
||||
}
|
||||
|
||||
SIMD_INLINE v64 v256_low_v64(v256 a) {
|
||||
return _mm_unpacklo_epi64(_mm256_extracti128_si256(a, 0), v64_zero());
|
||||
}
|
||||
|
||||
SIMD_INLINE v128 v256_low_v128(v256 a) {
|
||||
return _mm256_extracti128_si256(a, 0);
|
||||
}
|
||||
|
||||
SIMD_INLINE v128 v256_high_v128(v256 a) {
|
||||
return _mm256_extracti128_si256(a, 1);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_from_v128(v128 a, v128 b) {
|
||||
// gcc seems to be missing _mm256_set_m128i()
|
||||
return _mm256_insertf128_si256(
|
||||
_mm256_insertf128_si256(_mm256_setzero_si256(), b, 0), a, 1);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_from_v64(v64 a, v64 b, v64 c, v64 d) {
|
||||
return v256_from_v128(v128_from_v64(a, b), v128_from_v64(c, d));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_from_64(uint64_t a, uint64_t b, uint64_t c, uint64_t d) {
|
||||
return v256_from_v128(v128_from_64(a, b), v128_from_64(c, d));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_load_aligned(const void *p) {
|
||||
return _mm256_load_si256((const __m256i *)p);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_load_unaligned(const void *p) {
|
||||
return _mm256_loadu_si256((const __m256i *)p);
|
||||
}
|
||||
|
||||
SIMD_INLINE void v256_store_aligned(void *p, v256 a) {
|
||||
_mm256_store_si256((__m256i *)p, a);
|
||||
}
|
||||
|
||||
SIMD_INLINE void v256_store_unaligned(void *p, v256 a) {
|
||||
_mm256_storeu_si256((__m256i *)p, a);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_zero() { return _mm256_setzero_si256(); }
|
||||
|
||||
SIMD_INLINE v256 v256_dup_8(uint8_t x) { return _mm256_set1_epi8(x); }
|
||||
|
||||
SIMD_INLINE v256 v256_dup_16(uint16_t x) { return _mm256_set1_epi16(x); }
|
||||
|
||||
SIMD_INLINE v256 v256_dup_32(uint32_t x) { return _mm256_set1_epi32(x); }
|
||||
|
||||
SIMD_INLINE v256 v256_add_8(v256 a, v256 b) { return _mm256_add_epi8(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_add_16(v256 a, v256 b) { return _mm256_add_epi16(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_sadd_s16(v256 a, v256 b) {
|
||||
return _mm256_adds_epi16(a, b);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_add_32(v256 a, v256 b) { return _mm256_add_epi32(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_padd_s16(v256 a) {
|
||||
return _mm256_madd_epi16(a, _mm256_set1_epi16(1));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_sub_8(v256 a, v256 b) { return _mm256_sub_epi8(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_ssub_u8(v256 a, v256 b) { return _mm256_subs_epu8(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_ssub_s8(v256 a, v256 b) { return _mm256_subs_epi8(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_sub_16(v256 a, v256 b) { return _mm256_sub_epi16(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_ssub_s16(v256 a, v256 b) {
|
||||
return _mm256_subs_epi16(a, b);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_sub_32(v256 a, v256 b) { return _mm256_sub_epi32(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_abs_s16(v256 a) { return _mm256_abs_epi16(a); }
|
||||
|
||||
// AVX doesn't have the direct intrinsics to zip/unzip 8, 16, 32 bit
|
||||
// lanes of lower or upper halves of a 256bit vector because the
|
||||
// unpack/pack intrinsics operate on the 256 bit input vector as 2
|
||||
// independent 128 bit vectors.
|
||||
SIMD_INLINE v256 v256_ziplo_8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_8(v256_low_v128(a), v256_low_v128(b)),
|
||||
v128_ziplo_8(v256_low_v128(a), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziphi_8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_8(v256_high_v128(a), v256_high_v128(b)),
|
||||
v128_ziplo_8(v256_high_v128(a), v256_high_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziplo_16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_16(v256_low_v128(a), v256_low_v128(b)),
|
||||
v128_ziplo_16(v256_low_v128(a), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziphi_16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_16(v256_high_v128(a), v256_high_v128(b)),
|
||||
v128_ziplo_16(v256_high_v128(a), v256_high_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziplo_32(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_32(v256_low_v128(a), v256_low_v128(b)),
|
||||
v128_ziplo_32(v256_low_v128(a), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziphi_32(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_32(v256_high_v128(a), v256_high_v128(b)),
|
||||
v128_ziplo_32(v256_high_v128(a), v256_high_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziplo_64(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_64(v256_low_v128(a), v256_low_v128(b)),
|
||||
v128_ziplo_64(v256_low_v128(a), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziphi_64(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_ziphi_64(v256_high_v128(a), v256_high_v128(b)),
|
||||
v128_ziplo_64(v256_high_v128(a), v256_high_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziplo_128(v256 a, v256 b) {
|
||||
return v256_from_v128(v256_low_v128(a), v256_low_v128(b));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_ziphi_128(v256 a, v256 b) {
|
||||
return v256_from_v128(v256_high_v128(a), v256_high_v128(b));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_zip_8(v128 a, v128 b) {
|
||||
return v256_from_v128(v128_ziphi_8(a, b), v128_ziplo_8(a, b));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_zip_16(v128 a, v128 b) {
|
||||
return v256_from_v128(v128_ziphi_16(a, b), v128_ziplo_16(a, b));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_zip_32(v128 a, v128 b) {
|
||||
return v256_from_v128(v128_ziphi_32(a, b), v128_ziplo_32(a, b));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unziplo_8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_unziplo_8(v256_high_v128(a), v256_low_v128(a)),
|
||||
v128_unziplo_8(v256_high_v128(b), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unziphi_8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_unziphi_8(v256_high_v128(a), v256_low_v128(a)),
|
||||
v128_unziphi_8(v256_high_v128(b), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unziplo_16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_unziplo_16(v256_high_v128(a), v256_low_v128(a)),
|
||||
v128_unziplo_16(v256_high_v128(b), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unziphi_16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_unziphi_16(v256_high_v128(a), v256_low_v128(a)),
|
||||
v128_unziphi_16(v256_high_v128(b), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unziplo_32(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_unziplo_32(v256_high_v128(a), v256_low_v128(a)),
|
||||
v128_unziplo_32(v256_high_v128(b), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unziphi_32(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_unziphi_32(v256_high_v128(a), v256_low_v128(a)),
|
||||
v128_unziphi_32(v256_high_v128(b), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpack_u8_s16(v128 a) {
|
||||
return v256_from_v128(v128_unpackhi_u8_s16(a), v128_unpacklo_u8_s16(a));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpacklo_u8_s16(v256 a) {
|
||||
return v256_from_v128(v128_unpackhi_u8_s16(v256_low_v128(a)),
|
||||
v128_unpacklo_u8_s16(v256_low_v128(a)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpackhi_u8_s16(v256 a) {
|
||||
return v256_from_v128(v128_unpackhi_u8_s16(v256_high_v128(a)),
|
||||
v128_unpacklo_u8_s16(v256_high_v128(a)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_pack_s32_s16(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_pack_s32_s16(v256_high_v128(a), v256_low_v128(a)),
|
||||
v128_pack_s32_s16(v256_high_v128(b), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_pack_s16_u8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_pack_s16_u8(v256_high_v128(a), v256_low_v128(a)),
|
||||
v128_pack_s16_u8(v256_high_v128(b), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_pack_s16_s8(v256 a, v256 b) {
|
||||
return v256_from_v128(v128_pack_s16_s8(v256_high_v128(a), v256_low_v128(a)),
|
||||
v128_pack_s16_s8(v256_high_v128(b), v256_low_v128(b)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpack_u16_s32(v128 a) {
|
||||
return v256_from_v128(v128_unpackhi_u16_s32(a), v128_unpacklo_u16_s32(a));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpack_s16_s32(v128 a) {
|
||||
return v256_from_v128(v128_unpackhi_s16_s32(a), v128_unpacklo_s16_s32(a));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpacklo_u16_s32(v256 a) {
|
||||
return v256_from_v128(v128_unpackhi_u16_s32(v256_low_v128(a)),
|
||||
v128_unpacklo_u16_s32(v256_low_v128(a)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpacklo_s16_s32(v256 a) {
|
||||
return v256_from_v128(v128_unpackhi_s16_s32(v256_low_v128(a)),
|
||||
v128_unpacklo_s16_s32(v256_low_v128(a)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpackhi_u16_s32(v256 a) {
|
||||
return v256_from_v128(v128_unpackhi_u16_s32(v256_high_v128(a)),
|
||||
v128_unpacklo_u16_s32(v256_high_v128(a)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_unpackhi_s16_s32(v256 a) {
|
||||
return v256_from_v128(v128_unpackhi_s16_s32(v256_high_v128(a)),
|
||||
v128_unpacklo_s16_s32(v256_high_v128(a)));
|
||||
}
|
||||
SIMD_INLINE v256 v256_shuffle_8(v256 a, v256 pattern) {
|
||||
v128 c16 = v128_dup_8(16);
|
||||
v128 hi = v256_high_v128(pattern);
|
||||
v128 lo = v256_low_v128(pattern);
|
||||
v128 maskhi = v128_cmplt_s8(hi, c16);
|
||||
v128 masklo = v128_cmplt_s8(lo, c16);
|
||||
return v256_from_v128(
|
||||
v128_or(v128_and(v128_shuffle_8(v256_low_v128(a), hi), maskhi),
|
||||
v128_andn(v128_shuffle_8(v256_high_v128(a), v128_sub_8(hi, c16)),
|
||||
maskhi)),
|
||||
v128_or(v128_and(v128_shuffle_8(v256_low_v128(a), lo), masklo),
|
||||
v128_andn(v128_shuffle_8(v256_high_v128(a), v128_sub_8(lo, c16)),
|
||||
masklo)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_pshuffle_8(v256 a, v256 pattern) {
|
||||
return _mm256_shuffle_epi8(a, pattern);
|
||||
}
|
||||
|
||||
SIMD_INLINE int64_t v256_dotp_s16(v256 a, v256 b) {
|
||||
v256 r = _mm256_madd_epi16(a, b);
|
||||
#if defined(__x86_64__)
|
||||
v128 t;
|
||||
r = _mm256_add_epi64(_mm256_cvtepi32_epi64(v256_high_v128(r)),
|
||||
_mm256_cvtepi32_epi64(v256_low_v128(r)));
|
||||
t = v256_low_v128(_mm256_add_epi64(
|
||||
r, _mm256_permute2x128_si256(r, r, _MM_SHUFFLE(2, 0, 0, 1))));
|
||||
return _mm_cvtsi128_si64(_mm_add_epi64(t, _mm_srli_si128(t, 8)));
|
||||
#else
|
||||
v128 l = v256_low_v128(r);
|
||||
v128 h = v256_high_v128(r);
|
||||
return (int64_t)_mm_cvtsi128_si32(l) +
|
||||
(int64_t)_mm_cvtsi128_si32(_mm_srli_si128(l, 4)) +
|
||||
(int64_t)_mm_cvtsi128_si32(_mm_srli_si128(l, 8)) +
|
||||
(int64_t)_mm_cvtsi128_si32(_mm_srli_si128(l, 12)) +
|
||||
(int64_t)_mm_cvtsi128_si32(h) +
|
||||
(int64_t)_mm_cvtsi128_si32(_mm_srli_si128(h, 4)) +
|
||||
(int64_t)_mm_cvtsi128_si32(_mm_srli_si128(h, 8)) +
|
||||
(int64_t)_mm_cvtsi128_si32(_mm_srli_si128(h, 12));
|
||||
#endif
|
||||
}
|
||||
|
||||
SIMD_INLINE uint64_t v256_hadd_u8(v256 a) {
|
||||
v256 t = _mm256_sad_epu8(a, _mm256_setzero_si256());
|
||||
v128 lo = v256_low_v128(t);
|
||||
v128 hi = v256_high_v128(t);
|
||||
lo = v128_add_32(lo, hi);
|
||||
return v64_low_u32(v128_low_v64(lo)) + v128_low_u32(v128_high_v64(lo));
|
||||
}
|
||||
|
||||
typedef v256 sad256_internal;
|
||||
|
||||
SIMD_INLINE sad256_internal v256_sad_u8_init() {
|
||||
return _mm256_setzero_si256();
|
||||
}
|
||||
|
||||
/* Implementation dependent return value. Result must be finalised with
|
||||
v256_sad_sum().
|
||||
The result for more than 32 v256_sad_u8() calls is undefined. */
|
||||
SIMD_INLINE sad256_internal v256_sad_u8(sad256_internal s, v256 a, v256 b) {
|
||||
return _mm256_add_epi64(s, _mm256_sad_epu8(a, b));
|
||||
}
|
||||
|
||||
SIMD_INLINE uint32_t v256_sad_u8_sum(sad256_internal s) {
|
||||
v256 t = _mm256_add_epi32(s, _mm256_unpackhi_epi64(s, s));
|
||||
return v128_low_u32(_mm_add_epi32(v256_high_v128(t), v256_low_v128(t)));
|
||||
}
|
||||
|
||||
typedef v256 ssd256_internal;
|
||||
|
||||
SIMD_INLINE ssd256_internal v256_ssd_u8_init() {
|
||||
return _mm256_setzero_si256();
|
||||
}
|
||||
|
||||
/* Implementation dependent return value. Result must be finalised with
|
||||
* v256_ssd_sum(). */
|
||||
SIMD_INLINE ssd256_internal v256_ssd_u8(ssd256_internal s, v256 a, v256 b) {
|
||||
v256 l = _mm256_sub_epi16(_mm256_unpacklo_epi8(a, _mm256_setzero_si256()),
|
||||
_mm256_unpacklo_epi8(b, _mm256_setzero_si256()));
|
||||
v256 h = _mm256_sub_epi16(_mm256_unpackhi_epi8(a, _mm256_setzero_si256()),
|
||||
_mm256_unpackhi_epi8(b, _mm256_setzero_si256()));
|
||||
v256 rl = _mm256_madd_epi16(l, l);
|
||||
v256 rh = _mm256_madd_epi16(h, h);
|
||||
v128 c = _mm_cvtsi32_si128(32);
|
||||
rl = _mm256_add_epi32(rl, _mm256_srli_si256(rl, 8));
|
||||
rl = _mm256_add_epi32(rl, _mm256_srli_si256(rl, 4));
|
||||
rh = _mm256_add_epi32(rh, _mm256_srli_si256(rh, 8));
|
||||
rh = _mm256_add_epi32(rh, _mm256_srli_si256(rh, 4));
|
||||
return _mm256_add_epi64(
|
||||
s,
|
||||
_mm256_srl_epi64(_mm256_sll_epi64(_mm256_unpacklo_epi64(rl, rh), c), c));
|
||||
}
|
||||
|
||||
SIMD_INLINE uint32_t v256_ssd_u8_sum(ssd256_internal s) {
|
||||
v256 t = _mm256_add_epi32(s, _mm256_unpackhi_epi64(s, s));
|
||||
return v128_low_u32(_mm_add_epi32(v256_high_v128(t), v256_low_v128(t)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_or(v256 a, v256 b) { return _mm256_or_si256(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_xor(v256 a, v256 b) { return _mm256_xor_si256(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_and(v256 a, v256 b) { return _mm256_and_si256(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_andn(v256 a, v256 b) { return _mm256_andnot_si256(b, a); }
|
||||
|
||||
SIMD_INLINE v256 v256_mul_s16(v64 a, v64 b) {
|
||||
v128 lo_bits = v128_mullo_s16(a, b);
|
||||
v128 hi_bits = v128_mulhi_s16(a, b);
|
||||
return v256_from_v128(v128_ziphi_16(hi_bits, lo_bits),
|
||||
v128_ziplo_16(hi_bits, lo_bits));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_mullo_s16(v256 a, v256 b) {
|
||||
return _mm256_mullo_epi16(a, b);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_mulhi_s16(v256 a, v256 b) {
|
||||
return _mm256_mulhi_epi16(a, b);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_mullo_s32(v256 a, v256 b) {
|
||||
return _mm256_mullo_epi32(a, b);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_madd_s16(v256 a, v256 b) {
|
||||
return _mm256_madd_epi16(a, b);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_madd_us8(v256 a, v256 b) {
|
||||
return _mm256_maddubs_epi16(a, b);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_avg_u8(v256 a, v256 b) { return _mm256_avg_epu8(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_rdavg_u8(v256 a, v256 b) {
|
||||
return _mm256_sub_epi8(
|
||||
_mm256_avg_epu8(a, b),
|
||||
_mm256_and_si256(_mm256_xor_si256(a, b), v256_dup_8(1)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_avg_u16(v256 a, v256 b) { return _mm256_avg_epu16(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_min_u8(v256 a, v256 b) { return _mm256_min_epu8(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_max_u8(v256 a, v256 b) { return _mm256_max_epu8(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_min_s8(v256 a, v256 b) { return _mm256_min_epi8(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_max_s8(v256 a, v256 b) { return _mm256_max_epi8(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_min_s16(v256 a, v256 b) { return _mm256_min_epi16(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_max_s16(v256 a, v256 b) { return _mm256_max_epi16(a, b); }
|
||||
|
||||
SIMD_INLINE v256 v256_cmpgt_s8(v256 a, v256 b) {
|
||||
return _mm256_cmpgt_epi8(a, b);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_cmplt_s8(v256 a, v256 b) {
|
||||
return v256_andn(_mm256_cmpgt_epi8(b, a), _mm256_cmpeq_epi8(b, a));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_cmpeq_8(v256 a, v256 b) {
|
||||
return _mm256_cmpeq_epi8(a, b);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_cmpgt_s16(v256 a, v256 b) {
|
||||
return _mm256_cmpgt_epi16(a, b);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_cmplt_s16(v256 a, v256 b) {
|
||||
return v256_andn(_mm256_cmpgt_epi16(b, a), _mm256_cmpeq_epi16(b, a));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_cmpeq_16(v256 a, v256 b) {
|
||||
return _mm256_cmpeq_epi16(a, b);
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shl_8(v256 a, unsigned int c) {
|
||||
return _mm256_and_si256(_mm256_set1_epi8((uint8_t)(0xff << c)),
|
||||
_mm256_sll_epi16(a, _mm_cvtsi32_si128(c)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shr_u8(v256 a, unsigned int c) {
|
||||
return _mm256_and_si256(_mm256_set1_epi8(0xff >> c),
|
||||
_mm256_srl_epi16(a, _mm_cvtsi32_si128(c)));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shr_s8(v256 a, unsigned int c) {
|
||||
__m128i x = _mm_cvtsi32_si128(c + 8);
|
||||
return _mm256_packs_epi16(_mm256_sra_epi16(_mm256_unpacklo_epi8(a, a), x),
|
||||
_mm256_sra_epi16(_mm256_unpackhi_epi8(a, a), x));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shl_16(v256 a, unsigned int c) {
|
||||
return _mm256_sll_epi16(a, _mm_cvtsi32_si128(c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shr_u16(v256 a, unsigned int c) {
|
||||
return _mm256_srl_epi16(a, _mm_cvtsi32_si128(c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shr_s16(v256 a, unsigned int c) {
|
||||
return _mm256_sra_epi16(a, _mm_cvtsi32_si128(c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shl_32(v256 a, unsigned int c) {
|
||||
return _mm256_sll_epi32(a, _mm_cvtsi32_si128(c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shr_u32(v256 a, unsigned int c) {
|
||||
return _mm256_srl_epi32(a, _mm_cvtsi32_si128(c));
|
||||
}
|
||||
|
||||
SIMD_INLINE v256 v256_shr_s32(v256 a, unsigned int c) {
|
||||
return _mm256_sra_epi32(a, _mm_cvtsi32_si128(c));
|
||||
}
|
||||
|
||||
/* These intrinsics require immediate values, so we must use #defines
|
||||
to enforce that. */
|
||||
// _mm256_slli_si256 works on 128 bit lanes and can't be used
|
||||
#define v256_shl_n_byte(a, n) \
|
||||
((n) < 16 \
|
||||
? v256_from_v128(v128_or(v128_shl_n_byte(v256_high_v128(a), n), \
|
||||
v128_shr_n_byte(v256_low_v128(a), 16 - (n))), \
|
||||
v128_shl_n_byte(v256_low_v128(a), n)) \
|
||||
: v256_from_v128(v128_shl_n_byte(v256_low_v128(a), (n)-16), \
|
||||
v128_zero()))
|
||||
|
||||
// _mm256_srli_si256 works on 128 bit lanes and can't be used
|
||||
#define v256_shr_n_byte(a, n) \
|
||||
((n) < 16 \
|
||||
? _mm256_alignr_epi8( \
|
||||
_mm256_permute2x128_si256(a, a, _MM_SHUFFLE(2, 0, 0, 1)), a, n) \
|
||||
: ((n) > 16 \
|
||||
? _mm256_srli_si256( \
|
||||
_mm256_permute2x128_si256(a, a, _MM_SHUFFLE(2, 0, 0, 1)), \
|
||||
(n)-16) \
|
||||
: _mm256_permute2x128_si256(a, a, _MM_SHUFFLE(2, 0, 0, 1))))
|
||||
|
||||
// _mm256_alignr_epi8 works on two 128 bit lanes and can't be used
|
||||
#define v256_align(a, b, c) \
|
||||
((c) ? v256_or(v256_shr_n_byte(b, c), v256_shl_n_byte(a, 32 - c)) : b)
|
||||
|
||||
#define v256_shl_n_8(a, c) \
|
||||
_mm256_and_si256(_mm256_set1_epi8((uint8_t)(0xff << (c))), \
|
||||
_mm256_slli_epi16(a, c))
|
||||
#define v256_shr_n_u8(a, c) \
|
||||
_mm256_and_si256(_mm256_set1_epi8(0xff >> (c)), _mm256_srli_epi16(a, c))
|
||||
#define v256_shr_n_s8(a, c) \
|
||||
_mm256_packs_epi16(_mm256_srai_epi16(_mm256_unpacklo_epi8(a, a), (c) + 8), \
|
||||
_mm256_srai_epi16(_mm256_unpackhi_epi8(a, a), (c) + 8))
|
||||
#define v256_shl_n_16(a, c) _mm256_slli_epi16(a, c)
|
||||
#define v256_shr_n_u16(a, c) _mm256_srli_epi16(a, c)
|
||||
#define v256_shr_n_s16(a, c) _mm256_srai_epi16(a, c)
|
||||
#define v256_shl_n_32(a, c) _mm256_slli_epi32(a, c)
|
||||
#define v256_shr_n_u32(a, c) _mm256_srli_epi32(a, c)
|
||||
#define v256_shr_n_s32(a, c) _mm256_srai_epi32(a, c)
|
||||
#endif
|
||||
|
||||
#endif /* _V256_INTRINSICS_H */
|
||||
Reference in New Issue
Block a user