VP8 for ARMv8 by using NEON intrinsics 13
Add shortidct4x4llm_neon.c - vp8_short_idct4x4llm_neon Change-Id: I5a734bbffca8dacf8633c2b0ff07b98aa2f438ba Signed-off-by: James Yu <james.yu@linaro.org>
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James Yu
Gerrit Code Review
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;
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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EXPORT |vp8_short_idct4x4llm_neon|
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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;*************************************************************
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;void vp8_short_idct4x4llm_c(short *input, unsigned char *pred, int pitch,
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; unsigned char *dst, int stride)
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;r0 short * input
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;r1 short * pred
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;r2 int pitch
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;r3 unsigned char dst
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;sp int stride
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;*************************************************************
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; static const int cospi8sqrt2minus1=20091;
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; static const int sinpi8sqrt2 =35468;
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; static const int rounding = 0;
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; Optimization note: The resulted data from dequantization are signed
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; 13-bit data that is in the range of [-4096, 4095]. This allows to
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; use "vqdmulh"(neon) instruction since it won't go out of range
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; (13+16+1=30bits<32bits). This instruction gives the high half
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; result of the multiplication that is needed in IDCT.
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|vp8_short_idct4x4llm_neon| PROC
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vpush {d8-d15}
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adr r12, idct_coeff
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vld1.16 {q1, q2}, [r0]
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vld1.16 {d0}, [r12]
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vswp d3, d4 ;q2(vp[4] vp[12])
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ldr r0, [sp, #64] ; stride
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vqdmulh.s16 q3, q2, d0[2]
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vqdmulh.s16 q4, q2, d0[0]
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vqadd.s16 d12, d2, d3 ;a1
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vqsub.s16 d13, d2, d3 ;b1
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vshr.s16 q3, q3, #1
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vshr.s16 q4, q4, #1
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vqadd.s16 q3, q3, q2 ;modify since sinpi8sqrt2 > 65536/2 (negtive number)
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vqadd.s16 q4, q4, q2
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;d6 - c1:temp1
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;d7 - d1:temp2
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;d8 - d1:temp1
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;d9 - c1:temp2
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vqsub.s16 d10, d6, d9 ;c1
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vqadd.s16 d11, d7, d8 ;d1
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vqadd.s16 d2, d12, d11
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vqadd.s16 d3, d13, d10
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vqsub.s16 d4, d13, d10
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vqsub.s16 d5, d12, d11
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vtrn.32 d2, d4
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vtrn.32 d3, d5
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vtrn.16 d2, d3
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vtrn.16 d4, d5
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vswp d3, d4
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vqdmulh.s16 q3, q2, d0[2]
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vqdmulh.s16 q4, q2, d0[0]
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vqadd.s16 d12, d2, d3 ;a1
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vqsub.s16 d13, d2, d3 ;b1
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vshr.s16 q3, q3, #1
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vshr.s16 q4, q4, #1
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vqadd.s16 q3, q3, q2 ;modify since sinpi8sqrt2 > 65536/2 (negtive number)
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vqadd.s16 q4, q4, q2
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vqsub.s16 d10, d6, d9 ;c1
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vqadd.s16 d11, d7, d8 ;d1
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vqadd.s16 d2, d12, d11
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vqadd.s16 d3, d13, d10
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vqsub.s16 d4, d13, d10
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vqsub.s16 d5, d12, d11
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vrshr.s16 d2, d2, #3
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vrshr.s16 d3, d3, #3
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vrshr.s16 d4, d4, #3
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vrshr.s16 d5, d5, #3
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vtrn.32 d2, d4
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vtrn.32 d3, d5
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vtrn.16 d2, d3
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vtrn.16 d4, d5
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; load prediction data
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vld1.32 d6[0], [r1], r2
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vld1.32 d6[1], [r1], r2
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vld1.32 d7[0], [r1], r2
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vld1.32 d7[1], [r1], r2
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; add prediction and residual
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vaddw.u8 q1, q1, d6
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vaddw.u8 q2, q2, d7
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vqmovun.s16 d1, q1
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vqmovun.s16 d2, q2
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; store to destination
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vst1.32 d1[0], [r3], r0
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vst1.32 d1[1], [r3], r0
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vst1.32 d2[0], [r3], r0
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vst1.32 d2[1], [r3], r0
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vpop {d8-d15}
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bx lr
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ENDP
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;-----------------
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idct_coeff
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DCD 0x4e7b4e7b, 0x8a8c8a8c
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;20091, 20091, 35468, 35468
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END
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123
vp8/common/arm/neon/shortidct4x4llm_neon.c
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123
vp8/common/arm/neon/shortidct4x4llm_neon.c
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@ -0,0 +1,123 @@
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/*
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* Copyright (c) 2014 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <arm_neon.h>
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static const int16_t cospi8sqrt2minus1 = 20091;
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static const int16_t sinpi8sqrt2 = 35468;
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void vp8_short_idct4x4llm_neon(
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int16_t *input,
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unsigned char *pred_ptr,
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int pred_stride,
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unsigned char *dst_ptr,
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int dst_stride) {
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int i;
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uint32x2_t d6u32 = vdup_n_u32(0);
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uint8x8_t d1u8;
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int16x4_t d2, d3, d4, d5, d10, d11, d12, d13;
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uint16x8_t q1u16;
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int16x8_t q1s16, q2s16, q3s16, q4s16;
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int32x2x2_t v2tmp0, v2tmp1;
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int16x4x2_t v2tmp2, v2tmp3;
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d2 = vld1_s16(input);
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d3 = vld1_s16(input + 4);
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d4 = vld1_s16(input + 8);
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d5 = vld1_s16(input + 12);
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// 1st for loop
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q1s16 = vcombine_s16(d2, d4); // Swap d3 d4 here
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q2s16 = vcombine_s16(d3, d5);
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q3s16 = vqdmulhq_n_s16(q2s16, sinpi8sqrt2);
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q4s16 = vqdmulhq_n_s16(q2s16, cospi8sqrt2minus1);
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d12 = vqadd_s16(vget_low_s16(q1s16), vget_high_s16(q1s16)); // a1
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d13 = vqsub_s16(vget_low_s16(q1s16), vget_high_s16(q1s16)); // b1
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q3s16 = vshrq_n_s16(q3s16, 1);
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q4s16 = vshrq_n_s16(q4s16, 1);
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q3s16 = vqaddq_s16(q3s16, q2s16);
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q4s16 = vqaddq_s16(q4s16, q2s16);
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d10 = vqsub_s16(vget_low_s16(q3s16), vget_high_s16(q4s16)); // c1
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d11 = vqadd_s16(vget_high_s16(q3s16), vget_low_s16(q4s16)); // d1
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d2 = vqadd_s16(d12, d11);
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d3 = vqadd_s16(d13, d10);
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d4 = vqsub_s16(d13, d10);
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d5 = vqsub_s16(d12, d11);
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v2tmp0 = vtrn_s32(vreinterpret_s32_s16(d2), vreinterpret_s32_s16(d4));
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v2tmp1 = vtrn_s32(vreinterpret_s32_s16(d3), vreinterpret_s32_s16(d5));
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v2tmp2 = vtrn_s16(vreinterpret_s16_s32(v2tmp0.val[0]),
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vreinterpret_s16_s32(v2tmp1.val[0]));
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v2tmp3 = vtrn_s16(vreinterpret_s16_s32(v2tmp0.val[1]),
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vreinterpret_s16_s32(v2tmp1.val[1]));
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// 2nd for loop
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q1s16 = vcombine_s16(v2tmp2.val[0], v2tmp3.val[0]);
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q2s16 = vcombine_s16(v2tmp2.val[1], v2tmp3.val[1]);
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q3s16 = vqdmulhq_n_s16(q2s16, sinpi8sqrt2);
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q4s16 = vqdmulhq_n_s16(q2s16, cospi8sqrt2minus1);
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d12 = vqadd_s16(vget_low_s16(q1s16), vget_high_s16(q1s16)); // a1
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d13 = vqsub_s16(vget_low_s16(q1s16), vget_high_s16(q1s16)); // b1
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q3s16 = vshrq_n_s16(q3s16, 1);
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q4s16 = vshrq_n_s16(q4s16, 1);
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q3s16 = vqaddq_s16(q3s16, q2s16);
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q4s16 = vqaddq_s16(q4s16, q2s16);
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d10 = vqsub_s16(vget_low_s16(q3s16), vget_high_s16(q4s16)); // c1
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d11 = vqadd_s16(vget_high_s16(q3s16), vget_low_s16(q4s16)); // d1
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d2 = vqadd_s16(d12, d11);
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d3 = vqadd_s16(d13, d10);
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d4 = vqsub_s16(d13, d10);
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d5 = vqsub_s16(d12, d11);
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d2 = vrshr_n_s16(d2, 3);
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d3 = vrshr_n_s16(d3, 3);
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d4 = vrshr_n_s16(d4, 3);
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d5 = vrshr_n_s16(d5, 3);
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v2tmp0 = vtrn_s32(vreinterpret_s32_s16(d2), vreinterpret_s32_s16(d4));
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v2tmp1 = vtrn_s32(vreinterpret_s32_s16(d3), vreinterpret_s32_s16(d5));
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v2tmp2 = vtrn_s16(vreinterpret_s16_s32(v2tmp0.val[0]),
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vreinterpret_s16_s32(v2tmp1.val[0]));
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v2tmp3 = vtrn_s16(vreinterpret_s16_s32(v2tmp0.val[1]),
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vreinterpret_s16_s32(v2tmp1.val[1]));
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q1s16 = vcombine_s16(v2tmp2.val[0], v2tmp2.val[1]);
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q2s16 = vcombine_s16(v2tmp3.val[0], v2tmp3.val[1]);
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// dc_only_idct_add
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for (i = 0; i < 2; i++, q1s16 = q2s16) {
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d6u32 = vld1_lane_u32((const uint32_t *)pred_ptr, d6u32, 0);
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pred_ptr += pred_stride;
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d6u32 = vld1_lane_u32((const uint32_t *)pred_ptr, d6u32, 1);
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pred_ptr += pred_stride;
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q1u16 = vaddw_u8(vreinterpretq_u16_s16(q1s16),
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vreinterpret_u8_u32(d6u32));
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d1u8 = vqmovun_s16(vreinterpretq_s16_u16(q1u16));
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vst1_lane_u32((uint32_t *)dst_ptr, vreinterpret_u32_u8(d1u8), 0);
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dst_ptr += dst_stride;
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vst1_lane_u32((uint32_t *)dst_ptr, vreinterpret_u32_u8(d1u8), 1);
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dst_ptr += dst_stride;
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}
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return;
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}
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@ -159,7 +159,6 @@ VP8_COMMON_SRCS-$(HAVE_MEDIA) += common/arm/armv6/vp8_variance_halfpixvar16x16_
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VP8_COMMON_SRCS-$(HAVE_MEDIA) += common/arm/armv6/vp8_variance_halfpixvar16x16_hv_armv6$(ASM)
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# common (neon)
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VP8_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/shortidct4x4llm_neon$(ASM)
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VP8_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/sixtappredict4x4_neon$(ASM)
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VP8_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/sixtappredict8x4_neon$(ASM)
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VP8_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/sixtappredict8x8_neon$(ASM)
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@ -185,6 +184,7 @@ VP8_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/loopfiltersimplehorizontaledge_
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VP8_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/loopfiltersimpleverticaledge_neon.c
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VP8_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/mbloopfilter_neon.c
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VP8_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/sad_neon.c
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VP8_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/shortidct4x4llm_neon.c
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$(eval $(call rtcd_h_template,vp8_rtcd,vp8/common/rtcd_defs.pl))
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