2010-05-18 17:58:33 +02:00
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;
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2010-09-09 14:16:39 +02:00
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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2010-05-18 17:58:33 +02:00
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;
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2010-06-18 18:39:21 +02:00
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; Use of this source code is governed by a BSD-style license
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2010-06-04 22:19:40 +02:00
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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2010-06-18 18:39:21 +02:00
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; in the file PATENTS. All contributing project authors may
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2010-06-04 22:19:40 +02:00
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; be found in the AUTHORS file in the root of the source tree.
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2010-05-18 17:58:33 +02:00
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;
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EXPORT |vp8_short_walsh4x4_neon|
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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2011-09-19 09:15:33 +02:00
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;void vp8_short_walsh4x4_neon(short *input, short *output, int pitch)
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; r0 short *input,
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; r1 short *output,
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; r2 int pitch
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2010-05-18 17:58:33 +02:00
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|vp8_short_walsh4x4_neon| PROC
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2011-09-19 09:15:33 +02:00
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vld1.16 {d0}, [r0@64], r2 ; load input
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vld1.16 {d1}, [r0@64], r2
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vld1.16 {d2}, [r0@64], r2
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vld1.16 {d3}, [r0@64]
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2010-05-18 17:58:33 +02:00
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2011-09-19 09:15:33 +02:00
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;First for-loop
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;transpose d0, d1, d2, d3. Then, d0=ip[0], d1=ip[1], d2=ip[2], d3=ip[3]
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vtrn.32 d0, d2
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vtrn.32 d1, d3
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2011-09-19 09:15:33 +02:00
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vmov.s32 q15, #3 ; add 3 to all values
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2011-09-19 09:15:33 +02:00
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vtrn.16 d0, d1
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2010-05-18 17:58:33 +02:00
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vtrn.16 d2, d3
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2011-09-19 09:15:33 +02:00
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vadd.s16 d4, d0, d2 ; ip[0] + ip[2]
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vadd.s16 d5, d1, d3 ; ip[1] + ip[3]
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vsub.s16 d6, d1, d3 ; ip[1] - ip[3]
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vsub.s16 d7, d0, d2 ; ip[0] - ip[2]
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2011-09-19 09:15:33 +02:00
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vshl.s16 d4, d4, #2 ; a1 = (ip[0] + ip[2]) << 2
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vshl.s16 d5, d5, #2 ; d1 = (ip[1] + ip[3]) << 2
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vshl.s16 d6, d6, #2 ; c1 = (ip[1] - ip[3]) << 2
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vceq.s16 d16, d4, #0 ; a1 == 0
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vshl.s16 d7, d7, #2 ; b1 = (ip[0] - ip[2]) << 2
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2010-05-18 17:58:33 +02:00
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2011-09-19 09:15:33 +02:00
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vadd.s16 d0, d4, d5 ; a1 + d1
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vmvn d16, d16 ; a1 != 0
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vsub.s16 d3, d4, d5 ; op[3] = a1 - d1
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vadd.s16 d1, d7, d6 ; op[1] = b1 + c1
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vsub.s16 d2, d7, d6 ; op[2] = b1 - c1
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vsub.s16 d0, d0, d16 ; op[0] = a1 + d1 + (a1 != 0)
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2010-05-18 17:58:33 +02:00
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2011-09-19 09:15:33 +02:00
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;Second for-loop
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;transpose d0, d1, d2, d3, Then, d0=ip[0], d1=ip[4], d2=ip[8], d3=ip[12]
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vtrn.32 d1, d3
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vtrn.32 d0, d2
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vtrn.16 d2, d3
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vtrn.16 d0, d1
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vaddl.s16 q8, d0, d2 ; a1 = ip[0]+ip[8]
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vaddl.s16 q9, d1, d3 ; d1 = ip[4]+ip[12]
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vsubl.s16 q10, d1, d3 ; c1 = ip[4]-ip[12]
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vsubl.s16 q11, d0, d2 ; b1 = ip[0]-ip[8]
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vadd.s32 q0, q8, q9 ; a2 = a1 + d1
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vadd.s32 q1, q11, q10 ; b2 = b1 + c1
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vsub.s32 q2, q11, q10 ; c2 = b1 - c1
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vsub.s32 q3, q8, q9 ; d2 = a1 - d1
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vclt.s32 q8, q0, #0
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vclt.s32 q9, q1, #0
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vclt.s32 q10, q2, #0
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vclt.s32 q11, q3, #0
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; subtract -1 (or 0)
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vsub.s32 q0, q0, q8 ; a2 += a2 < 0
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vsub.s32 q1, q1, q9 ; b2 += b2 < 0
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vsub.s32 q2, q2, q10 ; c2 += c2 < 0
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vsub.s32 q3, q3, q11 ; d2 += d2 < 0
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vadd.s32 q8, q0, q15 ; a2 + 3
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vadd.s32 q9, q1, q15 ; b2 + 3
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vadd.s32 q10, q2, q15 ; c2 + 3
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vadd.s32 q11, q3, q15 ; d2 + 3
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; vrshrn? would add 1 << 3-1 = 2
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vshrn.s32 d0, q8, #3
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vshrn.s32 d1, q9, #3
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vshrn.s32 d2, q10, #3
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vshrn.s32 d3, q11, #3
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vst1.16 {q0, q1}, [r1@128]
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2010-05-18 17:58:33 +02:00
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bx lr
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ENDP
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END
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