2013-07-17 21:21:28 +02:00
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;
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; Copyright (c) 2013 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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2013-10-06 09:24:09 +02:00
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EXPORT |vp9_idct8x8_64_add_neon|
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2014-05-08 18:42:26 +02:00
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EXPORT |vp9_idct8x8_12_add_neon|
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2013-07-17 21:21:28 +02:00
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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; Parallel 1D IDCT on all the columns of a 8x8 16bit data matrix which are
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; loaded in q8-q15. The output will be stored back into q8-q15 registers.
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; This macro will touch q0-q7 registers and use them as buffer during
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; calculation.
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MACRO
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IDCT8x8_1D
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; stage 1
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2013-07-26 23:10:39 +02:00
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vdup.16 d0, r3 ; duplicate cospi_28_64
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vdup.16 d1, r4 ; duplicate cospi_4_64
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2013-09-05 00:41:26 +02:00
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vdup.16 d2, r5 ; duplicate cospi_12_64
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vdup.16 d3, r6 ; duplicate cospi_20_64
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2013-07-17 21:21:28 +02:00
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; input[1] * cospi_28_64
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vmull.s16 q2, d18, d0
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vmull.s16 q3, d19, d0
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2013-09-05 00:41:26 +02:00
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; input[5] * cospi_12_64
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vmull.s16 q5, d26, d2
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vmull.s16 q6, d27, d2
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2013-07-17 21:21:28 +02:00
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; input[1]*cospi_28_64-input[7]*cospi_4_64
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2013-08-16 19:27:00 +02:00
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vmlsl.s16 q2, d30, d1
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vmlsl.s16 q3, d31, d1
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2013-07-17 21:21:28 +02:00
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2013-09-05 00:41:26 +02:00
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; input[5] * cospi_12_64 - input[3] * cospi_20_64
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vmlsl.s16 q5, d22, d3
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vmlsl.s16 q6, d23, d3
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2013-07-17 21:21:28 +02:00
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; dct_const_round_shift(input_dc * cospi_16_64)
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2013-08-16 19:27:00 +02:00
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vqrshrn.s32 d8, q2, #14 ; >> 14
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vqrshrn.s32 d9, q3, #14 ; >> 14
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2013-07-17 21:21:28 +02:00
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2013-09-05 00:41:26 +02:00
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d10, q5, #14 ; >> 14
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vqrshrn.s32 d11, q6, #14 ; >> 14
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2013-07-17 21:21:28 +02:00
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; input[1] * cospi_4_64
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vmull.s16 q2, d18, d1
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vmull.s16 q3, d19, d1
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2013-09-05 00:41:26 +02:00
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; input[5] * cospi_20_64
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vmull.s16 q9, d26, d3
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vmull.s16 q13, d27, d3
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2013-07-17 21:21:28 +02:00
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; input[1]*cospi_4_64+input[7]*cospi_28_64
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2013-08-16 19:27:00 +02:00
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vmlal.s16 q2, d30, d0
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vmlal.s16 q3, d31, d0
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2013-07-17 21:21:28 +02:00
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; input[5] * cospi_20_64 + input[3] * cospi_12_64
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2013-09-05 00:41:26 +02:00
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vmlal.s16 q9, d22, d2
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vmlal.s16 q13, d23, d2
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2013-07-17 21:21:28 +02:00
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; dct_const_round_shift(input_dc * cospi_16_64)
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2013-09-05 00:41:26 +02:00
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vqrshrn.s32 d14, q2, #14 ; >> 14
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vqrshrn.s32 d15, q3, #14 ; >> 14
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2013-07-17 21:21:28 +02:00
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; stage 2 & stage 3 - even half
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2013-07-26 23:10:39 +02:00
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vdup.16 d0, r7 ; duplicate cospi_16_64
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2013-07-17 21:21:28 +02:00
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2013-09-05 00:41:26 +02:00
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d12, q9, #14 ; >> 14
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vqrshrn.s32 d13, q13, #14 ; >> 14
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2013-07-17 21:21:28 +02:00
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; input[0] * cospi_16_64
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vmull.s16 q2, d16, d0
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vmull.s16 q3, d17, d0
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2013-09-05 00:41:26 +02:00
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; input[0] * cospi_16_64
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vmull.s16 q13, d16, d0
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vmull.s16 q15, d17, d0
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2013-07-17 21:21:28 +02:00
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; (input[0] + input[2]) * cospi_16_64
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2013-08-17 01:36:07 +02:00
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vmlal.s16 q2, d24, d0
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vmlal.s16 q3, d25, d0
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2013-07-17 21:21:28 +02:00
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2013-09-05 00:41:26 +02:00
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; (input[0] - input[2]) * cospi_16_64
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vmlsl.s16 q13, d24, d0
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vmlsl.s16 q15, d25, d0
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vdup.16 d0, r8 ; duplicate cospi_24_64
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vdup.16 d1, r9 ; duplicate cospi_8_64
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2013-07-17 21:21:28 +02:00
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; dct_const_round_shift(input_dc * cospi_16_64)
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2013-08-17 01:36:07 +02:00
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vqrshrn.s32 d18, q2, #14 ; >> 14
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vqrshrn.s32 d19, q3, #14 ; >> 14
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2013-07-17 21:21:28 +02:00
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; dct_const_round_shift(input_dc * cospi_16_64)
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2013-09-05 00:41:26 +02:00
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vqrshrn.s32 d22, q13, #14 ; >> 14
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vqrshrn.s32 d23, q15, #14 ; >> 14
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2013-07-17 21:21:28 +02:00
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; input[1] * cospi_24_64 - input[3] * cospi_8_64
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; input[1] * cospi_24_64
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vmull.s16 q2, d20, d0
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vmull.s16 q3, d21, d0
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2013-09-05 00:41:26 +02:00
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; input[1] * cospi_8_64
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vmull.s16 q8, d20, d1
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vmull.s16 q12, d21, d1
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2013-07-17 21:21:28 +02:00
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; input[1] * cospi_24_64 - input[3] * cospi_8_64
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2013-08-16 19:27:00 +02:00
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vmlsl.s16 q2, d28, d1
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vmlsl.s16 q3, d29, d1
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2013-07-17 21:21:28 +02:00
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2013-09-05 00:41:26 +02:00
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; input[1] * cospi_8_64 + input[3] * cospi_24_64
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vmlal.s16 q8, d28, d0
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vmlal.s16 q12, d29, d0
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2013-07-17 21:21:28 +02:00
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d26, q2, #14 ; >> 14
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vqrshrn.s32 d27, q3, #14 ; >> 14
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; dct_const_round_shift(input_dc * cospi_16_64)
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2013-09-05 00:41:26 +02:00
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vqrshrn.s32 d30, q8, #14 ; >> 14
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vqrshrn.s32 d31, q12, #14 ; >> 14
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2013-07-17 21:21:28 +02:00
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vadd.s16 q0, q9, q15 ; output[0] = step[0] + step[3]
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vadd.s16 q1, q11, q13 ; output[1] = step[1] + step[2]
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vsub.s16 q2, q11, q13 ; output[2] = step[1] - step[2]
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vsub.s16 q3, q9, q15 ; output[3] = step[0] - step[3]
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2013-09-05 00:41:26 +02:00
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; stage 3 -odd half
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vdup.16 d16, r7 ; duplicate cospi_16_64
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2013-07-17 21:21:28 +02:00
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; stage 2 - odd half
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vsub.s16 q13, q4, q5 ; step2[5] = step1[4] - step1[5]
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vadd.s16 q4, q4, q5 ; step2[4] = step1[4] + step1[5]
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vsub.s16 q14, q7, q6 ; step2[6] = -step1[6] + step1[7]
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vadd.s16 q7, q7, q6 ; step2[7] = step1[6] + step1[7]
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; step2[6] * cospi_16_64
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vmull.s16 q9, d28, d16
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vmull.s16 q10, d29, d16
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2013-09-05 00:41:26 +02:00
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; step2[6] * cospi_16_64
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vmull.s16 q11, d28, d16
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vmull.s16 q12, d29, d16
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2013-07-17 21:21:28 +02:00
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; (step2[6] - step2[5]) * cospi_16_64
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2013-08-17 01:36:07 +02:00
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vmlsl.s16 q9, d26, d16
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vmlsl.s16 q10, d27, d16
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2013-07-17 21:21:28 +02:00
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2013-09-05 00:41:26 +02:00
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; (step2[5] + step2[6]) * cospi_16_64
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vmlal.s16 q11, d26, d16
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vmlal.s16 q12, d27, d16
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2013-07-17 21:21:28 +02:00
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d10, q9, #14 ; >> 14
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vqrshrn.s32 d11, q10, #14 ; >> 14
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; dct_const_round_shift(input_dc * cospi_16_64)
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2013-09-05 00:41:26 +02:00
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vqrshrn.s32 d12, q11, #14 ; >> 14
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vqrshrn.s32 d13, q12, #14 ; >> 14
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2013-07-17 21:21:28 +02:00
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; stage 4
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2013-07-26 23:10:39 +02:00
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vadd.s16 q8, q0, q7 ; output[0] = step1[0] + step1[7];
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vadd.s16 q9, q1, q6 ; output[1] = step1[1] + step1[6];
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vadd.s16 q10, q2, q5 ; output[2] = step1[2] + step1[5];
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vadd.s16 q11, q3, q4 ; output[3] = step1[3] + step1[4];
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vsub.s16 q12, q3, q4 ; output[4] = step1[3] - step1[4];
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vsub.s16 q13, q2, q5 ; output[5] = step1[2] - step1[5];
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vsub.s16 q14, q1, q6 ; output[6] = step1[1] - step1[6];
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vsub.s16 q15, q0, q7 ; output[7] = step1[0] - step1[7];
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2013-07-17 21:21:28 +02:00
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MEND
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; Transpose a 8x8 16bit data matrix. Datas are loaded in q8-q15.
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MACRO
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TRANSPOSE8X8
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vswp d17, d24
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vswp d23, d30
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vswp d21, d28
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vswp d19, d26
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vtrn.32 q8, q10
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vtrn.32 q9, q11
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vtrn.32 q12, q14
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vtrn.32 q13, q15
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vtrn.16 q8, q9
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vtrn.16 q10, q11
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vtrn.16 q12, q13
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vtrn.16 q14, q15
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MEND
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AREA Block, CODE, READONLY ; name this block of code
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2013-10-06 09:24:09 +02:00
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;void vp9_idct8x8_64_add_neon(int16_t *input, uint8_t *dest, int dest_stride)
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2013-07-17 21:21:28 +02:00
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;
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; r0 int16_t input
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; r1 uint8_t *dest
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; r2 int dest_stride)
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2013-10-06 09:24:09 +02:00
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|vp9_idct8x8_64_add_neon| PROC
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2013-07-17 21:21:28 +02:00
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push {r4-r9}
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2013-08-16 19:27:00 +02:00
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vpush {d8-d15}
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2013-08-17 01:36:07 +02:00
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vld1.s16 {q8,q9}, [r0]!
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vld1.s16 {q10,q11}, [r0]!
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vld1.s16 {q12,q13}, [r0]!
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vld1.s16 {q14,q15}, [r0]!
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2013-07-17 21:21:28 +02:00
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; transpose the input data
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TRANSPOSE8X8
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; generate cospi_28_64 = 3196
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mov r3, #0x0c00
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add r3, #0x7c
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; generate cospi_4_64 = 16069
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mov r4, #0x3e00
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add r4, #0xc5
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; generate cospi_12_64 = 13623
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mov r5, #0x3500
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add r5, #0x37
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; generate cospi_20_64 = 9102
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mov r6, #0x2300
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add r6, #0x8e
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; generate cospi_16_64 = 11585
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mov r7, #0x2d00
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add r7, #0x41
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; generate cospi_24_64 = 6270
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mov r8, #0x1800
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add r8, #0x7e
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; generate cospi_8_64 = 15137
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mov r9, #0x3b00
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add r9, #0x21
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; First transform rows
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IDCT8x8_1D
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; Transpose the matrix
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TRANSPOSE8X8
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; Then transform columns
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IDCT8x8_1D
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; ROUND_POWER_OF_TWO(temp_out[j], 5)
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vrshr.s16 q8, q8, #5
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vrshr.s16 q9, q9, #5
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vrshr.s16 q10, q10, #5
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vrshr.s16 q11, q11, #5
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vrshr.s16 q12, q12, #5
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vrshr.s16 q13, q13, #5
|
|
|
|
|
vrshr.s16 q14, q14, #5
|
|
|
|
|
vrshr.s16 q15, q15, #5
|
|
|
|
|
|
|
|
|
|
; save dest pointer
|
|
|
|
|
mov r0, r1
|
|
|
|
|
|
|
|
|
|
; load destination data
|
2013-07-26 23:10:39 +02:00
|
|
|
vld1.64 {d0}, [r1], r2
|
|
|
|
|
vld1.64 {d1}, [r1], r2
|
|
|
|
|
vld1.64 {d2}, [r1], r2
|
|
|
|
|
vld1.64 {d3}, [r1], r2
|
|
|
|
|
vld1.64 {d4}, [r1], r2
|
|
|
|
|
vld1.64 {d5}, [r1], r2
|
|
|
|
|
vld1.64 {d6}, [r1], r2
|
|
|
|
|
vld1.64 {d7}, [r1]
|
2013-07-17 21:21:28 +02:00
|
|
|
|
|
|
|
|
; ROUND_POWER_OF_TWO(temp_out[j], 5) + dest[j * dest_stride + i]
|
|
|
|
|
vaddw.u8 q8, q8, d0
|
|
|
|
|
vaddw.u8 q9, q9, d1
|
|
|
|
|
vaddw.u8 q10, q10, d2
|
|
|
|
|
vaddw.u8 q11, q11, d3
|
|
|
|
|
vaddw.u8 q12, q12, d4
|
|
|
|
|
vaddw.u8 q13, q13, d5
|
|
|
|
|
vaddw.u8 q14, q14, d6
|
|
|
|
|
vaddw.u8 q15, q15, d7
|
|
|
|
|
|
|
|
|
|
; clip_pixel
|
|
|
|
|
vqmovun.s16 d0, q8
|
|
|
|
|
vqmovun.s16 d1, q9
|
|
|
|
|
vqmovun.s16 d2, q10
|
|
|
|
|
vqmovun.s16 d3, q11
|
|
|
|
|
vqmovun.s16 d4, q12
|
|
|
|
|
vqmovun.s16 d5, q13
|
|
|
|
|
vqmovun.s16 d6, q14
|
|
|
|
|
vqmovun.s16 d7, q15
|
|
|
|
|
|
|
|
|
|
; store the data
|
|
|
|
|
vst1.64 {d0}, [r0], r2
|
|
|
|
|
vst1.64 {d1}, [r0], r2
|
|
|
|
|
vst1.64 {d2}, [r0], r2
|
|
|
|
|
vst1.64 {d3}, [r0], r2
|
|
|
|
|
vst1.64 {d4}, [r0], r2
|
|
|
|
|
vst1.64 {d5}, [r0], r2
|
|
|
|
|
vst1.64 {d6}, [r0], r2
|
|
|
|
|
vst1.64 {d7}, [r0], r2
|
|
|
|
|
|
2013-08-16 19:27:00 +02:00
|
|
|
vpop {d8-d15}
|
2013-07-17 21:21:28 +02:00
|
|
|
pop {r4-r9}
|
|
|
|
|
bx lr
|
2013-10-06 09:24:09 +02:00
|
|
|
ENDP ; |vp9_idct8x8_64_add_neon|
|
2013-07-17 21:21:28 +02:00
|
|
|
|
2014-05-08 18:42:26 +02:00
|
|
|
;void vp9_idct8x8_12_add_neon(int16_t *input, uint8_t *dest, int dest_stride)
|
2013-08-17 01:36:07 +02:00
|
|
|
;
|
|
|
|
|
; r0 int16_t input
|
|
|
|
|
; r1 uint8_t *dest
|
|
|
|
|
; r2 int dest_stride)
|
|
|
|
|
|
2014-05-08 18:42:26 +02:00
|
|
|
|vp9_idct8x8_12_add_neon| PROC
|
2013-08-17 01:36:07 +02:00
|
|
|
push {r4-r9}
|
|
|
|
|
vpush {d8-d15}
|
|
|
|
|
vld1.s16 {q8,q9}, [r0]!
|
|
|
|
|
vld1.s16 {q10,q11}, [r0]!
|
|
|
|
|
vld1.s16 {q12,q13}, [r0]!
|
|
|
|
|
vld1.s16 {q14,q15}, [r0]!
|
|
|
|
|
|
|
|
|
|
; transpose the input data
|
|
|
|
|
TRANSPOSE8X8
|
|
|
|
|
|
|
|
|
|
; generate cospi_28_64 = 3196
|
|
|
|
|
mov r3, #0x0c00
|
|
|
|
|
add r3, #0x7c
|
|
|
|
|
|
|
|
|
|
; generate cospi_4_64 = 16069
|
|
|
|
|
mov r4, #0x3e00
|
|
|
|
|
add r4, #0xc5
|
|
|
|
|
|
|
|
|
|
; generate cospi_12_64 = 13623
|
|
|
|
|
mov r5, #0x3500
|
|
|
|
|
add r5, #0x37
|
|
|
|
|
|
|
|
|
|
; generate cospi_20_64 = 9102
|
|
|
|
|
mov r6, #0x2300
|
|
|
|
|
add r6, #0x8e
|
|
|
|
|
|
|
|
|
|
; generate cospi_16_64 = 11585
|
|
|
|
|
mov r7, #0x2d00
|
|
|
|
|
add r7, #0x41
|
|
|
|
|
|
|
|
|
|
; generate cospi_24_64 = 6270
|
|
|
|
|
mov r8, #0x1800
|
|
|
|
|
add r8, #0x7e
|
|
|
|
|
|
|
|
|
|
; generate cospi_8_64 = 15137
|
|
|
|
|
mov r9, #0x3b00
|
|
|
|
|
add r9, #0x21
|
|
|
|
|
|
|
|
|
|
; First transform rows
|
|
|
|
|
; stage 1
|
|
|
|
|
; The following instructions use vqrdmulh to do the
|
|
|
|
|
; dct_const_round_shift(input[1] * cospi_28_64). vqrdmulh will do doubling
|
|
|
|
|
; multiply and shift the result by 16 bits instead of 14 bits. So we need
|
|
|
|
|
; to double the constants before multiplying to compensate this.
|
|
|
|
|
mov r12, r3, lsl #1
|
|
|
|
|
vdup.16 q0, r12 ; duplicate cospi_28_64*2
|
|
|
|
|
mov r12, r4, lsl #1
|
|
|
|
|
vdup.16 q1, r12 ; duplicate cospi_4_64*2
|
|
|
|
|
|
|
|
|
|
; dct_const_round_shift(input[1] * cospi_28_64)
|
|
|
|
|
vqrdmulh.s16 q4, q9, q0
|
|
|
|
|
|
|
|
|
|
mov r12, r6, lsl #1
|
|
|
|
|
rsb r12, #0
|
|
|
|
|
vdup.16 q0, r12 ; duplicate -cospi_20_64*2
|
|
|
|
|
|
|
|
|
|
; dct_const_round_shift(input[1] * cospi_4_64)
|
|
|
|
|
vqrdmulh.s16 q7, q9, q1
|
|
|
|
|
|
|
|
|
|
mov r12, r5, lsl #1
|
|
|
|
|
vdup.16 q1, r12 ; duplicate cospi_12_64*2
|
|
|
|
|
|
|
|
|
|
; dct_const_round_shift(- input[3] * cospi_20_64)
|
|
|
|
|
vqrdmulh.s16 q5, q11, q0
|
|
|
|
|
|
|
|
|
|
mov r12, r7, lsl #1
|
|
|
|
|
vdup.16 q0, r12 ; duplicate cospi_16_64*2
|
|
|
|
|
|
|
|
|
|
; dct_const_round_shift(input[3] * cospi_12_64)
|
|
|
|
|
vqrdmulh.s16 q6, q11, q1
|
|
|
|
|
|
|
|
|
|
; stage 2 & stage 3 - even half
|
|
|
|
|
mov r12, r8, lsl #1
|
|
|
|
|
vdup.16 q1, r12 ; duplicate cospi_24_64*2
|
|
|
|
|
|
|
|
|
|
; dct_const_round_shift(input_dc * cospi_16_64)
|
|
|
|
|
vqrdmulh.s16 q9, q8, q0
|
|
|
|
|
|
|
|
|
|
mov r12, r9, lsl #1
|
|
|
|
|
vdup.16 q0, r12 ; duplicate cospi_8_64*2
|
|
|
|
|
|
|
|
|
|
; dct_const_round_shift(input[1] * cospi_24_64)
|
|
|
|
|
vqrdmulh.s16 q13, q10, q1
|
|
|
|
|
|
|
|
|
|
; dct_const_round_shift(input[1] * cospi_8_64)
|
|
|
|
|
vqrdmulh.s16 q15, q10, q0
|
|
|
|
|
|
|
|
|
|
; stage 3 -odd half
|
|
|
|
|
vdup.16 d16, r7 ; duplicate cospi_16_64
|
|
|
|
|
|
|
|
|
|
vadd.s16 q0, q9, q15 ; output[0] = step[0] + step[3]
|
|
|
|
|
vadd.s16 q1, q9, q13 ; output[1] = step[1] + step[2]
|
|
|
|
|
vsub.s16 q2, q9, q13 ; output[2] = step[1] - step[2]
|
|
|
|
|
vsub.s16 q3, q9, q15 ; output[3] = step[0] - step[3]
|
|
|
|
|
|
|
|
|
|
; stage 2 - odd half
|
|
|
|
|
vsub.s16 q13, q4, q5 ; step2[5] = step1[4] - step1[5]
|
|
|
|
|
vadd.s16 q4, q4, q5 ; step2[4] = step1[4] + step1[5]
|
|
|
|
|
vsub.s16 q14, q7, q6 ; step2[6] = -step1[6] + step1[7]
|
|
|
|
|
vadd.s16 q7, q7, q6 ; step2[7] = step1[6] + step1[7]
|
|
|
|
|
|
|
|
|
|
; step2[6] * cospi_16_64
|
|
|
|
|
vmull.s16 q9, d28, d16
|
|
|
|
|
vmull.s16 q10, d29, d16
|
|
|
|
|
|
2013-09-05 00:41:26 +02:00
|
|
|
; step2[6] * cospi_16_64
|
|
|
|
|
vmull.s16 q11, d28, d16
|
|
|
|
|
vmull.s16 q12, d29, d16
|
|
|
|
|
|
2013-08-17 01:36:07 +02:00
|
|
|
; (step2[6] - step2[5]) * cospi_16_64
|
|
|
|
|
vmlsl.s16 q9, d26, d16
|
|
|
|
|
vmlsl.s16 q10, d27, d16
|
|
|
|
|
|
2013-09-05 00:41:26 +02:00
|
|
|
; (step2[5] + step2[6]) * cospi_16_64
|
|
|
|
|
vmlal.s16 q11, d26, d16
|
|
|
|
|
vmlal.s16 q12, d27, d16
|
|
|
|
|
|
2013-08-17 01:36:07 +02:00
|
|
|
; dct_const_round_shift(input_dc * cospi_16_64)
|
|
|
|
|
vqrshrn.s32 d10, q9, #14 ; >> 14
|
|
|
|
|
vqrshrn.s32 d11, q10, #14 ; >> 14
|
|
|
|
|
|
|
|
|
|
; dct_const_round_shift(input_dc * cospi_16_64)
|
2013-09-05 00:41:26 +02:00
|
|
|
vqrshrn.s32 d12, q11, #14 ; >> 14
|
|
|
|
|
vqrshrn.s32 d13, q12, #14 ; >> 14
|
2013-08-17 01:36:07 +02:00
|
|
|
|
|
|
|
|
; stage 4
|
|
|
|
|
vadd.s16 q8, q0, q7 ; output[0] = step1[0] + step1[7];
|
|
|
|
|
vadd.s16 q9, q1, q6 ; output[1] = step1[1] + step1[6];
|
|
|
|
|
vadd.s16 q10, q2, q5 ; output[2] = step1[2] + step1[5];
|
|
|
|
|
vadd.s16 q11, q3, q4 ; output[3] = step1[3] + step1[4];
|
|
|
|
|
vsub.s16 q12, q3, q4 ; output[4] = step1[3] - step1[4];
|
|
|
|
|
vsub.s16 q13, q2, q5 ; output[5] = step1[2] - step1[5];
|
|
|
|
|
vsub.s16 q14, q1, q6 ; output[6] = step1[1] - step1[6];
|
|
|
|
|
vsub.s16 q15, q0, q7 ; output[7] = step1[0] - step1[7];
|
|
|
|
|
|
|
|
|
|
; Transpose the matrix
|
|
|
|
|
TRANSPOSE8X8
|
|
|
|
|
|
|
|
|
|
; Then transform columns
|
|
|
|
|
IDCT8x8_1D
|
|
|
|
|
|
|
|
|
|
; ROUND_POWER_OF_TWO(temp_out[j], 5)
|
|
|
|
|
vrshr.s16 q8, q8, #5
|
|
|
|
|
vrshr.s16 q9, q9, #5
|
|
|
|
|
vrshr.s16 q10, q10, #5
|
|
|
|
|
vrshr.s16 q11, q11, #5
|
|
|
|
|
vrshr.s16 q12, q12, #5
|
|
|
|
|
vrshr.s16 q13, q13, #5
|
|
|
|
|
vrshr.s16 q14, q14, #5
|
|
|
|
|
vrshr.s16 q15, q15, #5
|
|
|
|
|
|
|
|
|
|
; save dest pointer
|
|
|
|
|
mov r0, r1
|
|
|
|
|
|
|
|
|
|
; load destination data
|
|
|
|
|
vld1.64 {d0}, [r1], r2
|
|
|
|
|
vld1.64 {d1}, [r1], r2
|
|
|
|
|
vld1.64 {d2}, [r1], r2
|
|
|
|
|
vld1.64 {d3}, [r1], r2
|
|
|
|
|
vld1.64 {d4}, [r1], r2
|
|
|
|
|
vld1.64 {d5}, [r1], r2
|
|
|
|
|
vld1.64 {d6}, [r1], r2
|
|
|
|
|
vld1.64 {d7}, [r1]
|
|
|
|
|
|
|
|
|
|
; ROUND_POWER_OF_TWO(temp_out[j], 5) + dest[j * dest_stride + i]
|
|
|
|
|
vaddw.u8 q8, q8, d0
|
|
|
|
|
vaddw.u8 q9, q9, d1
|
|
|
|
|
vaddw.u8 q10, q10, d2
|
|
|
|
|
vaddw.u8 q11, q11, d3
|
|
|
|
|
vaddw.u8 q12, q12, d4
|
|
|
|
|
vaddw.u8 q13, q13, d5
|
|
|
|
|
vaddw.u8 q14, q14, d6
|
|
|
|
|
vaddw.u8 q15, q15, d7
|
|
|
|
|
|
|
|
|
|
; clip_pixel
|
|
|
|
|
vqmovun.s16 d0, q8
|
|
|
|
|
vqmovun.s16 d1, q9
|
|
|
|
|
vqmovun.s16 d2, q10
|
|
|
|
|
vqmovun.s16 d3, q11
|
|
|
|
|
vqmovun.s16 d4, q12
|
|
|
|
|
vqmovun.s16 d5, q13
|
|
|
|
|
vqmovun.s16 d6, q14
|
|
|
|
|
vqmovun.s16 d7, q15
|
|
|
|
|
|
|
|
|
|
; store the data
|
|
|
|
|
vst1.64 {d0}, [r0], r2
|
|
|
|
|
vst1.64 {d1}, [r0], r2
|
|
|
|
|
vst1.64 {d2}, [r0], r2
|
|
|
|
|
vst1.64 {d3}, [r0], r2
|
|
|
|
|
vst1.64 {d4}, [r0], r2
|
|
|
|
|
vst1.64 {d5}, [r0], r2
|
|
|
|
|
vst1.64 {d6}, [r0], r2
|
|
|
|
|
vst1.64 {d7}, [r0], r2
|
|
|
|
|
|
|
|
|
|
vpop {d8-d15}
|
|
|
|
|
pop {r4-r9}
|
|
|
|
|
bx lr
|
2014-05-08 18:42:26 +02:00
|
|
|
ENDP ; |vp9_idct8x8_12_add_neon|
|
2013-08-17 01:36:07 +02:00
|
|
|
|
2013-07-17 21:21:28 +02:00
|
|
|
END
|
