Add neon optimize vp9_short_idct8x8_add.
Change-Id: Ic32acf3e2939c6d12d9c2bf192a5f5da59705fda
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vp9/common/arm/neon/vp9_short_idct8x8_add_neon.asm
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356
vp9/common/arm/neon/vp9_short_idct8x8_add_neon.asm
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@ -0,0 +1,356 @@
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;
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; Copyright (c) 2013 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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EXPORT |vp9_short_idct8x8_add_neon|
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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; Parallel 1D IDCT on all the columns of a 8x8 16bit data matrix which are
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; loaded in q8-q15. The output will be stored back into q8-q15 registers.
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; This macro will touch q0-q7 registers and use them as buffer during
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; calculation.
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MACRO
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IDCT8x8_1D
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; stage 1
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vdup.16 d0, r3; ; duplicate cospi_28_64
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vdup.16 d1, r4; ; duplicate cospi_4_64
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; input[1] * cospi_28_64
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vmull.s16 q2, d18, d0
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vmull.s16 q3, d19, d0
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; input[7] * cospi_4_64
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vmull.s16 q4, d30, d1
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vmull.s16 q5, d31, d1
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; input[1]*cospi_28_64-input[7]*cospi_4_64
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vsub.s32 q6, q2, q4
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vsub.s32 q7, q3, q5
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d8, q6, #14 ; >> 14
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vqrshrn.s32 d9, q7, #14 ; >> 14
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; input[1] * cospi_4_64
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vmull.s16 q2, d18, d1
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vmull.s16 q3, d19, d1
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; input[7] * cospi_28_64
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vmull.s16 q1, d30, d0
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vmull.s16 q5, d31, d0
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; input[1]*cospi_4_64+input[7]*cospi_28_64
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vadd.s32 q2, q2, q1
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vadd.s32 q3, q3, q5
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d14, q2, #14 ; >> 14
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vqrshrn.s32 d15, q3, #14 ; >> 14
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vdup.16 d0, r5; ; duplicate cospi_12_64
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vdup.16 d1, r6; ; duplicate cospi_20_64
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; input[5] * cospi_12_64
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vmull.s16 q2, d26, d0
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vmull.s16 q3, d27, d0
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; input[3] * cospi_20_64
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vmull.s16 q5, d22, d1
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vmull.s16 q6, d23, d1
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; input[5] * cospi_12_64 - input[3] * cospi_20_64
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vsub.s32 q2, q2, q5
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vsub.s32 q3, q3, q6
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d10, q2, #14 ; >> 14
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vqrshrn.s32 d11, q3, #14 ; >> 14
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; input[5] * cospi_20_64
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vmull.s16 q2, d26, d1
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vmull.s16 q3, d27, d1
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; input[3] * cospi_12_64
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vmull.s16 q9, d22, d0
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vmull.s16 q15, d23, d0
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; input[5] * cospi_20_64 + input[3] * cospi_12_64
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vadd.s32 q0, q2, q9
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vadd.s32 q1, q3, q15
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d12, q0, #14 ; >> 14
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vqrshrn.s32 d13, q1, #14 ; >> 14
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; stage 2 & stage 3 - even half
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vdup.16 d0, r7; ; duplicate cospi_16_64
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; input[0] * cospi_16_64
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vmull.s16 q2, d16, d0
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vmull.s16 q3, d17, d0
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; input[2] * cospi_16_64
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vmull.s16 q9, d24, d0
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vmull.s16 q11, d25, d0
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; (input[0] + input[2]) * cospi_16_64
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vadd.s32 q9, q2, q9
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vadd.s32 q11, q3, q11
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d18, q9, #14 ; >> 14
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vqrshrn.s32 d19, q11, #14 ; >> 14
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; input[0] * cospi_16_64
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vmull.s16 q2, d16, d0
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vmull.s16 q3, d17, d0
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; input[2] * cospi_16_64
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vmull.s16 q13, d24, d0
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vmull.s16 q15, d25, d0
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; (input[0] - input[2]) * cospi_16_64
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vsub.s32 q2, q2, q13
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vsub.s32 q3, q3, q15
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d22, q2, #14 ; >> 14
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vqrshrn.s32 d23, q3, #14 ; >> 14
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; input[1] * cospi_24_64 - input[3] * cospi_8_64
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vdup.16 d0, r8; ; duplicate cospi_24_64
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vdup.16 d1, r9; ; duplicate cospi_8_64
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; input[1] * cospi_24_64
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vmull.s16 q2, d20, d0
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vmull.s16 q3, d21, d0
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; input[3] * cospi_8_64
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vmull.s16 q13, d28, d1
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vmull.s16 q15, d29, d1
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; input[1] * cospi_24_64 - input[3] * cospi_8_64
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vsub.s32 q2, q2, q13
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vsub.s32 q3, q3, q15
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d26, q2, #14 ; >> 14
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vqrshrn.s32 d27, q3, #14 ; >> 14
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; input[1] * cospi_8_64
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vmull.s16 q2, d20, d1
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vmull.s16 q3, d21, d1
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; input[3] * cospi_24_64
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vmull.s16 q8, d28, d0
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vmull.s16 q10, d29, d0
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; input[1] * cospi_8_64 + input[3] * cospi_24_64
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vadd.s32 q0, q2, q8
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vadd.s32 q1, q3, q10
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d30, q0, #14 ; >> 14
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vqrshrn.s32 d31, q1, #14 ; >> 14
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vadd.s16 q0, q9, q15 ; output[0] = step[0] + step[3]
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vadd.s16 q1, q11, q13 ; output[1] = step[1] + step[2]
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vsub.s16 q2, q11, q13 ; output[2] = step[1] - step[2]
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vsub.s16 q3, q9, q15 ; output[3] = step[0] - step[3]
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; stage 2 - odd half
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vsub.s16 q13, q4, q5 ; step2[5] = step1[4] - step1[5]
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vadd.s16 q4, q4, q5 ; step2[4] = step1[4] + step1[5]
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vsub.s16 q14, q7, q6 ; step2[6] = -step1[6] + step1[7]
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vadd.s16 q7, q7, q6 ; step2[7] = step1[6] + step1[7]
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; stage 3 -odd half
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vdup.16 d16, r7; ; duplicate cospi_16_64
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; step2[6] * cospi_16_64
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vmull.s16 q9, d28, d16
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vmull.s16 q10, d29, d16
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; step2[5] * cospi_16_64
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vmull.s16 q11, d26, d16
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vmull.s16 q12, d27, d16
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; (step2[6] - step2[5]) * cospi_16_64
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vsub.s32 q9, q9, q11
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vsub.s32 q10, q10, q12
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d10, q9, #14 ; >> 14
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vqrshrn.s32 d11, q10, #14 ; >> 14
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; step2[6] * cospi_16_64
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vmull.s16 q9, d28, d16
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vmull.s16 q10, d29, d16
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; step2[5] * cospi_16_64
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vmull.s16 q11, d26, d16
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vmull.s16 q12, d27, d16
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; (step2[5] + step2[6]) * cospi_16_64
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vadd.s32 q9, q9, q11
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vadd.s32 q10, q10, q12
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; dct_const_round_shift(input_dc * cospi_16_64)
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vqrshrn.s32 d12, q9, #14 ; >> 14
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vqrshrn.s32 d13, q10, #14 ; >> 14
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; stage 4
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vadd.s16 q8, q0, q7; ; output[0] = step1[0] + step1[7];
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vadd.s16 q9, q1, q6; ; output[1] = step1[1] + step1[6];
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vadd.s16 q10, q2, q5; ; output[2] = step1[2] + step1[5];
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vadd.s16 q11, q3, q4; ; output[3] = step1[3] + step1[4];
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vsub.s16 q12, q3, q4; ; output[4] = step1[3] - step1[4];
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vsub.s16 q13, q2, q5; ; output[5] = step1[2] - step1[5];
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vsub.s16 q14, q1, q6; ; output[6] = step1[1] - step1[6];
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vsub.s16 q15, q0, q7; ; output[7] = step1[0] - step1[7];
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MEND
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; Transpose a 8x8 16bit data matrix. Datas are loaded in q8-q15.
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MACRO
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TRANSPOSE8X8
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vswp d17, d24
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vswp d23, d30
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vswp d21, d28
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vswp d19, d26
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vtrn.32 q8, q10
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vtrn.32 q9, q11
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vtrn.32 q12, q14
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vtrn.32 q13, q15
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vtrn.16 q8, q9
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vtrn.16 q10, q11
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vtrn.16 q12, q13
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vtrn.16 q14, q15
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MEND
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AREA Block, CODE, READONLY ; name this block of code
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;void vp9_short_idct8x8_add_neon(int16_t *input, uint8_t *dest, int dest_stride)
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;
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; r0 int16_t input
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; r1 uint8_t *dest
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; r2 int dest_stride)
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|vp9_short_idct8x8_add_neon| PROC
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push {r4-r9}
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vld1.s16 {q8}, [r0]!
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vld1.s16 {q9}, [r0]!
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vld1.s16 {q10}, [r0]!
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vld1.s16 {q11}, [r0]!
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vld1.s16 {q12}, [r0]!
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vld1.s16 {q13}, [r0]!
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vld1.s16 {q14}, [r0]!
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vld1.s16 {q15}, [r0]!
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; transpose the input data
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TRANSPOSE8X8
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; generate cospi_28_64 = 3196
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mov r3, #0x0c00
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add r3, #0x7c
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; generate cospi_4_64 = 16069
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mov r4, #0x3e00
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add r4, #0xc5
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; generate cospi_12_64 = 13623
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mov r5, #0x3500
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add r5, #0x37
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; generate cospi_20_64 = 9102
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mov r6, #0x2300
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add r6, #0x8e
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; generate cospi_16_64 = 11585
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mov r7, #0x2d00
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add r7, #0x41
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; generate cospi_24_64 = 6270
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mov r8, #0x1800
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add r8, #0x7e
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; generate cospi_8_64 = 15137
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mov r9, #0x3b00
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add r9, #0x21
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; First transform rows
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IDCT8x8_1D
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; Transpose the matrix
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TRANSPOSE8X8
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; Then transform columns
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IDCT8x8_1D
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; ROUND_POWER_OF_TWO(temp_out[j], 5)
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vrshr.s16 q8, q8, #5
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vrshr.s16 q9, q9, #5
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vrshr.s16 q10, q10, #5
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vrshr.s16 q11, q11, #5
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vrshr.s16 q12, q12, #5
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vrshr.s16 q13, q13, #5
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vrshr.s16 q14, q14, #5
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vrshr.s16 q15, q15, #5
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; save dest pointer
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mov r0, r1
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; load destination data
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vld1.u8 {d0}, [r1], r2
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vld1.u8 {d1}, [r1], r2
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vld1.s16 {d2}, [r1], r2
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vld1.s16 {d3}, [r1], r2
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vld1.s16 {d4}, [r1], r2
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vld1.s16 {d5}, [r1], r2
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vld1.s16 {d6}, [r1], r2
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vld1.s16 {d7}, [r1]
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; ROUND_POWER_OF_TWO(temp_out[j], 5) + dest[j * dest_stride + i]
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vaddw.u8 q8, q8, d0
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vaddw.u8 q9, q9, d1
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vaddw.u8 q10, q10, d2
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vaddw.u8 q11, q11, d3
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vaddw.u8 q12, q12, d4
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vaddw.u8 q13, q13, d5
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vaddw.u8 q14, q14, d6
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vaddw.u8 q15, q15, d7
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; clip_pixel
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vqmovun.s16 d0, q8
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vqmovun.s16 d1, q9
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vqmovun.s16 d2, q10
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vqmovun.s16 d3, q11
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vqmovun.s16 d4, q12
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vqmovun.s16 d5, q13
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vqmovun.s16 d6, q14
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vqmovun.s16 d7, q15
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; store the data
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vst1.64 {d0}, [r0], r2
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vst1.64 {d1}, [r0], r2
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vst1.64 {d2}, [r0], r2
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vst1.64 {d3}, [r0], r2
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vst1.64 {d4}, [r0], r2
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vst1.64 {d5}, [r0], r2
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vst1.64 {d6}, [r0], r2
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vst1.64 {d7}, [r0], r2
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pop {r4-r9}
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bx lr
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ENDP ; |vp9_short_idct8x8_add_neon|
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END
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@ -298,7 +298,7 @@ prototype void vp9_short_idct4x4_add "int16_t *input, uint8_t *dest, int dest_st
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specialize vp9_short_idct4x4_add sse2
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prototype void vp9_short_idct8x8_add "int16_t *input, uint8_t *dest, int dest_stride"
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specialize vp9_short_idct8x8_add sse2
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specialize vp9_short_idct8x8_add sse2 neon
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prototype void vp9_short_idct10_8x8_add "int16_t *input, uint8_t *dest, int dest_stride"
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specialize vp9_short_idct10_8x8_add sse2
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@ -90,5 +90,6 @@ VP9_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/vp9_convolve8_neon$(ASM)
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VP9_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/vp9_convolve8_avg_neon$(ASM)
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VP9_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/vp9_loopfilter_neon$(ASM)
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VP9_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/vp9_dc_only_idct_add_neon$(ASM)
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VP9_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/vp9_short_idct8x8_add_neon$(ASM)
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$(eval $(call rtcd_h_template,vp9_rtcd,vp9/common/vp9_rtcd_defs.sh))
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