2010-05-18 17:58:33 +02:00
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/*
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2010-09-09 14:16:39 +02:00
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* Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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2010-05-18 17:58:33 +02:00
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*
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2010-06-18 18:39:21 +02:00
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* Use of this source code is governed by a BSD-style license
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2010-06-04 22:19:40 +02:00
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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2010-06-18 18:39:21 +02:00
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* in the file PATENTS. All contributing project authors may
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2010-06-04 22:19:40 +02:00
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* be found in the AUTHORS file in the root of the source tree.
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2010-05-18 17:58:33 +02:00
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*/
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2011-02-10 20:41:38 +01:00
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#include "vp8/common/onyxc_int.h"
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2010-05-18 17:58:33 +02:00
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#if CONFIG_POSTPROC
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2011-02-10 20:41:38 +01:00
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#include "vp8/common/postproc.h"
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2010-05-18 17:58:33 +02:00
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#endif
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2011-02-10 20:41:38 +01:00
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#include "vp8/common/onyxd.h"
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2010-05-18 17:58:33 +02:00
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#include "onyxd_int.h"
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#include "vpx_mem/vpx_mem.h"
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2011-02-10 20:41:38 +01:00
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#include "vp8/common/alloccommon.h"
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#include "vp8/common/loopfilter.h"
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#include "vp8/common/swapyv12buffer.h"
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#include "vp8/common/threading.h"
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2010-05-18 17:58:33 +02:00
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#include "decoderthreading.h"
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#include <stdio.h>
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2011-06-01 21:41:12 +02:00
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#include <assert.h>
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2010-08-11 17:02:31 +02:00
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2011-02-10 20:41:38 +01:00
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#include "vp8/common/quant_common.h"
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2010-05-18 17:58:33 +02:00
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#include "vpx_scale/vpxscale.h"
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2011-02-10 20:41:38 +01:00
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#include "vp8/common/systemdependent.h"
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2010-05-18 17:58:33 +02:00
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#include "vpx_ports/vpx_timer.h"
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2010-08-12 15:05:37 +02:00
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#include "detokenize.h"
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2011-05-02 15:30:51 +02:00
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#if CONFIG_ERROR_CONCEALMENT
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#include "error_concealment.h"
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#endif
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Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
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#if ARCH_ARM
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#include "vpx_ports/arm.h"
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#endif
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2010-05-18 17:58:33 +02:00
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extern void vp8_init_loop_filter(VP8_COMMON *cm);
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extern void vp8cx_init_de_quantizer(VP8D_COMP *pbi);
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2011-05-23 13:47:33 +02:00
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static int get_free_fb (VP8_COMMON *cm);
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static void ref_cnt_fb (int *buf, int *idx, int new_idx);
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2010-05-18 17:58:33 +02:00
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2011-12-21 01:54:54 +01:00
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struct VP8D_COMP * vp8dx_create_decompressor(VP8D_CONFIG *oxcf)
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2010-05-18 17:58:33 +02:00
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{
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VP8D_COMP *pbi = vpx_memalign(32, sizeof(VP8D_COMP));
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if (!pbi)
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return NULL;
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vpx_memset(pbi, 0, sizeof(VP8D_COMP));
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if (setjmp(pbi->common.error.jmp))
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{
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pbi->common.error.setjmp = 0;
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vp8dx_remove_decompressor(pbi);
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return 0;
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}
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pbi->common.error.setjmp = 1;
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vp8_create_common(&pbi->common);
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pbi->common.current_video_frame = 0;
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pbi->ready_for_new_data = 1;
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2011-02-05 06:29:25 +01:00
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#if CONFIG_MULTITHREAD
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2010-05-18 17:58:33 +02:00
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pbi->max_threads = oxcf->max_threads;
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vp8_decoder_create_threads(pbi);
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2011-02-05 06:29:25 +01:00
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#endif
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2010-05-18 17:58:33 +02:00
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2010-10-28 01:04:02 +02:00
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/* vp8cx_init_de_quantizer() is first called here. Add check in frame_init_dequantizer() to avoid
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* unnecessary calling of vp8cx_init_de_quantizer() for every frame.
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*/
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2010-05-18 17:58:33 +02:00
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vp8cx_init_de_quantizer(pbi);
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2011-07-20 21:53:42 +02:00
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vp8_loop_filter_init(&pbi->common);
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2010-05-18 17:58:33 +02:00
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pbi->common.error.setjmp = 0;
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2011-05-02 15:30:51 +02:00
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#if CONFIG_ERROR_CONCEALMENT
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pbi->ec_enabled = oxcf->error_concealment;
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2012-04-24 14:33:44 +02:00
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pbi->overlaps = NULL;
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2011-05-02 15:30:51 +02:00
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#else
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pbi->ec_enabled = 0;
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#endif
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2011-08-08 10:56:20 +02:00
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/* Error concealment is activated after a key frame has been
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* decoded without errors when error concealment is enabled.
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*/
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pbi->ec_active = 0;
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pbi->decoded_key_frame = 0;
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2011-05-02 15:30:51 +02:00
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2011-09-29 09:17:09 +02:00
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pbi->input_fragments = oxcf->input_fragments;
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pbi->num_fragments = 0;
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2011-06-13 16:42:27 +02:00
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2011-08-08 10:56:20 +02:00
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/* Independent partitions is activated when a frame updates the
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* token probability table to have equal probabilities over the
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* PREV_COEF context.
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*/
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pbi->independent_partitions = 0;
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2012-04-23 14:20:07 +02:00
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vp8_setup_block_dptrs(&pbi->mb);
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2011-12-21 01:54:54 +01:00
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return pbi;
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2010-05-18 17:58:33 +02:00
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}
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2011-12-21 01:54:54 +01:00
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void vp8dx_remove_decompressor(VP8D_COMP *pbi)
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2010-05-18 17:58:33 +02:00
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{
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if (!pbi)
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return;
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2010-09-16 20:08:52 +02:00
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#if CONFIG_MULTITHREAD
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if (pbi->b_multithreaded_rd)
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vp8mt_de_alloc_temp_buffers(pbi, pbi->common.mb_rows);
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2010-05-18 17:58:33 +02:00
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vp8_decoder_remove_threads(pbi);
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2011-05-02 15:30:51 +02:00
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#endif
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#if CONFIG_ERROR_CONCEALMENT
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vp8_de_alloc_overlap_lists(pbi);
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2011-02-05 06:29:25 +01:00
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#endif
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2010-05-18 17:58:33 +02:00
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vp8_remove_common(&pbi->common);
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2011-06-14 02:29:49 +02:00
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vpx_free(pbi->mbc);
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2010-05-18 17:58:33 +02:00
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vpx_free(pbi);
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}
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2011-12-21 01:54:54 +01:00
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vpx_codec_err_t vp8dx_get_reference(VP8D_COMP *pbi, VP8_REFFRAME ref_frame_flag, YV12_BUFFER_CONFIG *sd)
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2010-05-18 17:58:33 +02:00
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{
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VP8_COMMON *cm = &pbi->common;
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2010-07-22 14:07:32 +02:00
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int ref_fb_idx;
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2010-05-18 17:58:33 +02:00
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if (ref_frame_flag == VP8_LAST_FLAG)
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2010-07-22 14:07:32 +02:00
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ref_fb_idx = cm->lst_fb_idx;
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2010-05-18 17:58:33 +02:00
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else if (ref_frame_flag == VP8_GOLD_FLAG)
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2010-07-22 14:07:32 +02:00
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ref_fb_idx = cm->gld_fb_idx;
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2010-05-18 17:58:33 +02:00
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else if (ref_frame_flag == VP8_ALT_FLAG)
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2010-07-22 14:07:32 +02:00
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ref_fb_idx = cm->alt_fb_idx;
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2011-06-22 18:41:17 +02:00
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else{
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vpx_internal_error(&pbi->common.error, VPX_CODEC_ERROR,
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"Invalid reference frame");
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return pbi->common.error.error_code;
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}
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2010-05-18 17:58:33 +02:00
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2011-06-22 18:41:17 +02:00
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if(cm->yv12_fb[ref_fb_idx].y_height != sd->y_height ||
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cm->yv12_fb[ref_fb_idx].y_width != sd->y_width ||
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cm->yv12_fb[ref_fb_idx].uv_height != sd->uv_height ||
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cm->yv12_fb[ref_fb_idx].uv_width != sd->uv_width){
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vpx_internal_error(&pbi->common.error, VPX_CODEC_ERROR,
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"Incorrect buffer dimensions");
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}
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else
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2012-04-19 14:55:03 +02:00
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vp8_yv12_copy_frame(&cm->yv12_fb[ref_fb_idx], sd);
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2010-07-22 14:07:32 +02:00
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2011-06-22 18:41:17 +02:00
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return pbi->common.error.error_code;
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2010-05-18 17:58:33 +02:00
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}
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2011-03-17 22:07:59 +01:00
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2011-12-21 01:54:54 +01:00
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vpx_codec_err_t vp8dx_set_reference(VP8D_COMP *pbi, VP8_REFFRAME ref_frame_flag, YV12_BUFFER_CONFIG *sd)
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2010-05-18 17:58:33 +02:00
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{
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VP8_COMMON *cm = &pbi->common;
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2011-05-23 13:47:33 +02:00
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int *ref_fb_ptr = NULL;
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int free_fb;
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2010-05-18 17:58:33 +02:00
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if (ref_frame_flag == VP8_LAST_FLAG)
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2011-06-01 21:41:12 +02:00
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ref_fb_ptr = &cm->lst_fb_idx;
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2010-05-18 17:58:33 +02:00
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else if (ref_frame_flag == VP8_GOLD_FLAG)
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2011-06-01 21:41:12 +02:00
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ref_fb_ptr = &cm->gld_fb_idx;
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2010-05-18 17:58:33 +02:00
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else if (ref_frame_flag == VP8_ALT_FLAG)
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2011-06-01 21:41:12 +02:00
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ref_fb_ptr = &cm->alt_fb_idx;
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2011-06-22 18:41:17 +02:00
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else{
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vpx_internal_error(&pbi->common.error, VPX_CODEC_ERROR,
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"Invalid reference frame");
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return pbi->common.error.error_code;
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}
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2011-05-23 13:47:33 +02:00
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2011-06-22 18:41:17 +02:00
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if(cm->yv12_fb[*ref_fb_ptr].y_height != sd->y_height ||
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cm->yv12_fb[*ref_fb_ptr].y_width != sd->y_width ||
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cm->yv12_fb[*ref_fb_ptr].uv_height != sd->uv_height ||
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cm->yv12_fb[*ref_fb_ptr].uv_width != sd->uv_width){
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vpx_internal_error(&pbi->common.error, VPX_CODEC_ERROR,
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"Incorrect buffer dimensions");
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}
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else{
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/* Find an empty frame buffer. */
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free_fb = get_free_fb(cm);
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/* Decrease fb_idx_ref_cnt since it will be increased again in
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* ref_cnt_fb() below. */
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cm->fb_idx_ref_cnt[free_fb]--;
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/* Manage the reference counters and copy image. */
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ref_cnt_fb (cm->fb_idx_ref_cnt, ref_fb_ptr, free_fb);
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2012-04-19 14:55:03 +02:00
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vp8_yv12_copy_frame(sd, &cm->yv12_fb[*ref_fb_ptr]);
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2011-06-22 18:41:17 +02:00
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}
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2010-07-22 14:07:32 +02:00
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2011-06-22 18:41:17 +02:00
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return pbi->common.error.error_code;
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2010-05-18 17:58:33 +02:00
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}
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2010-10-28 01:04:02 +02:00
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/*For ARM NEON, d8-d15 are callee-saved registers, and need to be saved by us.*/
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2012-01-20 00:18:31 +01:00
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#if HAVE_NEON
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2011-07-26 03:44:59 +02:00
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extern void vp8_push_neon(int64_t *store);
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extern void vp8_pop_neon(int64_t *store);
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2010-05-18 17:58:33 +02:00
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#endif
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2010-07-22 14:07:32 +02:00
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static int get_free_fb (VP8_COMMON *cm)
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{
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int i;
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for (i = 0; i < NUM_YV12_BUFFERS; i++)
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if (cm->fb_idx_ref_cnt[i] == 0)
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break;
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2011-06-01 21:41:12 +02:00
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assert(i < NUM_YV12_BUFFERS);
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2010-07-22 14:07:32 +02:00
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cm->fb_idx_ref_cnt[i] = 1;
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return i;
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}
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static void ref_cnt_fb (int *buf, int *idx, int new_idx)
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{
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if (buf[*idx] > 0)
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buf[*idx]--;
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*idx = new_idx;
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buf[new_idx]++;
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}
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2010-10-28 01:04:02 +02:00
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/* If any buffer copy / swapping is signalled it should be done here. */
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2010-07-22 14:07:32 +02:00
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static int swap_frame_buffers (VP8_COMMON *cm)
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{
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fix last frame buffer copy logic regression
Commit 0ce3901 introduced a change in the frame buffer copy logic where
the NEW frame could be copied to the ARF or GF buffer through the
copy_buffer_to_{arf,gf}==1 flags, if the LAST frame was not being
refreshed. This is not correct. The intent of the
copy_buffer_to_{arf,gf}==1 flag is to copy the LAST buffer. To copy the
NEW buffer, the refresh_{alt_ref,golden}_frame flag should be used.
The original buffer copy logic is fairly convoluted. For example:
if (cm->refresh_last_frame)
{
vp8_swap_yv12_buffer(&cm->last_frame, &cm->new_frame);
cm->frame_to_show = &cm->last_frame;
}
else
{
cm->frame_to_show = &cm->new_frame;
}
...
if (cm->copy_buffer_to_arf)
{
if (cm->copy_buffer_to_arf == 1)
{
if (cm->refresh_last_frame)
vp8_yv12_copy_frame_ptr(&cm->new_frame, &cm->alt_ref_frame);
else
vp8_yv12_copy_frame_ptr(&cm->last_frame, &cm->alt_ref_frame);
}
else if (cm->copy_buffer_to_arf == 2)
vp8_yv12_copy_frame_ptr(&cm->golden_frame, &cm->alt_ref_frame);
}
Effectively, if refresh_last_frame, then new and last are swapped, so
when "new" is copied to ARF, it's equivalent to copying LAST to ARF. If
not refresh_last_frame, then LAST is copied to ARF. So LAST is copied to
ARF in both cases.
Commit 0ce3901 removed the first buffer swap but kept the
refresh_last_frame?new:last behavior, changing the sense since the first
swap wasn't done to the more readable refresh_last_frame?last:new, but
this logic is not correct when !refresh_last_frame.
This commit restores the correct behavior from v0.9.1 and prior. This
case is missing from the test vector set.
Change-Id: I8369fc13a37ae882e31a8a104da808a08bc8428f
2011-01-06 19:07:39 +01:00
|
|
|
int err = 0;
|
2010-07-22 14:07:32 +02:00
|
|
|
|
2010-10-28 01:04:02 +02:00
|
|
|
/* The alternate reference frame or golden frame can be updated
|
|
|
|
|
* using the new, last, or golden/alt ref frame. If it
|
|
|
|
|
* is updated using the newly decoded frame it is a refresh.
|
|
|
|
|
* An update using the last or golden/alt ref frame is a copy.
|
|
|
|
|
*/
|
2010-07-22 14:07:32 +02:00
|
|
|
if (cm->copy_buffer_to_arf)
|
|
|
|
|
{
|
|
|
|
|
int new_fb = 0;
|
|
|
|
|
|
|
|
|
|
if (cm->copy_buffer_to_arf == 1)
|
fix last frame buffer copy logic regression
Commit 0ce3901 introduced a change in the frame buffer copy logic where
the NEW frame could be copied to the ARF or GF buffer through the
copy_buffer_to_{arf,gf}==1 flags, if the LAST frame was not being
refreshed. This is not correct. The intent of the
copy_buffer_to_{arf,gf}==1 flag is to copy the LAST buffer. To copy the
NEW buffer, the refresh_{alt_ref,golden}_frame flag should be used.
The original buffer copy logic is fairly convoluted. For example:
if (cm->refresh_last_frame)
{
vp8_swap_yv12_buffer(&cm->last_frame, &cm->new_frame);
cm->frame_to_show = &cm->last_frame;
}
else
{
cm->frame_to_show = &cm->new_frame;
}
...
if (cm->copy_buffer_to_arf)
{
if (cm->copy_buffer_to_arf == 1)
{
if (cm->refresh_last_frame)
vp8_yv12_copy_frame_ptr(&cm->new_frame, &cm->alt_ref_frame);
else
vp8_yv12_copy_frame_ptr(&cm->last_frame, &cm->alt_ref_frame);
}
else if (cm->copy_buffer_to_arf == 2)
vp8_yv12_copy_frame_ptr(&cm->golden_frame, &cm->alt_ref_frame);
}
Effectively, if refresh_last_frame, then new and last are swapped, so
when "new" is copied to ARF, it's equivalent to copying LAST to ARF. If
not refresh_last_frame, then LAST is copied to ARF. So LAST is copied to
ARF in both cases.
Commit 0ce3901 removed the first buffer swap but kept the
refresh_last_frame?new:last behavior, changing the sense since the first
swap wasn't done to the more readable refresh_last_frame?last:new, but
this logic is not correct when !refresh_last_frame.
This commit restores the correct behavior from v0.9.1 and prior. This
case is missing from the test vector set.
Change-Id: I8369fc13a37ae882e31a8a104da808a08bc8428f
2011-01-06 19:07:39 +01:00
|
|
|
new_fb = cm->lst_fb_idx;
|
2010-07-22 14:07:32 +02:00
|
|
|
else if (cm->copy_buffer_to_arf == 2)
|
|
|
|
|
new_fb = cm->gld_fb_idx;
|
|
|
|
|
else
|
|
|
|
|
err = -1;
|
|
|
|
|
|
|
|
|
|
ref_cnt_fb (cm->fb_idx_ref_cnt, &cm->alt_fb_idx, new_fb);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cm->copy_buffer_to_gf)
|
|
|
|
|
{
|
|
|
|
|
int new_fb = 0;
|
|
|
|
|
|
|
|
|
|
if (cm->copy_buffer_to_gf == 1)
|
fix last frame buffer copy logic regression
Commit 0ce3901 introduced a change in the frame buffer copy logic where
the NEW frame could be copied to the ARF or GF buffer through the
copy_buffer_to_{arf,gf}==1 flags, if the LAST frame was not being
refreshed. This is not correct. The intent of the
copy_buffer_to_{arf,gf}==1 flag is to copy the LAST buffer. To copy the
NEW buffer, the refresh_{alt_ref,golden}_frame flag should be used.
The original buffer copy logic is fairly convoluted. For example:
if (cm->refresh_last_frame)
{
vp8_swap_yv12_buffer(&cm->last_frame, &cm->new_frame);
cm->frame_to_show = &cm->last_frame;
}
else
{
cm->frame_to_show = &cm->new_frame;
}
...
if (cm->copy_buffer_to_arf)
{
if (cm->copy_buffer_to_arf == 1)
{
if (cm->refresh_last_frame)
vp8_yv12_copy_frame_ptr(&cm->new_frame, &cm->alt_ref_frame);
else
vp8_yv12_copy_frame_ptr(&cm->last_frame, &cm->alt_ref_frame);
}
else if (cm->copy_buffer_to_arf == 2)
vp8_yv12_copy_frame_ptr(&cm->golden_frame, &cm->alt_ref_frame);
}
Effectively, if refresh_last_frame, then new and last are swapped, so
when "new" is copied to ARF, it's equivalent to copying LAST to ARF. If
not refresh_last_frame, then LAST is copied to ARF. So LAST is copied to
ARF in both cases.
Commit 0ce3901 removed the first buffer swap but kept the
refresh_last_frame?new:last behavior, changing the sense since the first
swap wasn't done to the more readable refresh_last_frame?last:new, but
this logic is not correct when !refresh_last_frame.
This commit restores the correct behavior from v0.9.1 and prior. This
case is missing from the test vector set.
Change-Id: I8369fc13a37ae882e31a8a104da808a08bc8428f
2011-01-06 19:07:39 +01:00
|
|
|
new_fb = cm->lst_fb_idx;
|
2010-07-22 14:07:32 +02:00
|
|
|
else if (cm->copy_buffer_to_gf == 2)
|
|
|
|
|
new_fb = cm->alt_fb_idx;
|
|
|
|
|
else
|
|
|
|
|
err = -1;
|
|
|
|
|
|
|
|
|
|
ref_cnt_fb (cm->fb_idx_ref_cnt, &cm->gld_fb_idx, new_fb);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cm->refresh_golden_frame)
|
|
|
|
|
ref_cnt_fb (cm->fb_idx_ref_cnt, &cm->gld_fb_idx, cm->new_fb_idx);
|
|
|
|
|
|
|
|
|
|
if (cm->refresh_alt_ref_frame)
|
|
|
|
|
ref_cnt_fb (cm->fb_idx_ref_cnt, &cm->alt_fb_idx, cm->new_fb_idx);
|
|
|
|
|
|
|
|
|
|
if (cm->refresh_last_frame)
|
|
|
|
|
{
|
|
|
|
|
ref_cnt_fb (cm->fb_idx_ref_cnt, &cm->lst_fb_idx, cm->new_fb_idx);
|
|
|
|
|
|
|
|
|
|
cm->frame_to_show = &cm->yv12_fb[cm->lst_fb_idx];
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
cm->frame_to_show = &cm->yv12_fb[cm->new_fb_idx];
|
|
|
|
|
|
|
|
|
|
cm->fb_idx_ref_cnt[cm->new_fb_idx]--;
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-21 01:54:54 +01:00
|
|
|
int vp8dx_receive_compressed_data(VP8D_COMP *pbi, unsigned long size, const unsigned char *source, int64_t time_stamp)
|
2010-05-18 17:58:33 +02:00
|
|
|
{
|
2012-01-20 00:18:31 +01:00
|
|
|
#if HAVE_NEON
|
2011-07-26 03:44:59 +02:00
|
|
|
int64_t dx_store_reg[8];
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#endif
|
2010-05-18 17:58:33 +02:00
|
|
|
VP8_COMMON *cm = &pbi->common;
|
|
|
|
|
int retcode = 0;
|
|
|
|
|
|
2010-10-28 01:04:02 +02:00
|
|
|
/*if(pbi->ready_for_new_data == 0)
|
|
|
|
|
return -1;*/
|
2010-05-18 17:58:33 +02:00
|
|
|
|
2011-12-21 01:54:54 +01:00
|
|
|
if (pbi == 0)
|
2010-05-18 17:58:33 +02:00
|
|
|
{
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
pbi->common.error.error_code = VPX_CODEC_OK;
|
|
|
|
|
|
2011-09-29 09:17:09 +02:00
|
|
|
if (pbi->num_fragments == 0)
|
2010-12-16 16:46:31 +01:00
|
|
|
{
|
2011-09-29 09:17:09 +02:00
|
|
|
/* New frame, reset fragment pointers and sizes */
|
2012-05-08 20:45:35 +02:00
|
|
|
vpx_memset((void*)pbi->fragments, 0, sizeof(pbi->fragments));
|
2011-09-29 09:17:09 +02:00
|
|
|
vpx_memset(pbi->fragment_sizes, 0, sizeof(pbi->fragment_sizes));
|
|
|
|
|
}
|
|
|
|
|
if (pbi->input_fragments && !(source == NULL && size == 0))
|
|
|
|
|
{
|
|
|
|
|
/* Store a pointer to this fragment and return. We haven't
|
2011-06-13 16:42:27 +02:00
|
|
|
* received the complete frame yet, so we will wait with decoding.
|
2011-05-02 15:30:51 +02:00
|
|
|
*/
|
2011-09-29 09:17:09 +02:00
|
|
|
assert(pbi->num_fragments < MAX_PARTITIONS);
|
|
|
|
|
pbi->fragments[pbi->num_fragments] = source;
|
|
|
|
|
pbi->fragment_sizes[pbi->num_fragments] = size;
|
|
|
|
|
pbi->num_fragments++;
|
|
|
|
|
if (pbi->num_fragments > (1 << EIGHT_PARTITION) + 1)
|
2011-05-02 15:30:51 +02:00
|
|
|
{
|
2011-06-13 16:42:27 +02:00
|
|
|
pbi->common.error.error_code = VPX_CODEC_UNSUP_BITSTREAM;
|
|
|
|
|
pbi->common.error.setjmp = 0;
|
2011-09-29 09:17:09 +02:00
|
|
|
pbi->num_fragments = 0;
|
2011-06-13 16:42:27 +02:00
|
|
|
return -1;
|
2011-05-02 15:30:51 +02:00
|
|
|
}
|
2011-06-13 16:42:27 +02:00
|
|
|
return 0;
|
2010-12-16 16:46:31 +01:00
|
|
|
}
|
2011-09-29 09:17:09 +02:00
|
|
|
|
|
|
|
|
if (!pbi->input_fragments)
|
2011-06-13 16:42:27 +02:00
|
|
|
{
|
2011-09-29 09:17:09 +02:00
|
|
|
pbi->fragments[0] = source;
|
|
|
|
|
pbi->fragment_sizes[0] = size;
|
|
|
|
|
pbi->num_fragments = 1;
|
|
|
|
|
}
|
|
|
|
|
assert(pbi->common.multi_token_partition <= EIGHT_PARTITION);
|
|
|
|
|
if (pbi->num_fragments == 0)
|
|
|
|
|
{
|
|
|
|
|
pbi->num_fragments = 1;
|
|
|
|
|
pbi->fragments[0] = NULL;
|
|
|
|
|
pbi->fragment_sizes[0] = 0;
|
|
|
|
|
}
|
2010-12-16 16:46:31 +01:00
|
|
|
|
2011-11-18 15:44:17 +01:00
|
|
|
if (!pbi->ec_active &&
|
|
|
|
|
pbi->num_fragments <= 1 && pbi->fragment_sizes[0] == 0)
|
2011-09-29 09:17:09 +02:00
|
|
|
{
|
|
|
|
|
/* If error concealment is disabled we won't signal missing frames
|
|
|
|
|
* to the decoder.
|
|
|
|
|
*/
|
2011-11-18 15:44:17 +01:00
|
|
|
if (cm->fb_idx_ref_cnt[cm->lst_fb_idx] > 1)
|
2011-06-13 16:42:27 +02:00
|
|
|
{
|
2011-11-18 15:44:17 +01:00
|
|
|
/* The last reference shares buffer with another reference
|
|
|
|
|
* buffer. Move it to its own buffer before setting it as
|
|
|
|
|
* corrupt, otherwise we will make multiple buffers corrupt.
|
|
|
|
|
*/
|
|
|
|
|
const int prev_idx = cm->lst_fb_idx;
|
|
|
|
|
cm->fb_idx_ref_cnt[prev_idx]--;
|
|
|
|
|
cm->lst_fb_idx = get_free_fb(cm);
|
2012-04-19 14:55:03 +02:00
|
|
|
vp8_yv12_copy_frame(&cm->yv12_fb[prev_idx],
|
2011-11-18 15:44:17 +01:00
|
|
|
&cm->yv12_fb[cm->lst_fb_idx]);
|
|
|
|
|
}
|
|
|
|
|
/* This is used to signal that we are missing frames.
|
|
|
|
|
* We do not know if the missing frame(s) was supposed to update
|
|
|
|
|
* any of the reference buffers, but we act conservative and
|
|
|
|
|
* mark only the last buffer as corrupted.
|
|
|
|
|
*/
|
|
|
|
|
cm->yv12_fb[cm->lst_fb_idx].corrupted = 1;
|
2011-06-13 16:42:27 +02:00
|
|
|
|
2011-11-18 15:44:17 +01:00
|
|
|
/* Signal that we have no frame to show. */
|
|
|
|
|
cm->show_frame = 0;
|
2011-08-08 10:56:20 +02:00
|
|
|
|
2011-11-18 15:44:17 +01:00
|
|
|
pbi->num_fragments = 0;
|
|
|
|
|
|
|
|
|
|
/* Nothing more to do. */
|
|
|
|
|
return 0;
|
2011-09-29 09:17:09 +02:00
|
|
|
}
|
2010-12-16 16:46:31 +01:00
|
|
|
|
2012-01-20 00:18:31 +01:00
|
|
|
#if HAVE_NEON
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#if CONFIG_RUNTIME_CPU_DETECT
|
2012-01-13 01:55:44 +01:00
|
|
|
if (cm->cpu_caps & HAS_NEON)
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#endif
|
2011-09-29 09:17:09 +02:00
|
|
|
{
|
|
|
|
|
vp8_push_neon(dx_store_reg);
|
|
|
|
|
}
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#endif
|
|
|
|
|
|
2011-09-29 09:17:09 +02:00
|
|
|
cm->new_fb_idx = get_free_fb (cm);
|
2010-10-20 00:40:46 +02:00
|
|
|
|
2011-09-29 09:17:09 +02:00
|
|
|
if (setjmp(pbi->common.error.jmp))
|
|
|
|
|
{
|
2012-01-20 00:18:31 +01:00
|
|
|
#if HAVE_NEON
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#if CONFIG_RUNTIME_CPU_DETECT
|
2012-01-13 01:55:44 +01:00
|
|
|
if (cm->cpu_caps & HAS_NEON)
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#endif
|
2011-09-29 09:17:09 +02:00
|
|
|
{
|
|
|
|
|
vp8_pop_neon(dx_store_reg);
|
|
|
|
|
}
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#endif
|
2011-09-29 09:17:09 +02:00
|
|
|
pbi->common.error.setjmp = 0;
|
2011-08-08 10:56:20 +02:00
|
|
|
|
2011-09-29 09:17:09 +02:00
|
|
|
pbi->num_fragments = 0;
|
2010-05-18 17:58:33 +02:00
|
|
|
|
2011-09-29 09:17:09 +02:00
|
|
|
/* We do not know if the missing frame(s) was supposed to update
|
|
|
|
|
* any of the reference buffers, but we act conservative and
|
|
|
|
|
* mark only the last buffer as corrupted.
|
|
|
|
|
*/
|
|
|
|
|
cm->yv12_fb[cm->lst_fb_idx].corrupted = 1;
|
2010-05-18 17:58:33 +02:00
|
|
|
|
2011-09-29 09:17:09 +02:00
|
|
|
if (cm->fb_idx_ref_cnt[cm->new_fb_idx] > 0)
|
|
|
|
|
cm->fb_idx_ref_cnt[cm->new_fb_idx]--;
|
|
|
|
|
return -1;
|
2011-06-13 16:42:27 +02:00
|
|
|
}
|
2010-05-18 17:58:33 +02:00
|
|
|
|
2011-09-29 09:17:09 +02:00
|
|
|
pbi->common.error.setjmp = 1;
|
|
|
|
|
|
2010-05-18 17:58:33 +02:00
|
|
|
retcode = vp8_decode_frame(pbi);
|
|
|
|
|
|
|
|
|
|
if (retcode < 0)
|
|
|
|
|
{
|
2012-01-20 00:18:31 +01:00
|
|
|
#if HAVE_NEON
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#if CONFIG_RUNTIME_CPU_DETECT
|
2012-01-13 01:55:44 +01:00
|
|
|
if (cm->cpu_caps & HAS_NEON)
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#endif
|
|
|
|
|
{
|
|
|
|
|
vp8_pop_neon(dx_store_reg);
|
|
|
|
|
}
|
2010-05-18 17:58:33 +02:00
|
|
|
#endif
|
|
|
|
|
pbi->common.error.error_code = VPX_CODEC_ERROR;
|
|
|
|
|
pbi->common.error.setjmp = 0;
|
2011-09-29 09:17:09 +02:00
|
|
|
pbi->num_fragments = 0;
|
2010-10-20 00:40:46 +02:00
|
|
|
if (cm->fb_idx_ref_cnt[cm->new_fb_idx] > 0)
|
|
|
|
|
cm->fb_idx_ref_cnt[cm->new_fb_idx]--;
|
2010-05-18 17:58:33 +02:00
|
|
|
return retcode;
|
|
|
|
|
}
|
|
|
|
|
|
2011-02-05 06:29:25 +01:00
|
|
|
#if CONFIG_MULTITHREAD
|
2010-09-16 20:08:52 +02:00
|
|
|
if (pbi->b_multithreaded_rd && cm->multi_token_partition != ONE_PARTITION)
|
2010-05-18 17:58:33 +02:00
|
|
|
{
|
2010-09-16 20:08:52 +02:00
|
|
|
if (swap_frame_buffers (cm))
|
|
|
|
|
{
|
2012-01-20 00:18:31 +01:00
|
|
|
#if HAVE_NEON
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#if CONFIG_RUNTIME_CPU_DETECT
|
2012-01-13 01:55:44 +01:00
|
|
|
if (cm->cpu_caps & HAS_NEON)
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#endif
|
|
|
|
|
{
|
|
|
|
|
vp8_pop_neon(dx_store_reg);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2010-09-16 20:08:52 +02:00
|
|
|
pbi->common.error.error_code = VPX_CODEC_ERROR;
|
|
|
|
|
pbi->common.error.setjmp = 0;
|
2011-09-29 09:17:09 +02:00
|
|
|
pbi->num_fragments = 0;
|
2010-09-16 20:08:52 +02:00
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
} else
|
2011-02-05 06:29:25 +01:00
|
|
|
#endif
|
2010-05-18 17:58:33 +02:00
|
|
|
{
|
2010-09-16 20:08:52 +02:00
|
|
|
if (swap_frame_buffers (cm))
|
|
|
|
|
{
|
2012-01-20 00:18:31 +01:00
|
|
|
#if HAVE_NEON
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#if CONFIG_RUNTIME_CPU_DETECT
|
2012-01-13 01:55:44 +01:00
|
|
|
if (cm->cpu_caps & HAS_NEON)
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#endif
|
|
|
|
|
{
|
|
|
|
|
vp8_pop_neon(dx_store_reg);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2010-09-16 20:08:52 +02:00
|
|
|
pbi->common.error.error_code = VPX_CODEC_ERROR;
|
|
|
|
|
pbi->common.error.setjmp = 0;
|
2011-09-29 09:17:09 +02:00
|
|
|
pbi->num_fragments = 0;
|
2010-09-16 20:08:52 +02:00
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
2011-07-20 21:53:42 +02:00
|
|
|
if(cm->filter_level)
|
2010-09-16 20:08:52 +02:00
|
|
|
{
|
2010-10-28 01:04:02 +02:00
|
|
|
/* Apply the loop filter if appropriate. */
|
2011-07-20 21:53:42 +02:00
|
|
|
vp8_loop_filter_frame(cm, &pbi->mb);
|
2010-09-16 20:08:52 +02:00
|
|
|
}
|
2012-04-19 14:55:03 +02:00
|
|
|
vp8_yv12_extend_frame_borders(cm->frame_to_show);
|
2010-06-30 16:22:40 +02:00
|
|
|
}
|
2010-05-18 17:58:33 +02:00
|
|
|
|
|
|
|
|
|
|
|
|
|
vp8_clear_system_state();
|
|
|
|
|
|
2011-05-02 15:30:51 +02:00
|
|
|
#if CONFIG_ERROR_CONCEALMENT
|
|
|
|
|
/* swap the mode infos to storage for future error concealment */
|
|
|
|
|
if (pbi->ec_enabled && pbi->common.prev_mi)
|
|
|
|
|
{
|
2011-09-29 09:17:09 +02:00
|
|
|
MODE_INFO* tmp = pbi->common.prev_mi;
|
2011-05-02 15:30:51 +02:00
|
|
|
int row, col;
|
|
|
|
|
pbi->common.prev_mi = pbi->common.mi;
|
|
|
|
|
pbi->common.mi = tmp;
|
|
|
|
|
|
|
|
|
|
/* Propagate the segment_ids to the next frame */
|
|
|
|
|
for (row = 0; row < pbi->common.mb_rows; ++row)
|
|
|
|
|
{
|
|
|
|
|
for (col = 0; col < pbi->common.mb_cols; ++col)
|
|
|
|
|
{
|
|
|
|
|
const int i = row*pbi->common.mode_info_stride + col;
|
|
|
|
|
pbi->common.mi[i].mbmi.segment_id =
|
|
|
|
|
pbi->common.prev_mi[i].mbmi.segment_id;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2010-10-28 01:04:02 +02:00
|
|
|
/*vp8_print_modes_and_motion_vectors( cm->mi, cm->mb_rows,cm->mb_cols, cm->current_video_frame);*/
|
2010-05-18 17:58:33 +02:00
|
|
|
|
|
|
|
|
if (cm->show_frame)
|
|
|
|
|
cm->current_video_frame++;
|
|
|
|
|
|
|
|
|
|
pbi->ready_for_new_data = 0;
|
|
|
|
|
pbi->last_time_stamp = time_stamp;
|
2011-09-29 09:17:09 +02:00
|
|
|
pbi->num_fragments = 0;
|
2010-05-18 17:58:33 +02:00
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
{
|
|
|
|
|
int i;
|
2011-07-26 03:44:59 +02:00
|
|
|
int64_t earliest_time = pbi->dr[0].time_stamp;
|
|
|
|
|
int64_t latest_time = pbi->dr[0].time_stamp;
|
|
|
|
|
int64_t time_diff = 0;
|
2010-05-18 17:58:33 +02:00
|
|
|
int bytes = 0;
|
|
|
|
|
|
|
|
|
|
pbi->dr[pbi->common.current_video_frame&0xf].size = pbi->bc.pos + pbi->bc2.pos + 4;;
|
|
|
|
|
pbi->dr[pbi->common.current_video_frame&0xf].time_stamp = time_stamp;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
bytes += pbi->dr[i].size;
|
|
|
|
|
|
|
|
|
|
if (pbi->dr[i].time_stamp < earliest_time)
|
|
|
|
|
earliest_time = pbi->dr[i].time_stamp;
|
|
|
|
|
|
|
|
|
|
if (pbi->dr[i].time_stamp > latest_time)
|
|
|
|
|
latest_time = pbi->dr[i].time_stamp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
time_diff = latest_time - earliest_time;
|
|
|
|
|
|
|
|
|
|
if (time_diff > 0)
|
|
|
|
|
{
|
|
|
|
|
pbi->common.bitrate = 80000.00 * bytes / time_diff ;
|
|
|
|
|
pbi->common.framerate = 160000000.00 / time_diff ;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-01-20 00:18:31 +01:00
|
|
|
#if HAVE_NEON
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#if CONFIG_RUNTIME_CPU_DETECT
|
2012-01-13 01:55:44 +01:00
|
|
|
if (cm->cpu_caps & HAS_NEON)
|
Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
|
|
|
#endif
|
|
|
|
|
{
|
|
|
|
|
vp8_pop_neon(dx_store_reg);
|
|
|
|
|
}
|
2010-05-18 17:58:33 +02:00
|
|
|
#endif
|
|
|
|
|
pbi->common.error.setjmp = 0;
|
|
|
|
|
return retcode;
|
|
|
|
|
}
|
2011-12-21 01:54:54 +01:00
|
|
|
int vp8dx_get_raw_frame(VP8D_COMP *pbi, YV12_BUFFER_CONFIG *sd, int64_t *time_stamp, int64_t *time_end_stamp, vp8_ppflags_t *flags)
|
2010-05-18 17:58:33 +02:00
|
|
|
{
|
|
|
|
|
int ret = -1;
|
|
|
|
|
|
|
|
|
|
if (pbi->ready_for_new_data == 1)
|
|
|
|
|
return ret;
|
|
|
|
|
|
2010-10-28 01:04:02 +02:00
|
|
|
/* ie no raw frame to show!!! */
|
2010-05-18 17:58:33 +02:00
|
|
|
if (pbi->common.show_frame == 0)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
pbi->ready_for_new_data = 1;
|
|
|
|
|
*time_stamp = pbi->last_time_stamp;
|
|
|
|
|
*time_end_stamp = 0;
|
|
|
|
|
|
|
|
|
|
sd->clrtype = pbi->common.clr_type;
|
|
|
|
|
#if CONFIG_POSTPROC
|
2010-11-05 00:03:36 +01:00
|
|
|
ret = vp8_post_proc_frame(&pbi->common, sd, flags);
|
2010-05-18 17:58:33 +02:00
|
|
|
#else
|
|
|
|
|
|
|
|
|
|
if (pbi->common.frame_to_show)
|
|
|
|
|
{
|
|
|
|
|
*sd = *pbi->common.frame_to_show;
|
|
|
|
|
sd->y_width = pbi->common.Width;
|
|
|
|
|
sd->y_height = pbi->common.Height;
|
|
|
|
|
sd->uv_height = pbi->common.Height / 2;
|
|
|
|
|
ret = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
ret = -1;
|
|
|
|
|
}
|
|
|
|
|
|
2010-10-28 01:04:02 +02:00
|
|
|
#endif /*!CONFIG_POSTPROC*/
|
2010-05-18 17:58:33 +02:00
|
|
|
vp8_clear_system_state();
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
2012-01-27 19:13:20 +01:00
|
|
|
|
|
|
|
|
|
|
|
|
|
/* This function as written isn't decoder specific, but the encoder has
|
|
|
|
|
* much faster ways of computing this, so it's ok for it to live in a
|
|
|
|
|
* decode specific file.
|
|
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*/
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int vp8dx_references_buffer( VP8_COMMON *oci, int ref_frame )
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{
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|
const MODE_INFO *mi = oci->mi;
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int mb_row, mb_col;
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for (mb_row = 0; mb_row < oci->mb_rows; mb_row++)
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{
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for (mb_col = 0; mb_col < oci->mb_cols; mb_col++,mi++)
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{
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if( mi->mbmi.ref_frame == ref_frame)
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return 1;
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}
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mi++;
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}
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return 0;
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}
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