Rename amd64 modules to x86_64 and update RC4 implementation.
This commit is contained in:
Andy Polyakov
parent
4b45051902
commit
5f1841cdca
@ -118,7 +118,7 @@ my $x86_elf_asm="x86cpuid-elf.o:bn86-elf.o co86-elf.o:dx86-elf.o yx86-elf.o:ax86
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my $x86_coff_asm="x86cpuid-cof.o:bn86-cof.o co86-cof.o:dx86-cof.o yx86-cof.o:ax86-cof.o:bx86-cof.o:mx86-cof.o:sx86-cof.o s512sse2-cof.o:cx86-cof.o:rx86-cof.o:rm86-cof.o:r586-cof.o";
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my $x86_out_asm="x86cpuid-out.o:bn86-out.o co86-out.o:dx86-out.o yx86-out.o:ax86-out.o:bx86-out.o:mx86-out.o:sx86-out.o s512sse2-out.o:cx86-out.o:rx86-out.o:rm86-out.o:r586-out.o";
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my $x86_64_asm="amd64cpuid.o:x86_64-gcc.o:::::::rc4-amd64.o::";
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my $x86_64_asm="x86_64cpuid.o:x86_64-gcc.o:::::::rc4-x86_64.o::";
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my $ia64_asm=":ia64.o::aes_core.o aes_cbc.o aes-ia64.o:::sha1-ia64.o sha256-ia64.o sha512-ia64.o::rc4-ia64.o::";
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my $no_asm="::::::::::";
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12
TABLE
12
TABLE
@ -278,7 +278,7 @@ $thread_cflag = -pthread -D_THREAD_SAFE -D_REENTRANT
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$sys_id =
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$lflags =
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$bn_ops = SIXTY_FOUR_BIT_LONG RC4_CHUNK DES_INT DES_UNROLL
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$cpuid_obj = amd64cpuid.o
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$cpuid_obj = x86_64cpuid.o
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$bn_obj = x86_64-gcc.o
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$des_obj =
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$aes_obj =
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@ -286,7 +286,7 @@ $bf_obj =
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$md5_obj =
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$sha1_obj =
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$cast_obj =
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$rc4_obj = rc4-amd64.o
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$rc4_obj = rc4-x86_64.o
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$rmd160_obj =
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$rc5_obj =
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$dso_scheme = dlfcn
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@ -3086,7 +3086,7 @@ $thread_cflag = -D_REENTRANT
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$sys_id =
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$lflags = -ldl
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$bn_ops = SIXTY_FOUR_BIT_LONG RC4_CHUNK BF_PTR2 DES_INT DES_UNROLL
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$cpuid_obj = amd64cpuid.o
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$cpuid_obj = x86_64cpuid.o
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$bn_obj = x86_64-gcc.o
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$des_obj =
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$aes_obj =
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@ -3094,7 +3094,7 @@ $bf_obj =
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$md5_obj =
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$sha1_obj =
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$cast_obj =
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$rc4_obj = rc4-amd64.o
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$rc4_obj = rc4-x86_64.o
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$rmd160_obj =
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$rc5_obj =
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$dso_scheme = dlfcn
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@ -3896,7 +3896,7 @@ $thread_cflag = -D_REENTRANT
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$sys_id =
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$lflags = -lsocket -lnsl -ldl
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$bn_ops = SIXTY_FOUR_BIT_LONG RC4_CHUNK BF_PTR2 DES_INT DES_UNROLL
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$cpuid_obj = amd64cpuid.o
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$cpuid_obj = x86_64cpuid.o
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$bn_obj = x86_64-gcc.o
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$des_obj =
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$aes_obj =
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@ -3904,7 +3904,7 @@ $bf_obj =
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$md5_obj =
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$sha1_obj =
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$cast_obj =
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$rc4_obj = rc4-amd64.o
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$rc4_obj = rc4-x86_64.o
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$rmd160_obj =
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$rc5_obj =
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$dso_scheme = dlfcn
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@ -70,8 +70,8 @@ x86cpuid-cof.s: x86cpuid.pl perlasm/x86asm.pl
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x86cpuid-out.s: x86cpuid.pl perlasm/x86asm.pl
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$(PERL) x86cpuid.pl a.out $(CFLAGS) $(PROCESSOR) > $@
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amd64cpuid.s: amd64cpuid.pl
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$(PERL) amd64cpuid.pl $@
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x86_64cpuid.s: x86_64cpuid.pl
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$(PERL) x86_64cpuid.pl $@
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ia64cpuid.s: ia64cpuid.S
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$(CC) $(CFLAGS) -E ia64cpuid.S > $@
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@ -58,7 +58,7 @@ rx86-cof.s: asm/rc4-586.pl ../perlasm/x86asm.pl
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rx86-out.s: asm/rc4-586.pl ../perlasm/x86asm.pl
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(cd asm; $(PERL) rc4-586.pl a.out $(CFLAGS) > ../$@)
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rc4-amd64.s: asm/rc4-amd64.pl; $(PERL) asm/rc4-amd64.pl $@
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rc4-x86_64.s: asm/rc4-x86_64.pl; $(PERL) asm/rc4-x86_64.pl $@
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rc4-ia64.s: asm/rc4-ia64.S
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$(CC) $(CFLAGS) -E asm/rc4-ia64.S > $@
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@ -1,160 +0,0 @@
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#!/usr/bin/env perl
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#
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# ====================================================================
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# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
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# project. Rights for redistribution and usage in source and binary
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# forms are granted according to the OpenSSL license.
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# ====================================================================
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#
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# 2.22x RC4 tune-up:-) It should be noted though that my hand [as in
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# "hand-coded assembler"] doesn't stand for the whole improvement
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# coefficient. It turned out that eliminating RC4_CHAR from config
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# line results in ~40% improvement (yes, even for C implementation).
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# Presumably it has everything to do with AMD cache architecture and
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# RAW or whatever penalties. Once again! The module *requires* config
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# line *without* RC4_CHAR! As for coding "secret," I bet on partial
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# register arithmetics. For example instead of 'inc %r8; and $255,%r8'
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# I simply 'inc %r8b'. Even though optimization manual discourages
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# to operate on partial registers, it turned out to be the best bet.
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# At least for AMD... How IA32E would perform remains to be seen...
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# As was shown by Marc Bevand reordering of couple of load operations
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# results in even higher performance gain of 3.3x:-) At least on
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# Opteron... For reference, 1x in this case is RC4_CHAR C-code
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# compiled with gcc 3.3.2, which performs at ~54MBps per 1GHz clock.
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# Latter means that if you want to *estimate* what to expect from
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# *your* CPU, then multiply 54 by 3.3 and clock frequency in GHz.
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# Intel P4 EM64T core was found to run the AMD64 code really slow...
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# The only way to achieve comparable performance on P4 is to keep
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# RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to
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# compose blended code, which would perform even within 30% marginal
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# on either AMD and Intel platforms, I implement both cases. See
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# rc4_skey.c for further details... This applies to 0.9.8 and later.
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# In 0.9.7 context RC4_CHAR codepath is never engaged and ~70 bytes
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# of code remain redundant.
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$output=shift;
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open STDOUT,"| $^X ../perlasm/x86_64-xlate.pl $output";
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$dat="%rdi"; # arg1
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$len="%rsi"; # arg2
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$inp="%rdx"; # arg3
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$out="%rcx"; # arg4
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$XX="%r10";
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$TX="%r8";
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$YY="%r11";
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$TY="%r9";
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$code=<<___;
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.text
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.globl RC4
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.type RC4,\@function,4
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.align 16
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RC4: or $len,$len
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jne .Lentry
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ret
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.Lentry:
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add \$8,$dat
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movl -8($dat),$XX#d
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movl -4($dat),$YY#d
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cmpl \$-1,256($dat)
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je .LRC4_CHAR
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test \$-8,$len
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jz .Lloop1
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.align 16
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.Lloop8:
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inc $XX#b
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movl ($dat,$XX,4),$TX#d
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add $TX#b,$YY#b
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movl ($dat,$YY,4),$TY#d
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movl $TX#d,($dat,$YY,4)
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movl $TY#d,($dat,$XX,4)
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add $TX#b,$TY#b
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inc $XX#b
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movl ($dat,$XX,4),$TX#d
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movb ($dat,$TY,4),%al
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___
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for ($i=1;$i<=6;$i++) {
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$code.=<<___;
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add $TX#b,$YY#b
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ror \$8,%rax
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movl ($dat,$YY,4),$TY#d
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movl $TX#d,($dat,$YY,4)
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movl $TY#d,($dat,$XX,4)
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add $TX#b,$TY#b
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inc $XX#b
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movl ($dat,$XX,4),$TX#d
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movb ($dat,$TY,4),%al
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___
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}
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$code.=<<___;
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add $TX#b,$YY#b
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ror \$8,%rax
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movl ($dat,$YY,4),$TY#d
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movl $TX#d,($dat,$YY,4)
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movl $TY#d,($dat,$XX,4)
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sub \$8,$len
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add $TY#b,$TX#b
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movb ($dat,$TX,4),%al
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ror \$8,%rax
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add \$8,$inp
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add \$8,$out
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xor -8($inp),%rax
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mov %rax,-8($out)
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test \$-8,$len
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jnz .Lloop8
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cmp \$0,$len
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jne .Lloop1
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.Lexit:
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movl $XX#d,-8($dat)
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movl $YY#d,-4($dat)
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ret
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.align 16
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.Lloop1:
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movzb ($inp),%eax
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inc $XX#b
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movl ($dat,$XX,4),$TX#d
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add $TX#b,$YY#b
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movl ($dat,$YY,4),$TY#d
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movl $TX#d,($dat,$YY,4)
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movl $TY#d,($dat,$XX,4)
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add $TY#b,$TX#b
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movl ($dat,$TX,4),$TY#d
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xor $TY,%rax
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inc $inp
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movb %al,($out)
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inc $out
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dec $len
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jnz .Lloop1
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jmp .Lexit
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.align 16
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.LRC4_CHAR:
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add \$1,$XX#b
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movzb ($dat,$XX),$TX#d
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add $TX#b,$YY#b
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movzb ($dat,$YY),$TY#d
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movb $TX#b,($dat,$YY)
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movb $TY#b,($dat,$XX)
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add $TX#b,$TY#b
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movzb ($dat,$TY),$TY#d
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xorb ($inp),$TY#b
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movb $TY#b,($out)
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lea 1($inp),$inp
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lea 1($out),$out
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sub \$1,$len
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jnz .LRC4_CHAR
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jmp .Lexit
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.size RC4,.-RC4
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___
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$code =~ s/#([bwd])/$1/gm;
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print $code;
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close STDOUT;
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238
crypto/rc4/asm/rc4-x86_64.pl
Executable file
238
crypto/rc4/asm/rc4-x86_64.pl
Executable file
@ -0,0 +1,238 @@
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#!/usr/bin/env perl
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#
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# ====================================================================
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# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
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# project. Rights for redistribution and usage in source and binary
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# forms are granted according to the OpenSSL license.
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# ====================================================================
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#
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# 2.22x RC4 tune-up:-) It should be noted though that my hand [as in
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# "hand-coded assembler"] doesn't stand for the whole improvement
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# coefficient. It turned out that eliminating RC4_CHAR from config
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# line results in ~40% improvement (yes, even for C implementation).
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# Presumably it has everything to do with AMD cache architecture and
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# RAW or whatever penalties. Once again! The module *requires* config
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# line *without* RC4_CHAR! As for coding "secret," I bet on partial
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# register arithmetics. For example instead of 'inc %r8; and $255,%r8'
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# I simply 'inc %r8b'. Even though optimization manual discourages
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# to operate on partial registers, it turned out to be the best bet.
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# At least for AMD... How IA32E would perform remains to be seen...
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# As was shown by Marc Bevand reordering of couple of load operations
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# results in even higher performance gain of 3.3x:-) At least on
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# Opteron... For reference, 1x in this case is RC4_CHAR C-code
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# compiled with gcc 3.3.2, which performs at ~54MBps per 1GHz clock.
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# Latter means that if you want to *estimate* what to expect from
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# *your* Opteron, then multiply 54 by 3.3 and clock frequency in GHz.
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# Intel P4 EM64T core was found to run the AMD64 code really slow...
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# The only way to achieve comparable performance on P4 was to keep
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# RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to
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# compose blended code, which would perform even within 30% marginal
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# on either AMD and Intel platforms, I implement both cases. See
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# rc4_skey.c for further details...
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# P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing
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# those with add/sub results in 50% performance improvement of folded
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# loop...
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# As was shown by Zou Nanhai loop unrolling can improve Intel EM64T
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# performance by >30% [unlike P4 32-bit case that is]. But this is
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# provided that loads are reordered even more aggressively! Both code
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# pathes, AMD64 and EM64T, reorder loads in essentially same manner
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# as my IA-64 implementation. On Opteron this resulted in modest 5%
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# improvement [I had to test it], while final Intel P4 performance
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# achieves respectful 432MBps on 2.8GHz processor now. For reference.
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# If executed on Xeon, current RC4_CHAR code-path is 2.7x faster than
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# RC4_INT code-path. While if executed on Opteron, it's is only 25%
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# slower than the latter...
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$output=shift;
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open STDOUT,"| $^X ../perlasm/x86_64-xlate.pl $output";
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$dat="%rdi"; # arg1
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$len="%rsi"; # arg2
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$inp="%rdx"; # arg3
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$out="%rcx"; # arg4
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@XX=("%r8","%r10");
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@TX=("%r9","%r11");
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$YY="%r12";
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$TY="%r13";
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$code=<<___;
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.text
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.globl RC4
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.type RC4,\@function,4
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.align 16
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RC4: or $len,$len
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jne .Lentry
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ret
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.Lentry:
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push %r12
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push %r13
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add \$8,$dat
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movl -8($dat),$XX[0]#d
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movl -4($dat),$YY#d
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cmpl \$-1,256($dat)
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je .LRC4_CHAR
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inc $XX[0]#b
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movl ($dat,$XX[0],4),$TX[0]#d
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test \$-8,$len
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jz .Lloop1
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jmp .Lloop8
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.align 16
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.Lloop8:
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___
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for ($i=0;$i<8;$i++) {
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$code.=<<___;
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add $TX[0]#b,$YY#b
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mov $XX[0],$XX[1]
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movl ($dat,$YY,4),$TY#d
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ror \$8,%rax # ror is redundant when $i=0
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inc $XX[1]#b
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movl ($dat,$XX[1],4),$TX[1]#d
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cmp $XX[1],$YY
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movl $TX[0]#d,($dat,$YY,4)
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cmove $TX[0],$TX[1]
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movl $TY#d,($dat,$XX[0],4)
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add $TX[0]#b,$TY#b
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movb ($dat,$TY,4),%al
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___
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push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
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}
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$code.=<<___;
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ror \$8,%rax
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sub \$8,$len
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xor ($inp),%rax
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add \$8,$inp
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mov %rax,($out)
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add \$8,$out
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test \$-8,$len
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jnz .Lloop8
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cmp \$0,$len
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jne .Lloop1
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___
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$code.=<<___;
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.Lexit:
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sub \$1,$XX[0]#b
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movl $XX[0]#d,-8($dat)
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movl $YY#d,-4($dat)
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pop %r13
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pop %r12
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ret
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.align 16
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.Lloop1:
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add $TX[0]#b,$YY#b
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movl ($dat,$YY,4),$TY#d
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movl $TX[0]#d,($dat,$YY,4)
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movl $TY#d,($dat,$XX[0],4)
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add $TY#b,$TX[0]#b
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inc $XX[0]#b
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movl ($dat,$TX[0],4),$TY#d
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movl ($dat,$XX[0],4),$TX[0]#d
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xorb ($inp),$TY#b
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inc $inp
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movb $TY#b,($out)
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inc $out
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dec $len
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jnz .Lloop1
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jmp .Lexit
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.align 16
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.LRC4_CHAR:
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add \$1,$XX[0]#b
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movzb ($dat,$XX[0]),$TX[0]#d
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test \$-8,$len
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jz .Lcloop1
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push %rbx
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jmp .Lcloop8
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.align 16
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.Lcloop8:
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mov ($inp),%eax
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mov 4($inp),%ebx
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___
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# unroll 2x4-wise, because 64-bit rotates kill Intel P4...
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for ($i=0;$i<4;$i++) {
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$code.=<<___;
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add $TX[0]#b,$YY#b
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lea 1($XX[0]),$XX[1]
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movzb ($dat,$YY),$TY#d
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movzb $XX[1]#b,$XX[1]#d
|
||||
movzb ($dat,$XX[1]),$TX[1]#d
|
||||
movb $TX[0]#b,($dat,$YY)
|
||||
cmp $XX[1],$YY
|
||||
movb $TY#b,($dat,$XX[0])
|
||||
jne .Lcmov$i # Intel cmov is sloooow...
|
||||
mov $TX[0],$TX[1]
|
||||
.Lcmov$i:
|
||||
add $TX[0]#b,$TY#b
|
||||
xor ($dat,$TY),%al
|
||||
ror \$8,%eax
|
||||
___
|
||||
push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
|
||||
}
|
||||
for ($i=4;$i<8;$i++) {
|
||||
$code.=<<___;
|
||||
add $TX[0]#b,$YY#b
|
||||
lea 1($XX[0]),$XX[1]
|
||||
movzb ($dat,$YY),$TY#d
|
||||
movzb $XX[1]#b,$XX[1]
|
||||
movzb ($dat,$XX[1]),$TX[1]#d
|
||||
movb $TX[0]#b,($dat,$YY)
|
||||
cmp $XX[1],$YY
|
||||
movb $TY#b,($dat,$XX[0])
|
||||
jne .Lcmov$i # Intel cmov is sloooow...
|
||||
mov $TX[0],$TX[1]
|
||||
.Lcmov$i:
|
||||
add $TX[0]#b,$TY#b
|
||||
xor ($dat,$TY),%bl
|
||||
ror \$8,%ebx
|
||||
___
|
||||
push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
|
||||
}
|
||||
$code.=<<___;
|
||||
lea -8($len),$len
|
||||
mov %eax,($out)
|
||||
lea 8($inp),$inp
|
||||
mov %ebx,4($out)
|
||||
lea 8($out),$out
|
||||
|
||||
test \$-8,$len
|
||||
jnz .Lcloop8
|
||||
pop %rbx
|
||||
cmp \$0,$len
|
||||
jne .Lcloop1
|
||||
jmp .Lexit
|
||||
___
|
||||
$code.=<<___;
|
||||
.align 16
|
||||
.Lcloop1:
|
||||
add $TX[0]#b,$YY#b
|
||||
movzb ($dat,$YY),$TY#d
|
||||
movb $TX[0]#b,($dat,$YY)
|
||||
movb $TY#b,($dat,$XX[0])
|
||||
add $TX[0]#b,$TY#b
|
||||
add \$1,$XX[0]#b
|
||||
movzb ($dat,$TY),$TY#d
|
||||
movzb ($dat,$XX[0]),$TX[0]#d
|
||||
xorb ($inp),$TY#b
|
||||
lea 1($inp),$inp
|
||||
movb $TY#b,($out)
|
||||
lea 1($out),$out
|
||||
sub \$1,$len
|
||||
jnz .Lcloop1
|
||||
jmp .Lexit
|
||||
.size RC4,.-RC4
|
||||
___
|
||||
|
||||
$code =~ s/#([bwd])/$1/gm;
|
||||
|
||||
print $code;
|
||||
|
||||
close STDOUT;
|
||||
Loading…
Reference in New Issue
Block a user