Sync with HEAD. Up to >20% overall performance improvement.
This commit is contained in:
Andy Polyakov
parent
a77b16abd4
commit
370358dfb4
@ -1,6 +1,6 @@
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.explicit
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.text
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.ident "ia64.S, Version 2.0"
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.ident "ia64.S, Version 2.1"
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.ident "IA-64 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
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//
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@ -35,7 +35,7 @@
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// What does it mean? You might ratiocinate that the original code
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// should run just faster... Because sum of latencies is smaller...
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// Wrong! Note that getf latency increased. This means that if a loop is
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// scheduled for lower latency (and they are), then it will suffer from
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// scheduled for lower latency (as they were), then it will suffer from
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// stall condition and the code will therefore turn anti-scalable, e.g.
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// original bn_mul_words spun at 5*n or 2.5 times slower than expected
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// on Itanium2! What to do? Reschedule loops for Itanium2? But then
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@ -145,6 +145,12 @@
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// -Drum=nop.m in command line.
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//
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#if defined(_HPUX_SOURCE) && !defined(_LP64)
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#define ADDP addp4
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#else
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#define ADDP add
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#endif
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#if 1
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//
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// bn_[add|sub]_words routines.
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@ -178,27 +184,12 @@ bn_add_words:
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brp.loop.imp .L_bn_add_words_ctop,.L_bn_add_words_cend-16
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}
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.body
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{ .mib;
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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addp4 r14=0,r32 // rp
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#else
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mov r14=r32 // rp
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#endif
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{ .mib; ADDP r14=0,r32 // rp
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mov r9=pr };;
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{ .mii;
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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addp4 r15=0,r33 // ap
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#else
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mov r15=r33 // ap
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#endif
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{ .mii; ADDP r15=0,r33 // ap
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mov ar.lc=r10
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mov ar.ec=6 }
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{ .mib;
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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addp4 r16=0,r34 // bp
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#else
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mov r16=r34 // bp
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#endif
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{ .mib; ADDP r16=0,r34 // bp
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mov pr.rot=1<<16 };;
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.L_bn_add_words_ctop:
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@ -246,27 +237,12 @@ bn_sub_words:
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brp.loop.imp .L_bn_sub_words_ctop,.L_bn_sub_words_cend-16
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}
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.body
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{ .mib;
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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addp4 r14=0,r32 // rp
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#else
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mov r14=r32 // rp
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#endif
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{ .mib; ADDP r14=0,r32 // rp
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mov r9=pr };;
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{ .mii;
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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addp4 r15=0,r33 // ap
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#else
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mov r15=r33 // ap
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#endif
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{ .mii; ADDP r15=0,r33 // ap
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mov ar.lc=r10
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mov ar.ec=6 }
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{ .mib;
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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addp4 r16=0,r34 // bp
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#else
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mov r16=r34 // bp
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#endif
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{ .mib; ADDP r16=0,r34 // bp
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mov pr.rot=1<<16 };;
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.L_bn_sub_words_ctop:
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@ -332,16 +308,10 @@ bn_mul_words:
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#ifndef XMA_TEMPTATION
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{ .mii;
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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addp4 r14=0,r32 // rp
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addp4 r15=0,r33 // ap
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#else
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mov r14=r32 // rp
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mov r15=r33 // ap
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#endif
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{ .mmi; ADDP r14=0,r32 // rp
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ADDP r15=0,r33 // ap
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mov ar.lc=r10 }
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{ .mii; mov r40=0 // serves as r35 at first (p27)
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{ .mmi; mov r40=0 // serves as r35 at first (p27)
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mov ar.ec=13 };;
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// This loop spins in 2*(n+12) ticks. It's scheduled for data in Itanium
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@ -424,89 +394,64 @@ bn_mul_words:
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.global bn_mul_add_words#
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.proc bn_mul_add_words#
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.align 64
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//.skip 0 // makes the loop split at 64-byte boundary
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.skip 48 // makes the loop body aligned at 64-byte boundary
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bn_mul_add_words:
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.prologue
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.fframe 0
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.save ar.pfs,r2
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{ .mii; alloc r2=ar.pfs,4,12,0,16
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cmp4.le p6,p0=r34,r0 };;
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{ .mfb; mov r8=r0 // return value
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.save ar.lc,r3
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.save pr,r9
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{ .mmi; alloc r2=ar.pfs,4,4,0,8
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cmp4.le p6,p0=r34,r0
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mov r3=ar.lc };;
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{ .mib; mov r8=r0 // return value
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sub r10=r34,r0,1
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(p6) br.ret.spnt.many b0 };;
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.save ar.lc,r3
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{ .mii; sub r10=r34,r0,1
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mov r3=ar.lc
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mov r9=pr };;
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.body
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{ .mib; setf.sig f8=r35 // w
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mov pr.rot=0x800001<<16
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// ------^----- serves as (p50) at first (p27)
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{ .mib; setf.sig f8=r35 // w
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mov r9=pr
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brp.loop.imp .L_bn_mul_add_words_ctop,.L_bn_mul_add_words_cend-16
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}
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{ .mii;
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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addp4 r14=0,r32 // rp
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addp4 r15=0,r33 // ap
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#else
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mov r14=r32 // rp
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mov r15=r33 // ap
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#endif
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{ .mmi; ADDP r14=0,r32 // rp
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ADDP r15=0,r33 // ap
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mov ar.lc=r10 }
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{ .mii; mov r40=0 // serves as r35 at first (p27)
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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addp4 r18=0,r32 // rp copy
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#else
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mov r18=r32 // rp copy
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#endif
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mov ar.ec=15 };;
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{ .mii; ADDP r16=0,r32 // rp copy
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mov pr.rot=0x2001<<16
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// ------^----- serves as (p40) at first (p27)
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mov ar.ec=11 };;
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// This loop spins in 3*(n+14) ticks on Itanium and should spin in
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// 2*(n+14) on "wider" IA-64 implementations (to be verified with new
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// µ-architecture manuals as they become available). As usual it's
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// possible to compress the epilogue, down to 10 in this case, at the
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// cost of scalability. Compressed (and therefore non-scalable) loop
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// running at 3*(n+11) would buy you ~10% on Itanium but take ~35%
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// from "wider" IA-64 so let it be scalable! Special attention was
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// paid for having the loop body split at 64-byte boundary. ld8 is
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// scheduled for L1 cache as the data is more than likely there.
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// Indeed, bn_mul_words has put it there a moment ago:-)
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// This loop spins in 3*(n+10) ticks on Itanium and in 2*(n+10) on
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// Itanium 2. Yes, unlike previous versions it scales:-) Previous
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// version was peforming *all* additions in IALU and was starving
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// for those even on Itanium 2. In this version one addition is
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// moved to FPU and is folded with multiplication. This is at cost
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// of propogating the result from previous call to this subroutine
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// to L2 cache... In other words negligible even for shorter keys.
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// *Overall* performance improvement [over previous version] varies
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// from 11 to 22 percent depending on key length.
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.L_bn_mul_add_words_ctop:
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{ .mfi; (p25) getf.sig r36=f52 // low
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(p21) xmpy.lu f48=f37,f8
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(p28) cmp.ltu p54,p50=r41,r39 }
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{ .mfi; (p16) ldf8 f32=[r15],8
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(p21) xmpy.hu f40=f37,f8
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(p28) add r45=r45,r41 };;
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{ .mii; (p25) getf.sig r32=f44 // high
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.pred.rel "mutex",p50,p54
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(p50) add r40=r38,r35 // (p27)
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(p54) add r40=r38,r35,1 } // (p27)
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{ .mfb; (p28) cmp.ltu.unc p60,p0=r45,r41
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(p0) nop.f 0x0
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(p0) nop.b 0x0 }
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{ .mii; (p27) ld8 r44=[r18],8
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(p62) cmp.eq.or p61,p0=-1,r46
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(p62) add r46=1,r46 }
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{ .mfb; (p30) st8 [r14]=r47,8
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(p0) nop.f 0x0
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.pred.rel "mutex",p40,p42
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{ .mfi; (p23) getf.sig r36=f45 // low
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(p20) xma.lu f42=f36,f8,f50 // low
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(p40) add r39=r39,r35 } // (p27)
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{ .mfi; (p16) ldf8 f32=[r15],8 // *(ap++)
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(p20) xma.hu f36=f36,f8,f50 // high
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(p42) add r39=r39,r35,1 };; // (p27)
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{ .mmi; (p24) getf.sig r32=f40 // high
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(p16) ldf8 f46=[r16],8 // *(rp1++)
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(p40) cmp.ltu p41,p39=r39,r35 } // (p27)
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{ .mib; (p26) st8 [r14]=r39,8 // *(rp2++)
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(p42) cmp.leu p41,p39=r39,r35 // (p27)
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br.ctop.sptk .L_bn_mul_add_words_ctop};;
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.L_bn_mul_add_words_cend:
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{ .mii; nop.m 0x0
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.pred.rel "mutex",p53,p57
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(p53) add r8=r38,r0
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(p57) add r8=r38,r0,1 }
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{ .mfb; nop.m 0x0
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nop.f 0x0
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nop.b 0x0 };;
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{ .mii;
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(p63) add r8=1,r8
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mov pr=r9,0x1ffff
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mov ar.lc=r3 }
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{ .mfb; rum 1<<5 // clear um.mfh
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nop.f 0x0
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{ .mmi; .pred.rel "mutex",p40,p42
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(p40) add r8=r35,r0
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(p42) add r8=r35,r0,1
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mov pr=r9,0x1ffff }
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{ .mib; rum 1<<5 // clear um.mfh
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mov ar.lc=r3
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br.ret.sptk.many b0 };;
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.endp bn_mul_add_words#
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#endif
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@ -527,7 +472,8 @@ bn_sqr_words:
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sxt4 r34=r34 };;
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{ .mii; cmp.le p6,p0=r34,r0
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mov r8=r0 } // return value
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{ .mfb; nop.f 0x0
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{ .mfb; ADDP r32=0,r32
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nop.f 0x0
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(p6) br.ret.spnt.many b0 };;
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.save ar.lc,r3
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@ -536,11 +482,7 @@ bn_sqr_words:
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mov r9=pr };;
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.body
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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{ .mii; addp4 r32=0,r32
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addp4 r33=0,r33 };;
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#endif
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{ .mib;
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{ .mib; ADDP r33=0,r33
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mov pr.rot=1<<16
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brp.loop.imp .L_bn_sqr_words_ctop,.L_bn_sqr_words_cend-16
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}
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@ -605,7 +547,7 @@ bn_sqr_comba8:
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.prologue
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.fframe 0
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.save ar.pfs,r2
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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#if defined(_HPUX_SOURCE) && !defined(_LP64)
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{ .mii; alloc r2=ar.pfs,2,1,0,0
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addp4 r33=0,r33
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addp4 r32=0,r32 };;
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@ -631,6 +573,10 @@ bn_sqr_comba8:
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// clause in Itanium µ-architecture manual? Comments are welcomed and
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// highly appreciated.
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//
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// On Itanium 2 it takes ~190 ticks. This is because of stalls on
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// result from getf.sig. I do nothing about it at this point for
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// reasons depicted below.
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//
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// However! It should be noted that even 160 ticks is darn good result
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// as it's over 10 (yes, ten, spelled as t-e-n) times faster than the
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// C version (compiled with gcc with inline assembler). I really
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@ -673,7 +619,7 @@ bn_mul_comba8:
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.prologue
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.fframe 0
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.save ar.pfs,r2
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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#if defined(_HPUX_SOURCE) && !defined(_LP64)
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{ .mii; alloc r2=ar.pfs,3,0,0,0
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addp4 r33=0,r33
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addp4 r34=0,r34 };;
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@ -1231,7 +1177,7 @@ bn_sqr_comba4:
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.prologue
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.fframe 0
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.save ar.pfs,r2
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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#if defined(_HPUX_SOURCE) && !defined(_LP64)
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{ .mii; alloc r2=ar.pfs,2,1,0,0
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addp4 r32=0,r32
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addp4 r33=0,r33 };;
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@ -1264,7 +1210,7 @@ bn_mul_comba4:
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.prologue
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.fframe 0
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.save ar.pfs,r2
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#if defined(_HPUX_SOURCE) && defined(_ILP32)
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#if defined(_HPUX_SOURCE) && !defined(_LP64)
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{ .mii; alloc r2=ar.pfs,3,0,0,0
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addp4 r33=0,r33
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addp4 r34=0,r34 };;
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@ -1448,8 +1394,8 @@ bn_mul_comba4:
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#define I r21
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#if 0
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// Some preprocessors (most notably HP-UX) apper to be allergic to
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// macros enclosed to parenthesis as these three will be.
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// Some preprocessors (most notably HP-UX) appear to be allergic to
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// macros enclosed to parenthesis [as these three were].
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#define cont p16
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#define break p0 // p20
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#define equ p24
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@ -1581,9 +1527,18 @@ bn_div_words:
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// output: f8 = (int)(a/b)
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// clobbered: f8,f9,f10,f11,pred
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pred=p15
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// This procedure is essentially Intel code and therefore is
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// copyrighted to Intel Corporation (I suppose...). It's sligtly
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// modified for specific needs.
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// One can argue that this snippet is copyrighted to Intel
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// Corporation, as it's essentially identical to one of those
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// found in "Divide, Square Root and Remainder" section at
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// http://www.intel.com/software/products/opensource/libraries/num.htm.
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// Yes, I admit that the referred code was used as template,
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// but after I realized that there hardly is any other instruction
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// sequence which would perform this operation. I mean I figure that
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// any independent attempt to implement high-performance division
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// will result in code virtually identical to the Intel code. It
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// should be noted though that below division kernel is 1 cycle
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// faster than Intel one (note commented splits:-), not to mention
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// original prologue (rather lack of one) and epilogue.
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.align 32
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.skip 16
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.L_udiv64_32_b6:
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