cornerMinEigenVal
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@ -12,7 +12,7 @@
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//
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// Copyright (C) 2000-2008, Intel Corporation, all rights reserved.
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// Copyright (C) 2009, Willow Garage Inc., all rights reserved.
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// Copyright (C) 2014, Itseez Inc., all rights reserved.
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// Copyright (C) 2014-2015, Itseez Inc., all rights reserved.
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// Third party copyrights are property of their respective owners.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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@ -271,6 +271,8 @@ cornerEigenValsVecs( const Mat& src, Mat& eigenv, int block_size,
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#ifdef HAVE_TEGRA_OPTIMIZATION
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if (tegra::cornerEigenValsVecs(src, eigenv, block_size, aperture_size, op_type, k, borderType))
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return;
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#elif CV_SSE2
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bool haveSSE2 = checkHardwareSupport(CV_CPU_SSE2);
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#endif
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int depth = src.depth();
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@ -319,6 +321,33 @@ cornerEigenValsVecs( const Mat& src, Mat& eigenv, int block_size,
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vst3q_f32(cov_data + j * 3, v_dst);
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}
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#elif CV_SSE2
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if (haveSSE2)
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{
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for( ; j <= size.width - 8; j += 8 )
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{
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__m128 v_dx_0 = _mm_loadu_ps(dxdata + j);
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__m128 v_dx_1 = _mm_loadu_ps(dxdata + j + 4);
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__m128 v_dy_0 = _mm_loadu_ps(dydata + j);
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__m128 v_dy_1 = _mm_loadu_ps(dydata + j + 4);
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__m128 v_dx2_0 = _mm_mul_ps(v_dx_0, v_dx_0);
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__m128 v_dxy_0 = _mm_mul_ps(v_dx_0, v_dy_0);
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__m128 v_dy2_0 = _mm_mul_ps(v_dy_0, v_dy_0);
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__m128 v_dx2_1 = _mm_mul_ps(v_dx_1, v_dx_1);
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__m128 v_dxy_1 = _mm_mul_ps(v_dx_1, v_dy_1);
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__m128 v_dy2_1 = _mm_mul_ps(v_dy_1, v_dy_1);
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_mm_interleave_ps(v_dx2_0, v_dx2_1, v_dxy_0, v_dxy_1, v_dy2_0, v_dy2_1);
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_mm_storeu_ps(cov_data + j * 3, v_dx2_0);
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_mm_storeu_ps(cov_data + j * 3 + 4, v_dx2_1);
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_mm_storeu_ps(cov_data + j * 3 + 8, v_dxy_0);
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_mm_storeu_ps(cov_data + j * 3 + 12, v_dxy_1);
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_mm_storeu_ps(cov_data + j * 3 + 16, v_dy2_0);
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_mm_storeu_ps(cov_data + j * 3 + 20, v_dy2_1);
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}
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}
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#endif
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for( ; j < size.width; j++ )
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@ -736,8 +736,6 @@ struct ColumnSum<int, int> :
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bool haveScale = scale != 1;
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double _scale = scale;
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printf("bgfbffbbfg\n");
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#if CV_SSE2
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bool haveSSE2 = checkHardwareSupport(CV_CPU_SSE2);
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#endif
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