generic-library/isa-l
1
0
Fork 0
mirror of https://github.com/intel/isa-l.git synced 2024-12-12 09:23:50 +01:00
Code Issues Projects Releases Wiki Activity
ece814e912
isa-l/mem
History
H.J. Lu cd888f01a4 x86: Add ENDBR32/ENDBR64 at function entries for Intel CET 
To support Intel CET, all indirect branch targets must start with
ENDBR32/ENDBR64.  Here is a patch to define endbranch and add it to
function entries in x86 assembly codes which are indirect branch
targets as discovered by running testsuite on Intel CET machine and
visual inspection.

Verified with

$ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux
$ make -j8
$ make -j8 check

with both nasm and yasm on both CET and non-CET machines.

Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2020-05-26 09:16:49 -07:00
..
aarch64 multibinary: Add run-time cpu feature detect for aarch64 2019-08-26 17:58:42 +08:00
Makefile.am enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
mem_multibinary.asm mem: Add zero detect memory functions 2018-09-25 14:33:31 -07:00
mem_zero_detect_avx.asm x86: Add ENDBR32/ENDBR64 at function entries for Intel CET 2020-05-26 09:16:49 -07:00
mem_zero_detect_base_aliases.c mem: Add zero detect memory functions 2018-09-25 14:33:31 -07:00
mem_zero_detect_base.c mem: Remove unaligned loads in base function 2019-03-07 09:27:50 -07:00
mem_zero_detect_perf.c all: Revamp performance testing to be time based 2019-03-07 09:28:04 -07:00
mem_zero_detect_sse.asm x86: Add ENDBR32/ENDBR64 at function entries for Intel CET 2020-05-26 09:16:49 -07:00
mem_zero_detect_test.c mem: Change test r and l data type to avoid unsigned add overflow 2019-03-07 09:27:50 -07:00