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NASM version 2.14.01 supports all x86 ISA in this library. Since this version has been out since 2018, it is safe to only permit the library to be compiled with this minimum version, as announced in issue #297. Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
139 lines
3.5 KiB
NASM
139 lines
3.5 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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%include "reg_sizes.asm"
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%include "multibinary.asm"
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default rel
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[bits 64]
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extern pq_gen_base
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extern pq_gen_sse
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extern pq_gen_avx
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extern pq_gen_avx2
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extern xor_gen_base
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extern xor_gen_sse
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extern xor_gen_avx
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extern pq_check_base
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extern pq_check_sse
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extern xor_check_base
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extern xor_check_sse
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extern xor_gen_avx512
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extern pq_gen_avx512
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extern pq_gen_avx512_gfni
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extern pq_gen_avx2_gfni
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mbin_interface xor_gen
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mbin_interface pq_gen
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mbin_dispatch_init6 xor_gen, xor_gen_base, xor_gen_sse, xor_gen_avx, xor_gen_avx, xor_gen_avx512
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mbin_dispatch_init8 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2, pq_gen_avx512, pq_gen_avx2_gfni, pq_gen_avx512_gfni
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section .data
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xor_check_dispatched:
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dq xor_check_mbinit
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pq_check_dispatched:
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dq pq_check_mbinit
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section .text
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;;;;
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; pq_check multibinary function
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;;;;
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mk_global pq_check, function
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pq_check_mbinit:
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endbranch
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call pq_check_dispatch_init
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pq_check:
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endbranch
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jmp qword [pq_check_dispatched]
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pq_check_dispatch_init:
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push rax
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push rbx
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push rcx
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push rdx
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push rsi
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lea rsi, [pq_check_base WRT_OPT] ; Default
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mov eax, 1
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cpuid
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test ecx, FLAG_CPUID1_ECX_SSE4_1
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lea rbx, [pq_check_sse WRT_OPT]
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cmovne rsi, rbx
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mov [pq_check_dispatched], rsi
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pop rsi
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pop rdx
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pop rcx
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pop rbx
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pop rax
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ret
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;;;;
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; xor_check multibinary function
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;;;;
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mk_global xor_check, function
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xor_check_mbinit:
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endbranch
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call xor_check_dispatch_init
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xor_check:
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endbranch
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jmp qword [xor_check_dispatched]
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xor_check_dispatch_init:
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push rax
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push rbx
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push rcx
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push rdx
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push rsi
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lea rsi, [xor_check_base WRT_OPT] ; Default
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mov eax, 1
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cpuid
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test ecx, FLAG_CPUID1_ECX_SSE4_1
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lea rbx, [xor_check_sse WRT_OPT]
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cmovne rsi, rbx
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mov [xor_check_dispatched], rsi
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pop rsi
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pop rdx
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pop rcx
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pop rbx
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pop rax
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ret
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