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8045bee170
NASM version 2.14.01 supports all x86 ISA in this library. Since this version has been out since 2018, it is safe to only permit the library to be compiled with this minimum version, as announced in issue #297. Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
143 lines
3.7 KiB
NASM
143 lines
3.7 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2018 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%include "reg_sizes.asm"
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%ifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define tmpb r11b
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%define tmp3 arg4
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%define return rax
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%define func(x) x: endbranch
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%define FUNC_SAVE
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%define FUNC_RESTORE
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%endif
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define tmp r11
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%define tmpb r11b
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%define tmp3 r10
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%define return rax
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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end_prolog
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%endmacro
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%macro FUNC_RESTORE 0
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%endmacro
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%endif
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%define src arg0
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%define len arg1
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%define tmp0 arg2
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%define tmp1 arg3
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%use smartalign
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ALIGNMODE P6
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default rel
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[bits 64]
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section .text
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align 32 ; maximize mu-ops cache coverage
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mk_global mem_zero_detect_avx512, function
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func(mem_zero_detect_avx512)
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FUNC_SAVE
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or tmp1, -1 ; all ones mask
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mov eax, DWORD(src)
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and eax, 63
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neg rax
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add rax, 64 ; 64 - eax
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cmp rax, len
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cmovae eax, DWORD(len)
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bzhi tmp1, tmp1, rax ; alignment mask
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kmovq k1, tmp1
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vmovdqu8 zmm0{k1}{z}, [src]
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add src, rax ; align to cacheline
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sub len, rax
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vptestmb k1, zmm0, zmm0
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xor DWORD(tmp0), DWORD(tmp0)
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ktestq k1, k1
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setnz BYTE(tmp0)
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mov DWORD(tmp3), DWORD(len)
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xor eax, eax
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shr len, 7 ; len/128
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setz al
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add eax, DWORD(tmp0)
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jnz .mem_z_small_block
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align 16
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.mem_z_loop:
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vmovdqa64 zmm0, [src]
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vporq zmm0, zmm0,[src+64]
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xor tmp1,tmp1
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sub len, 1
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setz BYTE(tmp1)
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add src, 128
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vptestmb k1, zmm0, zmm0
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kmovq tmp0, k1
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add tmp1, tmp0 ; for macrofusion.
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jz .mem_z_loop
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align 16
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.mem_z_small_block:
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;len < 128
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xor eax, eax
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lea tmp1, [rax-1] ; 0xFFFFFF...
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mov DWORD(len), DWORD(tmp3)
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and DWORD(len), 127 ; len % 128
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and DWORD(tmp3),63 ; len % 64
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bzhi tmp, tmp1, tmp3; mask
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cmp DWORD(len), 64
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cmovb tmp1, tmp
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cmovb tmp, rax
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kmovq k1, tmp1
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kmovq k2, tmp
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vmovdqu8 zmm0{k1}{z}, [src]
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vmovdqu8 zmm1{k2}{z}, [src+64]
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vporq zmm0, zmm0, zmm1
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vptestmb k1, zmm0, zmm0
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kmovq tmp1, k1
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or tmp0, tmp1
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setnz al ; eax is still zero
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FUNC_RESTORE
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ret
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endproc_frame
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