mirror of
https://github.com/intel/isa-l.git
synced 2024-12-12 09:23:50 +01:00
623d2f0dc0
Update Bitbuf to use stdmac and decrease register dependencies by replaces a sub with an and. Change-Id: Iaadf3c6ef7f533540a7adb57a418e9e80e9b8503 Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
65 lines
2.4 KiB
NASM
65 lines
2.4 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
; Copyright(c) 2011-2016 Intel Corporation All rights reserved.
|
|
;
|
|
; Redistribution and use in source and binary forms, with or without
|
|
; modification, are permitted provided that the following conditions
|
|
; are met:
|
|
; * Redistributions of source code must retain the above copyright
|
|
; notice, this list of conditions and the following disclaimer.
|
|
; * Redistributions in binary form must reproduce the above copyright
|
|
; notice, this list of conditions and the following disclaimer in
|
|
; the documentation and/or other materials provided with the
|
|
; distribution.
|
|
; * Neither the name of Intel Corporation nor the names of its
|
|
; contributors may be used to endorse or promote products derived
|
|
; from this software without specific prior written permission.
|
|
;
|
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
%include "options.asm"
|
|
%include "stdmac.asm"
|
|
|
|
; Assumes m_out_buf is a register
|
|
; Clobbers RCX
|
|
; code is clobbered
|
|
; write_bits_always m_bits, m_bit_count, code, count, m_out_buf
|
|
%macro write_bits 5
|
|
%define %%m_bits %1
|
|
%define %%m_bit_count %2
|
|
%define %%code %3
|
|
%define %%count %4
|
|
%define %%m_out_buf %5
|
|
|
|
SHLX %%code, %%code, %%m_bit_count
|
|
|
|
or %%m_bits, %%code
|
|
add %%m_bit_count, %%count
|
|
|
|
mov [%%m_out_buf], %%m_bits
|
|
mov rcx, %%m_bit_count
|
|
shr rcx, 3 ; rcx = bytes
|
|
add %%m_out_buf, rcx
|
|
shl rcx, 3 ; rcx = bits
|
|
and %%m_bit_count, 0x7
|
|
|
|
SHRX %%m_bits, %%m_bits, rcx
|
|
%endm
|
|
|
|
%macro write_dword 2
|
|
%define %%data %1d
|
|
%define %%addr %2
|
|
mov [%%addr], %%data
|
|
add %%addr, 4
|
|
%endm
|