generic-library/isa-l
1
0
Fork 0
mirror of https://github.com/intel/isa-l.git synced 2024-12-12 09:23:50 +01:00
Code Issues Projects Releases Wiki Activity

igzip: Bitbuf improvements

Browse Source 
Update Bitbuf to use stdmac and decrease register dependencies by replaces a sub
with an and.

Change-Id: Iaadf3c6ef7f533540a7adb57a418e9e80e9b8503
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
This commit is contained in:
Roy Oursler 2019-01-17 13:37:08 -07:00
parent 53b92e83f4
commit 623d2f0dc0
1 changed files with 6 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
igzip/bitbuf2.asm
View File

@ -28,6 +28,7 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
%include "options.asm"
%include "stdmac.asm"
; Assumes m_out_buf is a register
; Clobbers RCX
@ -40,12 +41,8 @@
%define %%count %4
%define %%m_out_buf %5
%ifdef USE_HSWNI
shlx %%code, %%code, %%m_bit_count
%else
mov rcx, %%m_bit_count
shl %%code, cl
%endif
SHLX %%code, %%code, %%m_bit_count
or %%m_bits, %%code
add %%m_bit_count, %%count
@ -54,12 +51,9 @@
shr rcx, 3 ; rcx = bytes
add %%m_out_buf, rcx
shl rcx, 3 ; rcx = bits
sub %%m_bit_count, rcx
%ifdef USE_HSWNI
shrx %%m_bits, %%m_bits, rcx
%else
shr %%m_bits, cl
%endif
and %%m_bit_count, 0x7
SHRX %%m_bits, %%m_bits, rcx
%endm
%macro write_dword 2