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Author SHA1 Message Date
Taiju Yamada
ae034d6f08 Use _byteswap_ushort etc for WIN32 
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
 2024-11-21 15:30:27 +00:00
Taiju Yamada
ea1288fc6a Disable hardening build on mingw 
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
 2024-11-21 15:30:27 +00:00
Marcel Cornu
aaad73e15d workflows: add validation to windows build 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-11-19 17:02:28 +00:00
Cornu, Marcel D
07f8028743 erasure_code: fix unaligned free error in perf apps on windows 
Signed-off-by: Cornu, Marcel D <marcel.d.cornu@intel.com>
 2024-11-19 14:20:33 +00:00
Cornu, Marcel D
00d6e6fe87 add perf target to windows makefile 
Signed-off-by: Cornu, Marcel D <marcel.d.cornu@intel.com>
 2024-11-19 14:20:33 +00:00
Marcel Cornu
496255cda6 tools: format source files in parallel 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-06-06 12:34:36 +01:00
Greg Troxel
0231d314f5 Extend FreeBSD conditional about byte ordering to NetBSD 
NetBSD has the same byte-ordering idioms as FreeBSD.

Signed-off-by: Greg Troxel <gdt@lexort.com>
 2024-06-06 12:33:54 +01:00
Bernd Schubert
dbaf284e11 aarch64_multibinary.h: Fix -Wasm-operand-widths 
Compilation with clang gave warnings as per below.
Arm64 is has a width of 64 bit and these warnings came up.

In file included from igzip/aarch64/igzip_multibinary_aarch64_dispatcher.c:29:
./include/aarch64_multibinary.h:338:35: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths]
                asm("mrs %0, MIDR_EL1 " : "=r" (id));
                                                ^
./include/aarch64_multibinary.h:338:12: note: use constraint modifier "w"
                asm("mrs %0, MIDR_EL1 " : "=r" (id));
                         ^~
                         %w0
1 warning generated.
In file included from mem/aarch64/mem_aarch64_dispatcher.c:29:
./include/aarch64_multibinary.h:338:35: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths]
                asm("mrs %0, MIDR_EL1 " : "=r" (id));
                                                ^
./include/aarch64_multibinary.h:338:12: note: use constraint modifier "w"
                asm("mrs %0, MIDR_EL1 " : "=r" (id));
                         ^~
                         %w0
1 warning generated.

Signed-off-by: Bernd Schubert <bschubert@ddn.com>
 2024-05-31 17:02:19 +01:00
Pablo de Lara
4e898eced6 mem: fix build on FreeBSD 
Fix build warnings on FreeBSD, due to unused value.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-05-31 13:30:48 +01:00
Pablo de Lara
7ebc65baa7 igzip: fix build on FreeBSD 
Fix build warnings on FreeBSD, due to unused value.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-05-31 13:30:48 +01:00
Pablo de Lara
47b2c5ab15 Makefile: remove duplicated pattern match 
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-05-31 13:30:48 +01:00
Marcel Cornu
0234d629a4 clang-format: ignore aarch64_label.h 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-05-03 13:19:17 +01:00
Marcel Cornu
84ad119970 programs: add igzip binary as man page dependency 
Required to support parallel builds

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-05-03 13:19:17 +01:00
Marcel Cornu
75ce489550 workflows: use clang-format-18 to check format 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-04-22 11:35:03 +02:00
Marcel Cornu
9ab5a9e579 tests: reformat using new code style 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-04-22 11:35:03 +02:00
Marcel Cornu
ae951677ab raid: reformat using new code style 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-04-22 11:35:03 +02:00
Marcel Cornu
cf6105271a programs: reformat using new code style 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-04-22 11:35:03 +02:00
Marcel Cornu
aaa78d6a7c mem: reformat using new code style 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-04-22 11:35:03 +02:00
Marcel Cornu
fa5b8baf84 include: reformat using new code style 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-04-22 11:35:03 +02:00
Marcel Cornu
55fbfabfc6 igzip: reformat using new code style 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-04-22 11:35:03 +02:00
Marcel Cornu
9d99f8215d examples: reformat using new code style 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-04-22 11:35:03 +02:00
Marcel Cornu
300260a4d9 erasure_code: reformat using new code style 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-04-22 11:35:03 +02:00
Marcel Cornu
671e67b62d crc: reformat using new code style 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-04-22 11:35:03 +02:00
Marcel Cornu
07bca509e7 tools: use clang-format for style checking 
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
 2024-04-22 11:35:03 +02:00
Taiju Yamada
7b30857e20 Run macos-13 (actual x86_64 latest) and macos-14 (arm64) CIs 
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
 2024-03-25 15:34:01 +00:00
Taiju Yamada
38279f5e9e Avoid using x18 register 
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
 2024-03-25 15:34:01 +00:00
Taiju Yamada
14ec878aae enable macOS extended test 
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
 2024-03-21 09:58:33 +00:00
Taiju Yamada
4b74fb2204 tools: replace echo -n with printf 
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
 2024-03-21 09:58:33 +00:00
Pablo de Lara
69d4a8a081 Add CI/Coverity/OpenSSF scorecard badges 
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-03-19 21:30:50 +00:00
Pablo de Lara
8c2ff41c7f build: allow alternative compiler 
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-03-14 13:41:41 +00:00
orbea
37005a00fc tools: fix shebang 
This causes a build failure with slibtool.

Gentoo issue: https://bugs.gentoo.org/829500

Signed-off-by: orbea <orbea@riseup.net>
 2024-03-12 14:25:16 +00:00
Taiju Yamada
f1b144bbab Fix mach compilation again; fold_constant has to be the same section as crc16_t10dif_copy_pmull 
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
 2024-03-07 10:10:51 +00:00
Taiju Yamada
4be96e2437 Fixed isal_deflate_icf_finish_lvl1 dispatcher 
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
 2024-03-07 10:10:39 +00:00
Taiju Yamada
f36d1ede78 add libtool dependency for MacOS CI 
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
 2024-03-01 11:37:29 +00:00
Colin Ian King
1500db751d Fix a handful of spelling mistakes and typos 
There are quite a few spelling mistakes and typos in comments and
user facing message literal strings as found using codespell. Fix
these.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-02-06 15:03:14 +00:00
Pablo de Lara
ffc16330d8 makefile: add spellcheck 
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-02-06 15:03:14 +00:00
Mattias Ellert
1b1ee1e18f erasure_code: fix wrong return type 
erasure_code/ppc64le/gf_vect_mul_vsx.c: In function '_gf_vect_mul_base':
erasure_code/ppc64le/gf_vect_mul_vsx.c:14:16: error: 'return' with a value, in function returning void [-Wreturn-mismatch]
   14 |         return 0;
      |                ^
erasure_code/ppc64le/gf_vect_mul_vsx.c:6:13: note: declared here
    6 | static void _gf_vect_mul_base(int len, unsigned char *a, unsigned char *src,
      |             ^~~~~~~~~~~~~~~~~

Signed-off-by: Mattias Ellert <mattias.ellert@physics.uu.se>
 2024-01-23 12:01:14 +00:00
Pablo de Lara
bd22637502 Bump version to v2.31 
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-01-18 18:27:24 +00:00
Pablo de Lara
d4e1c21acb lib: add missing structure documentation 
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-01-15 16:58:43 +00:00
Pablo de Lara
4997190ab3 Update release notes for v2.31 
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-01-15 16:55:28 +00:00
Greg Tucker
479b3f84f9 build: fix CET default in unix Makefile 
CET default flag was clobbering CFLAGS.

Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
 2024-01-15 16:53:04 +00:00
Pablo de Lara
e0fd782974 erasure_code: use internal gf_vect_mul_base for ppc64le encoding 
gf_vect_mul_base is expected to work for all buffer sizes.
However, this function is checking for size alignment to 32 bytes,
to follow the other gf_vect_mul implementations.
Therefore, another implementation for this function is included
inside ppc64le folder to be used by the encoding functions.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-01-15 15:48:14 +00:00
Pablo de Lara
b8d5633e51 erasure_code: check for size alignment on powerpc gf_vect_mul_vsx implementation 
Follows the rest of the gf_vect_mul implementations for other architectures,
and checks for size alignment, stated in the documentation.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-01-15 15:48:14 +00:00
Pablo de Lara
91e7906f3f erasure_code: check for size on gf_vect_mul_sse/avx 
gf_vect_mul requires length to be multiple of 32 bytes,
so this check is added in the SSE/AVX implementations.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-01-15 13:52:08 +00:00
liuqinfei
275977156d gf_vect_mul_sve: fix error and enable unit tests for aarch64 
Signed-off-by: liuqinfei <lucas.liuqinfei@huawei.com>
 2024-01-12 15:18:37 +00:00
Pablo de Lara
e0fffbe48b erasure_code: disable unit tests temporarily for aarch64/ppc64le 
Some aarch64 and ppc64le implementations of gf_vect_mul do not check
for invalid sizes, so the unit test checking for negative return value
from this function is disabled temporarily on these architectures.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-01-10 15:53:14 +00:00
Pablo de Lara
7145c7f8b4 Makefile: add architecture to CFLAGS 
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-01-10 15:53:14 +00:00
Pablo de Lara
455fdded4e erasure_code: add missing aarch64 and powerpc interface for ec_init_tables 
ec_init_tables is now a multi-implementation function,
so it requires a dispatcher for all architectures.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-01-09 13:38:43 +00:00
Pablo de Lara
ae0a688051 Update License file 
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
 2024-01-09 09:42:48 +00:00
Tomasz Kantecki
75af1c4d4e build: detect availability of -z now, relro and noexecstack linker options 
Signed-off-by: Tomasz Kantecki <tomasz.kantecki@intel.com>
 2024-01-05 14:45:12 +00:00