Commit Graph

624 Commits

Author SHA1 Message Date
Marcel Cornu
164d9ff1f0 erasure_code: add 2 vector AVX2 dot product with GFNI implementation
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-12-11 22:44:07 +00:00
Pablo de Lara
f82746491e tools: check code style first
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-11 15:23:56 +00:00
Pablo de Lara
8f2634aeac raid: remove unneeded load
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-11 09:31:11 +00:00
Pablo de Lara
5d6092c832 raid: optimize final parity check
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-11 09:31:11 +00:00
Pablo de Lara
bf8f2a25ba raid: fix function descriptions
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-11 09:31:11 +00:00
Marcel Cornu
307d737bf2 erasure_code: add 3 vector AVX2 dot product with GFNI implementation
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-12-07 14:01:18 +00:00
Pablo de Lara
4203d9628c igzip: fix null-terminated string setting
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-07 13:34:21 +00:00
Pablo de Lara
4a4635e8db igzip: remove unneeded check
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-07 13:34:21 +00:00
Pablo de Lara
02aa005c2d igzip: fix return value in wrapper header test
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-07 13:34:21 +00:00
Pablo de Lara
6dc544c661 Ignore obsolete warnings when using autoreconf
A few macros are declared obsolete from autoconf 2.70.
In order to avoid breaking compatibility with 2.69 removing them,
these warnings are ignored.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-07 13:29:03 +00:00
Pablo de Lara
7e2b097f15 igzip: fix build warnings on Windows
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-07 13:23:09 +00:00
Pablo de Lara
6188bf7b2f crc: fix build warnings on Windows
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-07 13:23:09 +00:00
Pablo de Lara
df073be348 tools: allow testing on multiple architectures with Intel SDE
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-01 14:33:29 +00:00
Pablo de Lara
2ca781df19 lib: reduce verbosity by default in tests
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-01 14:33:29 +00:00
Marcel Cornu
5f23c03415 erasure_code: add initial AVX2 mad with GFNI implementation
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-12-01 14:20:56 +00:00
Pablo de Lara
447d9af75b erasure_code: add initial AVX2 dot product with GFNI implementation
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-12-01 14:20:56 +00:00
Marcel Cornu
637f5a631d include: add memcpy asm module
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-12-01 14:20:56 +00:00
Marcel Cornu
bc34d87427 erasure_code: update GF_MUL_XOR macro to support VEX encoding
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-12-01 14:20:56 +00:00
Pablo de Lara
c8dd92f04a lib: add new interface supporting AVX2 with GFNI
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-12-01 14:20:56 +00:00
Pablo de Lara
f971f02309 erasure_code: expose base implementation of init_tables
Expose ec_init_tables_base(), which should be used
with ec_encode_data_base() and ec_encode_data_update_base().

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-23 10:56:28 +00:00
Pablo de Lara
65e89717df erasure_code: implement EC update with AVX512 + GFNI
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-23 10:56:28 +00:00
Pablo de Lara
1eff12dddb erasure_code: implement EC with AVX512 + GFNI
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-23 10:56:28 +00:00
Pablo de Lara
9d487fd6db erasure_code: [perf] get parameters for number of buffers
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-23 10:56:28 +00:00
Pablo de Lara
07af4032ff erasure_code: fix stack allocation
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-23 10:56:28 +00:00
Pablo de Lara
801df41929 erasure_code: fix vmovdqa instruction
vmovdqa needs to be vmovdqa32/64 when used on ZMMs (EVEX encoded).

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-23 10:56:28 +00:00
Pablo de Lara
34463cb663 ci: build with EC_ALIGNED_ADDR and NO_NT_LDST
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-23 10:56:28 +00:00
Pablo de Lara
e2acfbfe78 igzip: fix build warning
Fix the following build issue by initializing look_back_dist to 0.

igzip/igzip_inflate.c: In function ‘decode_huffman_code_block_stateless_base’:
igzip/igzip_inflate.c:1727:36:
 warning: ‘look_back_dist’ may be used uninitialized  [-Wmaybe-uninitialized]

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-15 13:46:52 +00:00
Pablo de Lara
acbe0deecf crc: fix build with NASM 2.14
Fix following compilation error
crc/crc32_iscsi_by16_10.s:408: error: invalid combination of opcode and operands

Fixes #257.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-15 13:42:00 +00:00
liuqinfei
4815174a68 crc: optimize by supporting arm xor fusion feature
Arrange the two xor instructions according to the specified
paradigm, then the two xor instructions can be fused to execute
which can save one issue slot and one execution latency.

Change-Id: Ic64bcfe569b2468e4dc9c13d073d367cc81fd937
Signed-off-by: liuqinfei <lucas.liuqinfei@huawei.com>
2023-08-18 07:53:59 +00:00
Pablo de Lara
f534a5c6a9 crc: fold 64 bytes of data if possible
When less than 256 bytes of data are left, fold data
in steps of 64 bytes, instead of 16 bytes, if there is enough
data.

Change-Id: I47d7cacdd1ba620078df528136945695c338db6d
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-08-17 11:54:24 +01:00
Pablo de Lara
beab678fb8 crc: optimize last bytes
Change-Id: I4b8f73b23eb50c4c50ca65fab19716f217fe5780
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-08-17 11:54:20 +01:00
Greg Tucker
e53db85631 doc: Add notes on reentrancy and threading
Fixes #249

Change-Id: Id56464436aeeb2c16bab2cbc0efeb4fded80dc4f
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2023-07-19 13:11:43 -07:00
Pablo de Lara
e1e0df6c7e Update README.md
libtool is required for the autotool build otherwise you will get the "error: possibly undefined macro: AC_PROG_LD" error message

Change-Id: Ifa4d8fd48dba6714246390aadedaecb844c206c9
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-07-06 09:41:56 +01:00
Pablo de Lara
2bbce31943 crc: add CRC64 rocksoft implementation
- Added reference implementation
- Added base implementation
- Added functional and performance tests

Change-Id: I60c5097bd5fb89ee7a50910e71d449d50d155d0a
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2023-05-08 12:37:44 +00:00
Pablo de Lara
16056ff4e4 crc: refactor SSE CRC64 implementations to use common code
Change-Id: I2d141f2ccd12ab338783e50736e36ed4aeb11f7f
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-05-08 12:37:44 +00:00
Pablo de Lara
22d33cf795 crc: use k-mask to load final bytes of data
Change-Id: Ibd8d2144bc6942e11911e25a6365c1cb108af477
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-05-08 12:37:23 +00:00
Greg Tucker
9f2b68f057 igzip: Add precautionary reset hist_bits on stateless_init
The zstate.hist_bits is an option and shouldn't be set randomly by a
deflate stateless run but like level we may set anyway.

Change-Id: I37d3b51863d4697e964d45a482ddd526f40a0902
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2023-03-14 17:26:58 -07:00
Greg Tucker
33a2d94845 doc: Updates and info on crc combine
Change-Id: Ibe5d6c61e73a03e7ff1840ca0335ada3657eaf00
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2023-02-10 17:44:52 -07:00
Greg Tucker
4cbd285861 ex: Add crc combine example for multiple polynomials
Change-Id: I55b6585f768877cffe1cbe16802456c8a12aea28
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2023-02-10 15:41:35 -07:00
Taiju Yamada
ad39d7ccfd Include hwcap.h only in C compilation
Change-Id: I08a75896ebd49634f31a80ed37acf2a1267fe156
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
2022-12-08 14:10:30 -07:00
Greg Tucker
c2bec3ea65 crc: Use ternlog in by16 avx512 loop
Ternlog has additional benefit in by16 crc main loop in both reflected
and non-reflected polynomial crcs. Some arch see 4-7% improvement.
Revisited on suggestion by Nicola Torracca.

Change-Id: I806266a7080168cf33409634983e254a291a0795
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2022-11-02 12:16:20 -07:00
Greg Tucker
fec429e1b9 build: Add top-level read-only permissions to ci actions
This is recommended by ossf scorecard:
https://github.com/ossf/scorecard/blob/main/docs/checks.md#token-permissions

Change-Id: I48a36cc6625fa3f1e6babb9edbe81c9522f41a13
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2022-10-28 17:05:01 -07:00
Taiju Yamada
1187583a97 Fixes for aarch64 mac
- It should be fine to enable pmull always on Apple Silicon
- macOS 12+ is required for PMULL instruction.
- Changed the conditional macro to __APPLE__
- Rewritten dispatcher using sysctlbyname
- Use __USER_LABEL_PREFIX__
- Use __TEXT,__const as readonly section
- use ASM_DEF_RODATA macro
- fix func decl

Change-Id: I800593f21085d8187b480c8bb3ab2bd70c4a6974
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
2022-10-28 08:27:26 -07:00
Surendar Chandra
85716fe2fe Correct loop bounds check in aarch64 gf_vect_mul
Prior to this change, a missing loop bounds check in the aarch64
version of gf_vect_mul would cause the routine to return 1 (error)
in the normal case.

This change introduces a check and branch to "return_pass" (success), and
also adds checks of the return code of gf_vect_mul to the supplied unit
test; it was previously ignored.

Change-Id: I9f7fe0014189b24f9600e0473ee02b5316c2da91
Signed-off-by: Surendar Chandra <vsurench@amazon.com>
2022-10-27 15:30:00 -07:00
Pawel Piatek
b6e96427d2 Use gindent on FreeBSD
Also add workaround for GNU indent bug.

Signed-off-by: Pawel Piatek <pawelx.piatek@intel.com>
Change-Id: I9478a06dc17675c858030cfe15552609fef021da
2022-10-11 12:30:53 +02:00
Greg Tucker
04f3125ea0 test: Move perf routine output from stack to heap
Large cold perf tests were allocating more then allowed stack size.

Change-Id: I2c54f36ac6b42b359078dae7fffa5ce0b6d4890a
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2022-08-08 15:19:03 -07:00
Greg Tucker
9c7e3b9f22 test: Change perf tests to warm by default
The cold versions of tests depended on a fixed size of last level
cache that is too low on some arch and too high for the total
available memory on others.

Change-Id: Iee98403f9ace02e01b810c296a5fe44b933bfb17
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2022-08-03 16:35:55 -07:00
Greg Tucker
2bcbaf4c39 doc: Add security policy file
Change-Id: Id5703011c296bd79b57ce2342b3bc25f82c6bd99
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2022-07-18 19:53:53 -07:00
Greg Tucker
9f75defd57 Remove all slver legacy segments
The relic slver is no longer used for individual versioning
on functions and is confusing tools looking for data in text
sections. This removes all instances instead of fixing since
its usefulness is waining. Fixes #221

Change-Id: Ife0b9f105950a90337c58e8a41ac2cffc0f67d99
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2022-07-14 19:23:52 -07:00
Greg Tucker
62519d97ec build: Remove ms link flag for msvcrt
The cflag to link with dynamic msvcrt /MD is not necessary and causes
warnings when static linking.  Fixes #219

Change-Id: I0085d468afc4acbe323b0783cbbc6760b4c70704
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2022-07-11 16:16:07 -07:00