The ISA-L EC code has been written using RVV vector instructions and the minimum multiplication table,
resulting in a performance improvement of over 10 times compared to the existing implementation.
Signed-off-by: Shuo Lv <lv.shuo@sanechips.com.cn>
Added new RAID performance application which consolidates the
existing XOR and P+Q gen performance applications.
This application accepts buffer sizes to benchmark,
as a single value, list or range, and the RAID function
to test and the number of sources.
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Added new CRC performance application which consolidates the
existing CRC performance applications (CRC16, CRC32 and CRC64).
This application accepts buffer sizes to benchmark,
as a single value, list or range, and the CRC function
to test (or all of them).
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
As already announced in issue #296, we are removing 32-bit x86 support,
which was not being validated anyway.
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
NASM version 2.14.01 supports all x86 ISA in this library.
Since this version has been out since 2018, it is safe to
only permit the library to be compiled with this minimum version,
as announced in issue #297.
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
There are quite a few spelling mistakes and typos in comments and
user facing message literal strings as found using codespell. Fix
these.
Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
- Includes gf_nvect_dot_prod, gf_nvect_mad functions
- Change ec multibinary to use common macros
- Autoconf checks for nasm or yasm support and picks if available
- Leave out compile of any avx512 code if assembler not available
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
