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add R-V V build check

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Signed-off-by: sunyuechi <sunyuechi@iscas.ac.cn>
This commit is contained in:
sunyuechi
2025-02-27 12:19:09 +08:00
committed by Pablo de Lara
parent 027be4beb9
commit c0bd84c20e
4 changed files with 44 additions and 11 deletions
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45
configure.ac
View File

@@ -39,16 +39,7 @@ AM_CONDITIONAL([CPU_AARCH64], [test "$CPU" = "aarch64"])
AM_CONDITIONAL([CPU_PPC64LE], [test "$CPU" = "ppc64le"]) AM_CONDITIONAL([CPU_PPC64LE], [test "$CPU" = "ppc64le"])
AM_CONDITIONAL([CPU_RISCV64], [test "$CPU" = "riscv64"]) AM_CONDITIONAL([CPU_RISCV64], [test "$CPU" = "riscv64"])
AM_CONDITIONAL([CPU_UNDEFINED], [test "x$CPU" = "x"]) AM_CONDITIONAL([CPU_UNDEFINED], [test "x$CPU" = "x"])
AM_CONDITIONAL([HAVE_RVV], [false])
if test "$CPU" = "x86_64"; then
is_x86=yes
else
if test "$CPU" = "x86_32"; then
is_x86=yes
else
is_x86=no
fi
fi
# Check for programs # Check for programs
AC_PROG_CC_STDC AC_PROG_CC_STDC
@@ -59,6 +50,40 @@ AC_PREFIX_DEFAULT([/usr])
AC_PROG_SED AC_PROG_SED
AC_PROG_MKDIR_P AC_PROG_MKDIR_P
case "${CPU}" in
x86_64)
is_x86=yes
;;
x86_32)
is_x86=yes
;;
riscv64)
AC_MSG_CHECKING([checking RVV support])
AC_COMPILE_IFELSE(
[AC_LANG_PROGRAM([], [
__asm__ volatile(
".option arch, +v\n"
"vsetivli zero, 0, e8, m1, ta, ma\n"
);
])],
[AC_DEFINE([HAVE_RVV], [1], [Enable RVV instructions])
AM_CONDITIONAL([HAVE_RVV], [true]) rvv=yes],
[AM_CONDITIONAL([HAVE_RVV], [false]) rvv=no]
)
AC_MSG_RESULT([$rvv])
;;
*)
is_x86=no
esac
# Options # Options
AC_ARG_ENABLE([debug], AC_ARG_ENABLE([debug],
AS_HELP_STRING([--enable-debug], [enable debug messages @<:@default=disabled@:>@]), AS_HELP_STRING([--enable-debug], [enable debug messages @<:@default=disabled@:>@]),

2
igzip/riscv64/igzip_isal_adler32_rvv.S
View File

@@ -26,6 +26,7 @@
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**********************************************************************/ **********************************************************************/
#if HAVE_RVV
.option arch, +v .option arch, +v
.global adler32_rvv .global adler32_rvv
.type adler32_rvv, %function .type adler32_rvv, %function
@@ -74,3 +75,4 @@ adler32_rvv:
add a0, t2, t3 // a0 = A + B add a0, t2, t3 // a0 = A + B
ret ret
#endif

6
igzip/riscv64/igzip_multibinary_riscv64.S
View File

@@ -29,7 +29,11 @@
#include "riscv64_multibinary.h" #include "riscv64_multibinary.h"
mbin_interface isal_adler32 #if HAVE_RVV
mbin_interface isal_adler32
#else
mbin_interface_base isal_adler32, adler32_base
#endif
mbin_interface_base gen_icf_map_lh1, gen_icf_map_h1_base mbin_interface_base gen_icf_map_lh1, gen_icf_map_h1_base
mbin_interface_base decode_huffman_code_block_stateless, decode_huffman_code_block_stateless_base mbin_interface_base decode_huffman_code_block_stateless, decode_huffman_code_block_stateless_base

2
igzip/riscv64/igzip_multibinary_riscv64_dispatcher.c
View File

@@ -30,9 +30,11 @@
DEFINE_INTERFACE_DISPATCHER(isal_adler32) DEFINE_INTERFACE_DISPATCHER(isal_adler32)
{ {
#if HAVE_RVV
const unsigned long hwcap = getauxval(AT_HWCAP); const unsigned long hwcap = getauxval(AT_HWCAP);
if (hwcap & HWCAP_RV('V')) if (hwcap & HWCAP_RV('V'))
return PROVIDER_INFO(adler32_rvv); return PROVIDER_INFO(adler32_rvv);
else else
#endif
return PROVIDER_BASIC(adler32); return PROVIDER_BASIC(adler32);
} }