diff --git a/configure.ac b/configure.ac
index 954bc55..9c6ab57 100644
--- a/configure.ac
+++ b/configure.ac
@@ -39,16 +39,7 @@ AM_CONDITIONAL([CPU_AARCH64], [test "$CPU" = "aarch64"])
 AM_CONDITIONAL([CPU_PPC64LE], [test "$CPU" = "ppc64le"])
 AM_CONDITIONAL([CPU_RISCV64], [test "$CPU" = "riscv64"])
 AM_CONDITIONAL([CPU_UNDEFINED], [test "x$CPU" = "x"])
-
-if test "$CPU" = "x86_64"; then
-   is_x86=yes
-else
-   if test "$CPU" = "x86_32"; then
-      is_x86=yes
-   else
-      is_x86=no
-   fi
-fi
+AM_CONDITIONAL([HAVE_RVV], [false])
 
 # Check for programs
 AC_PROG_CC_STDC
@@ -59,6 +50,40 @@ AC_PREFIX_DEFAULT([/usr])
 AC_PROG_SED
 AC_PROG_MKDIR_P
 
+case "${CPU}" in
+
+	x86_64)
+
+		is_x86=yes
+		;;
+
+	x86_32)
+
+		is_x86=yes
+		;;
+
+	riscv64)
+
+		AC_MSG_CHECKING([checking RVV support])
+		AC_COMPILE_IFELSE(
+			[AC_LANG_PROGRAM([], [
+				__asm__ volatile(
+					".option arch, +v\n"
+					"vsetivli zero, 0, e8, m1, ta, ma\n"
+				);
+			])],
+			[AC_DEFINE([HAVE_RVV], [1], [Enable RVV instructions])
+			AM_CONDITIONAL([HAVE_RVV], [true]) rvv=yes],
+			[AM_CONDITIONAL([HAVE_RVV], [false]) rvv=no]
+		)
+		AC_MSG_RESULT([$rvv])
+		;;
+
+	*)
+		is_x86=no
+
+esac
+
 # Options
 AC_ARG_ENABLE([debug],
         AS_HELP_STRING([--enable-debug], [enable debug messages @<:@default=disabled@:>@]),
diff --git a/igzip/riscv64/igzip_isal_adler32_rvv.S b/igzip/riscv64/igzip_isal_adler32_rvv.S
index 28c4a08..958bc8c 100644
--- a/igzip/riscv64/igzip_isal_adler32_rvv.S
+++ b/igzip/riscv64/igzip_isal_adler32_rvv.S
@@ -26,6 +26,7 @@
   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **********************************************************************/
+#if HAVE_RVV
 .option         arch, +v
 .global         adler32_rvv
 .type           adler32_rvv, %function
@@ -74,3 +75,4 @@ adler32_rvv:
   add           a0, t2, t3                           // a0 = A + B
 
   ret
+#endif
diff --git a/igzip/riscv64/igzip_multibinary_riscv64.S b/igzip/riscv64/igzip_multibinary_riscv64.S
index 3658014..75afe7b 100644
--- a/igzip/riscv64/igzip_multibinary_riscv64.S
+++ b/igzip/riscv64/igzip_multibinary_riscv64.S
@@ -29,7 +29,11 @@
 
 #include "riscv64_multibinary.h"
 
-mbin_interface		isal_adler32
+#if HAVE_RVV
+    mbin_interface		isal_adler32
+#else
+    mbin_interface_base		isal_adler32, adler32_base
+#endif
 
 mbin_interface_base gen_icf_map_lh1, gen_icf_map_h1_base
 mbin_interface_base decode_huffman_code_block_stateless, decode_huffman_code_block_stateless_base
diff --git a/igzip/riscv64/igzip_multibinary_riscv64_dispatcher.c b/igzip/riscv64/igzip_multibinary_riscv64_dispatcher.c
index daf7066..8bc095f 100644
--- a/igzip/riscv64/igzip_multibinary_riscv64_dispatcher.c
+++ b/igzip/riscv64/igzip_multibinary_riscv64_dispatcher.c
@@ -30,9 +30,11 @@
 
 DEFINE_INTERFACE_DISPATCHER(isal_adler32)
 {
+#if HAVE_RVV
         const unsigned long hwcap = getauxval(AT_HWCAP);
         if (hwcap & HWCAP_RV('V'))
                 return PROVIDER_INFO(adler32_rvv);
         else
+#endif
                 return PROVIDER_BASIC(adler32);
 }