generic-library/isa-l
1
0
Fork 0
mirror of https://github.com/intel/isa-l.git synced 2024-12-12 17:33:50 +01:00
Code Issues Projects Releases Wiki Activity

Remove all slver legacy segments

Browse Source 
The relic slver is no longer used for individual versioning
on functions and is confusing tools looking for data in text
sections. This removes all instances instead of fixing since
its usefulness is waining. Fixes #221

Change-Id: Ife0b9f105950a90337c58e8a41ac2cffc0f67d99
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
This commit is contained in:
Greg Tucker 2022-07-14 16:50:49 -07:00
parent 62519d97ec
commit 9f75defd57
74 changed files with 4 additions and 420 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
crc/crc16_t10dif_01.asm
View File

@ -660,7 +660,3 @@ pshufb_shf_table:
; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15 ; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15
dq 0x8786858483828100, 0x8f8e8d8c8b8a8988 dq 0x8786858483828100, 0x8f8e8d8c8b8a8988
dq 0x0706050403020100, 0x000e0d0c0b0a0908 dq 0x0706050403020100, 0x000e0d0c0b0a0908
;;; func core, ver, snum
slversion crc16_t10dif_01, 01, 06, 0010

3
crc/crc16_t10dif_by4.asm
View File

@ -558,6 +558,3 @@ pshufb_shf_table:
; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15 ; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15
dq 0x8786858483828100, 0x8f8e8d8c8b8a8988 dq 0x8786858483828100, 0x8f8e8d8c8b8a8988
dq 0x0706050403020100, 0x000e0d0c0b0a0908 dq 0x0706050403020100, 0x000e0d0c0b0a0908
;;; func core, ver, snum
slversion crc16_t10dif_by4, 05, 02, 0016

3
crc/crc16_t10dif_copy_by4.asm
View File

@ -594,6 +594,3 @@ pshufb_shf_table:
; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15 ; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15
dq 0x8786858483828100, 0x8f8e8d8c8b8a8988 dq 0x8786858483828100, 0x8f8e8d8c8b8a8988
dq 0x0706050403020100, 0x000e0d0c0b0a0908 dq 0x0706050403020100, 0x000e0d0c0b0a0908
;;; func core, ver, snum
slversion crc16_t10dif_copy_by4, 05, 02, 0000

3
crc/crc32_gzip_refl_by8.asm
View File

@ -620,6 +620,3 @@ pshufb_shf_table:
; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15 ; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15
dq 0x8786858483828100, 0x8f8e8d8c8b8a8988 dq 0x8786858483828100, 0x8f8e8d8c8b8a8988
dq 0x0706050403020100, 0x000e0d0c0b0a0908 dq 0x0706050403020100, 0x000e0d0c0b0a0908
;;; func core, ver, snum
slversion crc32_gzip_refl_by8, 01, 00, 002c

4
crc/crc32_ieee_01.asm
View File

@ -650,7 +650,3 @@ pshufb_shf_table:
; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15 ; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15
dq 0x8786858483828100, 0x8f8e8d8c8b8a8988 dq 0x8786858483828100, 0x8f8e8d8c8b8a8988
dq 0x0706050403020100, 0x000e0d0c0b0a0908 dq 0x0706050403020100, 0x000e0d0c0b0a0908
;;; func core, ver, snum
slversion crc32_ieee_01, 01, 06, 0011

3
crc/crc32_ieee_by4.asm
View File

@ -561,6 +561,3 @@ pshufb_shf_table:
SHUF_MASK dq 0x08090A0B0C0D0E0F, 0x0001020304050607 SHUF_MASK dq 0x08090A0B0C0D0E0F, 0x0001020304050607
;;; func core, ver, snum
slversion crc32_ieee_by4, 05, 02, 0017

6
crc/crc32_iscsi_00.asm
View File

@ -36,6 +36,8 @@
%include "reg_sizes.asm" %include "reg_sizes.asm"
default rel default rel
section .text
; crcB3 MACRO to implement crc32 on 3 %%bSize-byte blocks ; crcB3 MACRO to implement crc32 on 3 %%bSize-byte blocks
%macro crcB3 3 %macro crcB3 3
%define %%bSize %1 ; 1/3 of buffer size %define %%bSize %1 ; 1/3 of buffer size
@ -666,7 +668,3 @@ DD 0xd875c27e,0x051309c5,0x675423f9,0xba32e842
DD 0xa3da7781,0x7ebcbc3a,0x1cfb9606,0xc19d5dbd DD 0xa3da7781,0x7ebcbc3a,0x1cfb9606,0xc19d5dbd
DD 0x2f2aa980,0xf24c623b,0x900b4807,0x4d6d83bc DD 0x2f2aa980,0xf24c623b,0x900b4807,0x4d6d83bc
DD 0x54851c7f,0x89e3d7c4,0xeba4fdf8,0x36c23643 DD 0x54851c7f,0x89e3d7c4,0xeba4fdf8,0x36c23643
;;; func core, ver, snum
slversion crc32_iscsi_00, 00, 04, 0014

6
crc/crc32_iscsi_01.asm
View File

@ -32,6 +32,8 @@
%include "reg_sizes.asm" %include "reg_sizes.asm"
default rel default rel
section .text
%define CONCAT(a,b,c) a %+ b %+ c %define CONCAT(a,b,c) a %+ b %+ c
; Define threshold where buffers are considered "small" and routed to more ; Define threshold where buffers are considered "small" and routed to more
@ -586,7 +588,3 @@ K_table:
dq 0x045cddf4e, 0x0e0ac139e dq 0x045cddf4e, 0x0e0ac139e
dq 0x1a91647f2, 0x169cf9eb0 dq 0x1a91647f2, 0x169cf9eb0
dq 0x1a0f717c4, 0x0170076fa dq 0x1a0f717c4, 0x0170076fa
;;; func core, ver, snum
slversion crc32_iscsi_01, 01, 04, 0015

24
crc/crc64_base.c
View File

@ -886,27 +886,3 @@ uint64_t crc64_jones_norm_base(uint64_t seed, const uint8_t * buf, uint64_t len)
return ~crc; return ~crc;
} }
struct slver {
unsigned short snum;
unsigned char ver;
unsigned char core;
};
struct slver crc64_ecma_refl_base_slver_0000001c;
struct slver crc64_ecma_refl_base_slver = { 0x001c, 0x00, 0x00 };
struct slver crc64_ecma_norm_base_slver_00000019;
struct slver crc64_ecma_norm_base_slver = { 0x0019, 0x00, 0x00 };
struct slver crc64_iso_refl_base_slver_00000022;
struct slver crc64_iso_refl_base_slver = { 0x0022, 0x00, 0x00 };
struct slver crc64_iso_norm_base_slver_0000001f;
struct slver crc64_iso_norm_base_slver = { 0x001f, 0x00, 0x00 };
struct slver crc64_jones_refl_base_slver_00000028;
struct slver crc64_jones_refl_base_slver = { 0x0028, 0x00, 0x00 };
struct slver crc64_jones_norm_base_slver_00000025;
struct slver crc64_jones_norm_base_slver = { 0x0025, 0x00, 0x00 };

3
crc/crc64_ecma_norm_by8.asm
View File

@ -579,6 +579,3 @@ dq 0x8786858483828100, 0x8f8e8d8c8b8a8988
dq 0x0706050403020100, 0x0f0e0d0c0b0a0908 dq 0x0706050403020100, 0x0f0e0d0c0b0a0908
dq 0x8080808080808080, 0x0f0e0d0c0b0a0908 dq 0x8080808080808080, 0x0f0e0d0c0b0a0908
dq 0x8080808080808080, 0x8080808080808080 dq 0x8080808080808080, 0x8080808080808080
;;; func core, ver, snum
slversion crc64_ecma_norm_by8, 01, 00, 001a

3
crc/crc64_ecma_refl_by8.asm
View File

@ -544,6 +544,3 @@ mask2:
dq 0xFFFFFFFF00000000, 0xFFFFFFFFFFFFFFFF dq 0xFFFFFFFF00000000, 0xFFFFFFFFFFFFFFFF
mask3: mask3:
dq 0x8080808080808080, 0x8080808080808080 dq 0x8080808080808080, 0x8080808080808080
;;; func core, ver, snum
slversion crc64_ecma_refl_by8, 01, 00, 001d

3
crc/crc64_iso_norm_by8.asm
View File

@ -577,6 +577,3 @@ dq 0x8786858483828100, 0x8f8e8d8c8b8a8988
dq 0x0706050403020100, 0x0f0e0d0c0b0a0908 dq 0x0706050403020100, 0x0f0e0d0c0b0a0908
dq 0x8080808080808080, 0x0f0e0d0c0b0a0908 dq 0x8080808080808080, 0x0f0e0d0c0b0a0908
dq 0x8080808080808080, 0x8080808080808080 dq 0x8080808080808080, 0x8080808080808080
;;; func core, ver, snum
slversion crc64_iso_norm_by8, 01, 00, 0020

3
crc/crc64_iso_refl_by8.asm
View File

@ -540,6 +540,3 @@ mask2:
dq 0xFFFFFFFF00000000, 0xFFFFFFFFFFFFFFFF dq 0xFFFFFFFF00000000, 0xFFFFFFFFFFFFFFFF
mask3: mask3:
dq 0x8080808080808080, 0x8080808080808080 dq 0x8080808080808080, 0x8080808080808080
;;; func core, ver, snum
slversion crc64_iso_refl_by8, 01, 00, 0023

3
crc/crc64_jones_norm_by8.asm
View File

@ -577,6 +577,3 @@ dq 0x8786858483828100, 0x8f8e8d8c8b8a8988
dq 0x0706050403020100, 0x0f0e0d0c0b0a0908 dq 0x0706050403020100, 0x0f0e0d0c0b0a0908
dq 0x8080808080808080, 0x0f0e0d0c0b0a0908 dq 0x8080808080808080, 0x0f0e0d0c0b0a0908
dq 0x8080808080808080, 0x8080808080808080 dq 0x8080808080808080, 0x8080808080808080
;;; func core, ver, snum
slversion crc64_jones_norm_by8, 01, 00, 0026

3
crc/crc64_jones_refl_by8.asm
View File

@ -540,6 +540,3 @@ mask2:
dq 0xFFFFFFFF00000000, 0xFFFFFFFFFFFFFFFF dq 0xFFFFFFFF00000000, 0xFFFFFFFFFFFFFFFF
mask3: mask3:
dq 0x8080808080808080, 0x8080808080808080 dq 0x8080808080808080, 0x8080808080808080
;;; func core, ver, snum
slversion crc64_jones_refl_by8, 01, 00, 0029

8
crc/crc64_multibinary.asm
View File

@ -82,11 +82,3 @@ mbin_interface crc64_jones_refl
mbin_dispatch_init7 crc64_jones_refl, crc64_jones_refl_base, crc64_jones_refl_by8, crc64_jones_refl_by8, crc64_jones_refl_by8, crc64_jones_refl_by8, crc64_jones_refl_by16_10 mbin_dispatch_init7 crc64_jones_refl, crc64_jones_refl_base, crc64_jones_refl_by8, crc64_jones_refl_by8, crc64_jones_refl_by8, crc64_jones_refl_by8, crc64_jones_refl_by16_10
mbin_interface crc64_jones_norm mbin_interface crc64_jones_norm
mbin_dispatch_init7 crc64_jones_norm, crc64_jones_norm_base, crc64_jones_norm_by8, crc64_jones_norm_by8, crc64_jones_norm_by8, crc64_jones_norm_by8, crc64_jones_norm_by16_10 mbin_dispatch_init7 crc64_jones_norm, crc64_jones_norm_base, crc64_jones_norm_by8, crc64_jones_norm_by8, crc64_jones_norm_by8, crc64_jones_norm_by8, crc64_jones_norm_by16_10
;;; func core, ver, snum
slversion crc64_ecma_refl, 00, 00, 001b
slversion crc64_ecma_norm, 00, 00, 0018
slversion crc64_iso_refl, 00, 00, 0021
slversion crc64_iso_norm, 00, 00, 001e
slversion crc64_jones_refl, 00, 00, 0027
slversion crc64_jones_norm, 00, 00, 0024

18
crc/crc_base.c
View File

@ -331,21 +331,3 @@ uint32_t crc32_gzip_refl_base(uint32_t seed, uint8_t * buf, uint64_t len)
return ~crc; return ~crc;
} }
struct slver {
unsigned short snum;
unsigned char ver;
unsigned char core;
};
struct slver crc32_iscsi_base_slver_0001011d;
struct slver crc32_iscsi_base_slver = { 0x011d, 0x02, 0x00 };
struct slver crc16_t10dif_base_slver_0001011e;
struct slver crc16_t10dif_base_slver = { 0x011e, 0x02, 0x00 };
struct slver crc32_ieee_base_slver_0001011f;
struct slver crc32_ieee_base_slver = { 0x011f, 0x02, 0x00 };
struct slver crc32_gzip_refl_base_slver_0000002b;
struct slver crc32_gzip_refl_base_slver = { 0x002b, 0x00, 0x00 };

6
crc/crc_multibinary.asm
View File

@ -320,9 +320,3 @@ mbin_dispatch_init_clmul crc32_gzip_refl, crc32_gzip_refl_base, crc32_gzip_refl_
mbin_interface crc16_t10dif_copy mbin_interface crc16_t10dif_copy
mbin_dispatch_init_clmul crc16_t10dif_copy, crc16_t10dif_copy_base, crc16_t10dif_copy_by4, crc16_t10dif_copy_by4_02, crc16_t10dif_copy_by4_02 mbin_dispatch_init_clmul crc16_t10dif_copy, crc16_t10dif_copy_base, crc16_t10dif_copy_by4, crc16_t10dif_copy_by4_02, crc16_t10dif_copy_by4_02
;;; func core, ver, snum
slversion crc16_t10dif, 00, 03, 011a
slversion crc32_ieee, 00, 03, 011b
slversion crc32_iscsi, 00, 03, 011c
slversion crc32_gzip_refl, 00, 00, 002a

31
erasure_code/ec_base.c
View File

@ -338,34 +338,3 @@ void gf_vect_mul_base(int len, unsigned char *a, unsigned char *src, unsigned ch
while (len-- > 0) while (len-- > 0)
*dest++ = gf_mul(c, *src++); *dest++ = gf_mul(c, *src++);
} }
struct slver {
unsigned short snum;
unsigned char ver;
unsigned char core;
};
// Version info
struct slver gf_vect_mul_init_slver_00020035;
struct slver gf_vect_mul_init_slver = { 0x0035, 0x02, 0x00 };
struct slver ec_encode_data_base_slver_00010135;
struct slver ec_encode_data_base_slver = { 0x0135, 0x01, 0x00 };
struct slver gf_vect_mul_base_slver_00010136;
struct slver gf_vect_mul_base_slver = { 0x0136, 0x01, 0x00 };
struct slver gf_vect_dot_prod_base_slver_00010137;
struct slver gf_vect_dot_prod_base_slver = { 0x0137, 0x01, 0x00 };
struct slver gf_mul_slver_00000214;
struct slver gf_mul_slver = { 0x0214, 0x00, 0x00 };
struct slver gf_invert_matrix_slver_00000215;
struct slver gf_invert_matrix_slver = { 0x0215, 0x00, 0x00 };
struct slver gf_gen_rs_matrix_slver_00000216;
struct slver gf_gen_rs_matrix_slver = { 0x0216, 0x00, 0x00 };
struct slver gf_gen_cauchy1_matrix_slver_00000217;
struct slver gf_gen_cauchy1_matrix_slver = { 0x0217, 0x00, 0x00 };

13
erasure_code/ec_highlevel_func.c
View File

@ -359,16 +359,3 @@ void ec_encode_data_update_avx2(int len, int k, int rows, int vec_i, unsigned ch
#endif //__WORDSIZE == 64 || _WIN64 || __x86_64__ #endif //__WORDSIZE == 64 || _WIN64 || __x86_64__
#endif //__x86_64__ || __i386__ || _M_X64 || _M_IX86 #endif //__x86_64__ || __i386__ || _M_X64 || _M_IX86
struct slver {
unsigned short snum;
unsigned char ver;
unsigned char core;
};
// Version info
struct slver ec_init_tables_slver_00010068;
struct slver ec_init_tables_slver = { 0x0068, 0x01, 0x00 };
struct slver ec_encode_data_sse_slver_00020069;
struct slver ec_encode_data_sse_slver = { 0x0069, 0x02, 0x00 };

7
erasure_code/ec_multibinary.asm
View File

@ -86,10 +86,3 @@ mbin_interface gf_vect_mad
mbin_dispatch_init6 gf_vect_mad, gf_vect_mad_base, gf_vect_mad_sse, gf_vect_mad_avx, gf_vect_mad_avx2, gf_vect_mad_avx512 mbin_dispatch_init6 gf_vect_mad, gf_vect_mad_base, gf_vect_mad_sse, gf_vect_mad_avx, gf_vect_mad_avx2, gf_vect_mad_avx512
mbin_dispatch_init6 gf_vect_dot_prod, gf_vect_dot_prod_base, gf_vect_dot_prod_sse, gf_vect_dot_prod_avx, gf_vect_dot_prod_avx2, gf_vect_dot_prod_avx512 mbin_dispatch_init6 gf_vect_dot_prod, gf_vect_dot_prod_base, gf_vect_dot_prod_sse, gf_vect_dot_prod_avx, gf_vect_dot_prod_avx2, gf_vect_dot_prod_avx512
%endif %endif
;;; func core, ver, snum
slversion ec_encode_data, 00, 06, 0133
slversion gf_vect_mul, 00, 05, 0134
slversion ec_encode_data_update, 00, 05, 0212
slversion gf_vect_dot_prod, 00, 05, 0138
slversion gf_vect_mad, 00, 04, 0213

3
erasure_code/gf_2vect_dot_prod_avx.asm
View File

@ -332,6 +332,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_2vect_dot_prod_avx, 02, 05, 0191

5
erasure_code/gf_2vect_dot_prod_avx2.asm
View File

@ -349,8 +349,3 @@ func(gf_2vect_dot_prod_avx2)
ret ret
endproc_frame endproc_frame
section .data
;;; func core, ver, snum
slversion gf_2vect_dot_prod_avx2, 04, 05, 0196

3
erasure_code/gf_2vect_dot_prod_sse.asm
View File

@ -334,6 +334,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_2vect_dot_prod_sse, 00, 04, 0062

3
erasure_code/gf_2vect_mad_avx.asm
View File

@ -231,6 +231,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_2vect_mad_avx, 02, 01, 0204

5
erasure_code/gf_2vect_mad_avx2.asm
View File

@ -240,8 +240,3 @@ func(gf_2vect_mad_avx2)
ret ret
endproc_frame endproc_frame
section .data
;;; func core, ver, snum
slversion gf_2vect_mad_avx2, 04, 01, 0205

3
erasure_code/gf_2vect_mad_sse.asm
View File

@ -234,6 +234,3 @@ align 16
mask0f: mask0f:
dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_2vect_mad_sse, 00, 01, 0203

3
erasure_code/gf_3vect_dot_prod_avx.asm
View File

@ -372,6 +372,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_3vect_dot_prod_avx, 02, 05, 0192

5
erasure_code/gf_3vect_dot_prod_avx2.asm
View File

@ -390,8 +390,3 @@ func(gf_3vect_dot_prod_avx2)
ret ret
endproc_frame endproc_frame
section .data
;;; func core, ver, snum
slversion gf_3vect_dot_prod_avx2, 04, 05, 0197

3
erasure_code/gf_3vect_dot_prod_sse.asm
View File

@ -373,6 +373,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_3vect_dot_prod_sse, 00, 06, 0063

3
erasure_code/gf_3vect_mad_avx.asm
View File

@ -283,6 +283,3 @@ align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
constip16: constip16:
dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7 dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
;;; func core, ver, snum
slversion gf_3vect_mad_avx, 02, 01, 0207

3
erasure_code/gf_3vect_mad_avx2.asm
View File

@ -312,6 +312,3 @@ align 32
constip32: constip32:
dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7 dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
dq 0xe8e9eaebecedeeef, 0xe0e1e2e3e4e5e6e7 dq 0xe8e9eaebecedeeef, 0xe0e1e2e3e4e5e6e7
;;; func core, ver, snum
slversion gf_3vect_mad_avx2, 04, 01, 0208

3
erasure_code/gf_3vect_mad_sse.asm
View File

@ -293,6 +293,3 @@ mask0f:
dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
constip16: constip16:
dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7 dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
;;; func core, ver, snum
slversion gf_3vect_mad_sse, 00, 01, 0206

3
erasure_code/gf_4vect_dot_prod_avx.asm
View File

@ -436,6 +436,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_4vect_dot_prod_avx, 02, 05, 0193

5
erasure_code/gf_4vect_dot_prod_avx2.asm
View File

@ -453,8 +453,3 @@ func(gf_4vect_dot_prod_avx2)
ret ret
endproc_frame endproc_frame
section .data
;;; func core, ver, snum
slversion gf_4vect_dot_prod_avx2, 04, 05, 0198

3
erasure_code/gf_4vect_dot_prod_sse.asm
View File

@ -438,6 +438,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_4vect_dot_prod_sse, 00, 06, 0064

3
erasure_code/gf_4vect_mad_avx.asm
View File

@ -331,6 +331,3 @@ align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
constip16: constip16:
dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7 dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
;;; func core, ver, snum
slversion gf_4vect_mad_avx, 02, 01, 020a

3
erasure_code/gf_4vect_mad_avx2.asm
View File

@ -337,6 +337,3 @@ align 32
constip32: constip32:
dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7 dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
dq 0xe8e9eaebecedeeef, 0xe0e1e2e3e4e5e6e7 dq 0xe8e9eaebecedeeef, 0xe0e1e2e3e4e5e6e7
;;; func core, ver, snum
slversion gf_4vect_mad_avx2, 04, 01, 020b

3
erasure_code/gf_4vect_mad_sse.asm
View File

@ -337,6 +337,3 @@ mask0f:
dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
constip16: constip16:
dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7 dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
;;; func core, ver, snum
slversion gf_4vect_mad_sse, 00, 01, 0209

3
erasure_code/gf_5vect_dot_prod_avx.asm
View File

@ -298,6 +298,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_5vect_dot_prod_avx, 02, 04, 0194

5
erasure_code/gf_5vect_dot_prod_avx2.asm
View File

@ -308,8 +308,3 @@ func(gf_5vect_dot_prod_avx2)
ret ret
endproc_frame endproc_frame
section .data
;;; func core, ver, snum
slversion gf_5vect_dot_prod_avx2, 04, 04, 0199

3
erasure_code/gf_5vect_dot_prod_sse.asm
View File

@ -299,6 +299,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_5vect_dot_prod_sse, 00, 05, 0065

3
erasure_code/gf_5vect_mad_avx.asm
View File

@ -360,6 +360,3 @@ align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
constip16: constip16:
dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7 dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
;;; func core, ver, snum
slversion gf_5vect_mad_avx, 02, 01, 020d

3
erasure_code/gf_5vect_mad_avx2.asm
View File

@ -358,6 +358,3 @@ align 32
constip32: constip32:
dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7 dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
dq 0xe8e9eaebecedeeef, 0xe0e1e2e3e4e5e6e7 dq 0xe8e9eaebecedeeef, 0xe0e1e2e3e4e5e6e7
;;; func core, ver, snum
slversion gf_5vect_mad_avx2, 04, 01, 020e

3
erasure_code/gf_5vect_mad_sse.asm
View File

@ -368,6 +368,3 @@ mask0f:
dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
constip16: constip16:
dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7 dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
;;; func core, ver, snum
slversion gf_5vect_mad_sse, 00, 01, 020c

3
erasure_code/gf_6vect_dot_prod_avx.asm
View File

@ -310,6 +310,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_6vect_dot_prod_avx, 02, 04, 0195

5
erasure_code/gf_6vect_dot_prod_avx2.asm
View File

@ -319,8 +319,3 @@ func(gf_6vect_dot_prod_avx2)
ret ret
endproc_frame endproc_frame
section .data
;;; func core, ver, snum
slversion gf_6vect_dot_prod_avx2, 04, 04, 019a

3
erasure_code/gf_6vect_dot_prod_sse.asm
View File

@ -310,6 +310,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_6vect_dot_prod_sse, 00, 05, 0066

3
erasure_code/gf_6vect_mad_avx.asm
View File

@ -389,6 +389,3 @@ align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
constip16: constip16:
dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7 dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
;;; func core, ver, snum
slversion gf_6vect_mad_avx, 02, 01, 0210

3
erasure_code/gf_6vect_mad_avx2.asm
View File

@ -395,6 +395,3 @@ align 32
constip32: constip32:
dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7 dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
dq 0xe8e9eaebecedeeef, 0xe0e1e2e3e4e5e6e7 dq 0xe8e9eaebecedeeef, 0xe0e1e2e3e4e5e6e7
;;; func core, ver, snum
slversion gf_6vect_mad_avx2, 04, 01, 0211

3
erasure_code/gf_6vect_mad_sse.asm
View File

@ -401,6 +401,3 @@ align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
constip16: constip16:
dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7 dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
;;; func core, ver, snum
slversion gf_6vect_mad_sse, 00, 01, 020f

3
erasure_code/gf_vect_dot_prod_avx.asm
View File

@ -266,6 +266,3 @@ align 16
mask0f: mask0f:
dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_vect_dot_prod_avx, 02, 05, 0061

5
erasure_code/gf_vect_dot_prod_avx2.asm
View File

@ -273,8 +273,3 @@ func(gf_vect_dot_prod_avx2)
ret ret
endproc_frame endproc_frame
section .data
;;; func core, ver, snum
slversion gf_vect_dot_prod_avx2, 04, 05, 0190

3
erasure_code/gf_vect_dot_prod_sse.asm
View File

@ -266,6 +266,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_vect_dot_prod_sse, 00, 05, 0060

3
erasure_code/gf_vect_mad_avx.asm
View File

@ -191,6 +191,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_vect_mad_avx, 02, 01, 0201

5
erasure_code/gf_vect_mad_avx2.asm
View File

@ -196,8 +196,3 @@ func(gf_vect_mad_avx2)
ret ret
endproc_frame endproc_frame
section .data
;;; func core, ver, snum
slversion gf_vect_mad_avx2, 04, 01, 0202

3
erasure_code/gf_vect_mad_sse.asm
View File

@ -192,6 +192,3 @@ section .data
align 16 align 16
mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_vect_mad_sse, 00, 01, 0200

3
erasure_code/gf_vect_mul_avx.asm
View File

@ -159,6 +159,3 @@ align 16
mask0f: mask0f:
dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_vect_mul_avx, 01, 03, 0036

3
erasure_code/gf_vect_mul_sse.asm
View File

@ -165,6 +165,3 @@ section .data
align 16 align 16
mask0f: mask0f:
dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
;;; func core, ver, snum
slversion gf_vect_mul_sse, 00, 03, 0034

16
igzip/huff_codes.c
View File

@ -599,22 +599,6 @@ static struct hufftables_icf static_hufftables = {
{{{.code_and_extra = 0x000,.length2 = 0x0}}}} {{{.code_and_extra = 0x000,.length2 = 0x0}}}}
}; };
struct slver {
uint16_t snum;
uint8_t ver;
uint8_t core;
};
/* Version info */
struct slver isal_update_histogram_slver_00010085;
struct slver isal_update_histogram_slver = { 0x0085, 0x01, 0x00 };
struct slver isal_create_hufftables_slver_00010086;
struct slver isal_create_hufftables_slver = { 0x0086, 0x01, 0x00 };
struct slver isal_create_hufftables_subset_slver_00010087;
struct slver isal_create_hufftables_subset_slver = { 0x0087, 0x01, 0x00 };
extern uint32_t build_huff_tree(struct heap_tree *heap, uint64_t heap_size, uint64_t node_ptr); extern uint32_t build_huff_tree(struct heap_tree *heap, uint64_t heap_size, uint64_t node_ptr);
extern void build_heap(uint64_t * heap, uint64_t heap_size); extern void build_heap(uint64_t * heap, uint64_t heap_size);

28
igzip/igzip.c
View File

@ -94,34 +94,6 @@ static void write_header(struct isal_zstream *stream, uint8_t * deflate_hdr,
uint32_t next_state, uint32_t toggle_end_of_stream); uint32_t next_state, uint32_t toggle_end_of_stream);
static void write_trailer(struct isal_zstream *stream); static void write_trailer(struct isal_zstream *stream);
struct slver {
uint16_t snum;
uint8_t ver;
uint8_t core;
};
/* Version info */
struct slver isal_deflate_init_slver_01030081;
struct slver isal_deflate_init_slver = { 0x0081, 0x03, 0x01 };
struct slver isal_deflate_reset_slver_0001008e;
struct slver isal_deflate_reset_slver = { 0x008e, 0x01, 0x00 };
struct slver isal_deflate_stateless_init_slver_00010084;
struct slver isal_deflate_stateless_init_slver = { 0x0084, 0x01, 0x00 };
struct slver isal_deflate_slver_01030082;
struct slver isal_deflate_slver = { 0x0082, 0x03, 0x01 };
struct slver isal_deflate_stateless_slver_01010083;
struct slver isal_deflate_stateless_slver = { 0x0083, 0x01, 0x01 };
struct slver isal_deflate_set_hufftables_slver_0001008b;
struct slver isal_deflate_set_hufftables_slver = { 0x008b, 0x01, 0x00 };
struct slver isal_deflate_set_dict_slver_0001008c;
struct slver isal_deflate_set_dict_slver = { 0x008c, 0x01, 0x00 };
/*****************************************************************/ /*****************************************************************/
// isal_adler32_bam1 - adler with (B | A minus 1) storage // isal_adler32_bam1 - adler with (B | A minus 1) storage

22
igzip/igzip_inflate.c
View File

@ -126,28 +126,6 @@ static struct rfc1951_tables rfc_lookup_table = {
0x0083, 0x00a3, 0x00c3, 0x00e3, 0x0102, 0x0103, 0x0000, 0x0000} 0x0083, 0x00a3, 0x00c3, 0x00e3, 0x0102, 0x0103, 0x0000, 0x0000}
}; };
struct slver {
uint16_t snum;
uint8_t ver;
uint8_t core;
};
/* Version info */
struct slver isal_inflate_init_slver_00010088;
struct slver isal_inflate_init_slver = { 0x0088, 0x01, 0x00 };
struct slver isal_inflate_reset_slver_0001008f;
struct slver isal_inflate_reset_slver = { 0x008f, 0x01, 0x00 };
struct slver isal_inflate_stateless_slver_00010089;
struct slver isal_inflate_stateless_slver = { 0x0089, 0x01, 0x00 };
struct slver isal_inflate_slver_0001008a;
struct slver isal_inflate_slver = { 0x008a, 0x01, 0x00 };
struct slver isal_inflate_set_dict_slver_0001008d;
struct slver isal_inflate_set_dict_slver = { 0x008d, 0x01, 0x00 };
/*Performs a copy of length repeat_length data starting at dest - /*Performs a copy of length repeat_length data starting at dest -
* lookback_distance into dest. This copy copies data previously copied when the * lookback_distance into dest. This copy copies data previously copied when the
* src buffer and the dest buffer overlap. */ * src buffer and the dest buffer overlap. */

11
include/reg_sizes.asm
View File

@ -294,15 +294,4 @@ section .text
%define elf64 macho64 %define elf64 macho64
mac_equ equ 1 mac_equ equ 1
%endif %endif
%macro slversion 4
section .text
global %1_slver_%2%3%4
global %1_slver
%1_slver:
%1_slver_%2%3%4:
dw 0x%4
db 0x%3, 0x%2
%endmacro
%endif ; ifndef _REG_SIZES_ASM_ %endif ; ifndef _REG_SIZES_ASM_

3
raid/pq_check_sse.asm
View File

@ -272,6 +272,3 @@ section .data
align 16 align 16
poly: poly:
dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d
;;; func core, ver, snum
slversion pq_check_sse, 00, 06, 0033

3
raid/pq_check_sse_i32.asm
View File

@ -277,6 +277,3 @@ section .data
align 16 align 16
poly: poly:
dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d
;;; func core, ver, snum
slversion pq_check_sse, 00, 06, 0033

3
raid/pq_gen_avx.asm
View File

@ -249,6 +249,3 @@ section .data
align 16 align 16
poly: poly:
dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d
;;; func core, ver, snum
slversion pq_gen_avx, 02, 0a, 0039

3
raid/pq_gen_avx2.asm
View File

@ -251,6 +251,3 @@ align 32
poly: poly:
dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d
dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d
;;; func core, ver, snum
slversion pq_gen_avx2, 04, 03, 0041

3
raid/pq_gen_sse.asm
View File

@ -253,6 +253,3 @@ section .data
align 16 align 16
poly: poly:
dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d
;;; func core, ver, snum
slversion pq_gen_sse, 00, 09, 0032

3
raid/pq_gen_sse_i32.asm
View File

@ -259,6 +259,3 @@ section .data
align 16 align 16
poly: poly:
dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d
;;; func core, ver, snum
slversion pq_gen_sse, 00, 08, 0032

18
raid/raid_base.c
View File

@ -139,21 +139,3 @@ int xor_check_base(int vects, int len, void **array)
return len; return len;
return fail; return fail;
} }
struct slver {
unsigned short snum;
unsigned char ver;
unsigned char core;
};
struct slver pq_gen_base_slver_0001012a;
struct slver pq_gen_base_slver = { 0x012a, 0x01, 0x00 };
struct slver xor_gen_base_slver_0001012b;
struct slver xor_gen_base_slver = { 0x012b, 0x01, 0x00 };
struct slver pq_check_base_slver_0001012c;
struct slver pq_check_base_slver = { 0x012c, 0x01, 0x00 };
struct slver xor_check_base_slver_0001012d;
struct slver xor_check_base_slver = { 0x012d, 0x01, 0x00 };

6
raid/raid_multibinary.asm
View File

@ -135,9 +135,3 @@ xor_check_dispatch_init:
pop rbx pop rbx
pop rax pop rax
ret ret
;;; func core, ver, snum
slversion xor_gen, 00, 03, 0126
slversion xor_check, 00, 03, 0127
slversion pq_gen, 00, 03, 0128
slversion pq_check, 00, 03, 0129

6
raid/xor_check_sse.asm
View File

@ -277,9 +277,3 @@ return_fail:
ret ret
endproc_frame endproc_frame
section .data
;;; func core, ver, snum
slversion xor_check_sse, 00, 03, 0031

6
raid/xor_gen_avx.asm
View File

@ -220,9 +220,3 @@ return_fail:
ret ret
endproc_frame endproc_frame
section .data
;;; func core, ver, snum
slversion xor_gen_avx, 02, 05, 0037

6
raid/xor_gen_sse.asm
View File

@ -276,9 +276,3 @@ return_fail:
ret ret
endproc_frame endproc_frame
section .data
;;; func core, ver, snum
slversion xor_gen_sse, 00, 0c, 0030