mirror of
https://github.com/intel/isa-l.git
synced 2024-12-12 17:33:50 +01:00
9f75defd57
The relic slver is no longer used for individual versioning on functions and is confusing tools looking for data in text sections. This removes all instances instead of fixing since its usefulness is waining. Fixes #221 Change-Id: Ife0b9f105950a90337c58e8a41ac2cffc0f67d99 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
298 lines
7.6 KiB
NASM
298 lines
7.6 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%ifndef _REG_SIZES_ASM_
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%define _REG_SIZES_ASM_
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%ifndef AS_FEATURE_LEVEL
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%define AS_FEATURE_LEVEL 4
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%endif
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%define EFLAGS_HAS_CPUID (1<<21)
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%define FLAG_CPUID1_ECX_CLMUL (1<<1)
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%define FLAG_CPUID1_EDX_SSE2 (1<<26)
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%define FLAG_CPUID1_ECX_SSE3 (1)
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%define FLAG_CPUID1_ECX_SSE4_1 (1<<19)
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%define FLAG_CPUID1_ECX_SSE4_2 (1<<20)
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%define FLAG_CPUID1_ECX_POPCNT (1<<23)
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%define FLAG_CPUID1_ECX_AESNI (1<<25)
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%define FLAG_CPUID1_ECX_OSXSAVE (1<<27)
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%define FLAG_CPUID1_ECX_AVX (1<<28)
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%define FLAG_CPUID1_EBX_AVX2 (1<<5)
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%define FLAG_CPUID7_EBX_AVX2 (1<<5)
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%define FLAG_CPUID7_EBX_AVX512F (1<<16)
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%define FLAG_CPUID7_EBX_AVX512DQ (1<<17)
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%define FLAG_CPUID7_EBX_AVX512IFMA (1<<21)
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%define FLAG_CPUID7_EBX_AVX512PF (1<<26)
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%define FLAG_CPUID7_EBX_AVX512ER (1<<27)
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%define FLAG_CPUID7_EBX_AVX512CD (1<<28)
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%define FLAG_CPUID7_EBX_AVX512BW (1<<30)
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%define FLAG_CPUID7_EBX_AVX512VL (1<<31)
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%define FLAG_CPUID7_ECX_AVX512VBMI (1<<1)
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%define FLAG_CPUID7_ECX_AVX512VBMI2 (1 << 6)
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%define FLAG_CPUID7_ECX_GFNI (1 << 8)
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%define FLAG_CPUID7_ECX_VAES (1 << 9)
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%define FLAG_CPUID7_ECX_VPCLMULQDQ (1 << 10)
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%define FLAG_CPUID7_ECX_VNNI (1 << 11)
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%define FLAG_CPUID7_ECX_BITALG (1 << 12)
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%define FLAG_CPUID7_ECX_VPOPCNTDQ (1 << 14)
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%define FLAGS_CPUID7_EBX_AVX512_G1 (FLAG_CPUID7_EBX_AVX512F | FLAG_CPUID7_EBX_AVX512VL | FLAG_CPUID7_EBX_AVX512BW | FLAG_CPUID7_EBX_AVX512CD | FLAG_CPUID7_EBX_AVX512DQ)
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%define FLAGS_CPUID7_ECX_AVX512_G2 (FLAG_CPUID7_ECX_AVX512VBMI2 | FLAG_CPUID7_ECX_GFNI | FLAG_CPUID7_ECX_VAES | FLAG_CPUID7_ECX_VPCLMULQDQ | FLAG_CPUID7_ECX_VNNI | FLAG_CPUID7_ECX_BITALG | FLAG_CPUID7_ECX_VPOPCNTDQ)
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%define FLAG_XGETBV_EAX_XMM (1<<1)
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%define FLAG_XGETBV_EAX_YMM (1<<2)
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%define FLAG_XGETBV_EAX_XMM_YMM 0x6
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%define FLAG_XGETBV_EAX_ZMM_OPM 0xe0
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%define FLAG_CPUID1_EAX_AVOTON 0x000406d0
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%define FLAG_CPUID1_EAX_STEP_MASK 0xfffffff0
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; define d and w variants for registers
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%define raxd eax
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%define raxw ax
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%define raxb al
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%define rbxd ebx
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%define rbxw bx
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%define rbxb bl
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%define rcxd ecx
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%define rcxw cx
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%define rcxb cl
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%define rdxd edx
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%define rdxw dx
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%define rdxb dl
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%define rsid esi
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%define rsiw si
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%define rsib sil
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%define rdid edi
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%define rdiw di
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%define rdib dil
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%define rbpd ebp
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%define rbpw bp
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%define rbpb bpl
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%define ymm0x xmm0
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%define ymm1x xmm1
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%define ymm2x xmm2
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%define ymm3x xmm3
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%define ymm4x xmm4
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%define ymm5x xmm5
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%define ymm6x xmm6
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%define ymm7x xmm7
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%define ymm8x xmm8
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%define ymm9x xmm9
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%define ymm10x xmm10
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%define ymm11x xmm11
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%define ymm12x xmm12
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%define ymm13x xmm13
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%define ymm14x xmm14
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%define ymm15x xmm15
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%define zmm0x xmm0
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%define zmm1x xmm1
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%define zmm2x xmm2
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%define zmm3x xmm3
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%define zmm4x xmm4
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%define zmm5x xmm5
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%define zmm6x xmm6
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%define zmm7x xmm7
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%define zmm8x xmm8
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%define zmm9x xmm9
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%define zmm10x xmm10
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%define zmm11x xmm11
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%define zmm12x xmm12
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%define zmm13x xmm13
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%define zmm14x xmm14
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%define zmm15x xmm15
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%define zmm16x xmm16
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%define zmm17x xmm17
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%define zmm18x xmm18
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%define zmm19x xmm19
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%define zmm20x xmm20
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%define zmm21x xmm21
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%define zmm22x xmm22
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%define zmm23x xmm23
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%define zmm24x xmm24
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%define zmm25x xmm25
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%define zmm26x xmm26
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%define zmm27x xmm27
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%define zmm28x xmm28
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%define zmm29x xmm29
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%define zmm30x xmm30
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%define zmm31x xmm31
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%define zmm0y ymm0
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%define zmm1y ymm1
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%define zmm2y ymm2
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%define zmm3y ymm3
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%define zmm4y ymm4
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%define zmm5y ymm5
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%define zmm6y ymm6
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%define zmm7y ymm7
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%define zmm8y ymm8
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%define zmm9y ymm9
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%define zmm10y ymm10
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%define zmm11y ymm11
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%define zmm12y ymm12
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%define zmm13y ymm13
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%define zmm14y ymm14
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%define zmm15y ymm15
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%define zmm16y ymm16
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%define zmm17y ymm17
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%define zmm18y ymm18
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%define zmm19y ymm19
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%define zmm20y ymm20
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%define zmm21y ymm21
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%define zmm22y ymm22
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%define zmm23y ymm23
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%define zmm24y ymm24
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%define zmm25y ymm25
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%define zmm26y ymm26
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%define zmm27y ymm27
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%define zmm28y ymm28
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%define zmm29y ymm29
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%define zmm30y ymm30
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%define zmm31y ymm31
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%define DWORD(reg) reg %+ d
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%define WORD(reg) reg %+ w
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%define BYTE(reg) reg %+ b
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%define XWORD(reg) reg %+ x
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%ifdef INTEL_CET_ENABLED
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%ifdef __NASM_VER__
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%if AS_FEATURE_LEVEL >= 10
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%ifidn __OUTPUT_FORMAT__,elf32
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section .note.gnu.property note alloc noexec align=4
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DD 0x00000004,0x0000000c,0x00000005,0x00554e47
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DD 0xc0000002,0x00000004,0x00000003
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%endif
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%ifidn __OUTPUT_FORMAT__,elf64
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section .note.gnu.property note alloc noexec align=8
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DD 0x00000004,0x00000010,0x00000005,0x00554e47
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DD 0xc0000002,0x00000004,0x00000003,0x00000000
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%endif
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%endif
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%endif
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%endif
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%ifidn __OUTPUT_FORMAT__,elf32
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section .note.GNU-stack noalloc noexec nowrite progbits
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section .text
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%endif
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%ifidn __OUTPUT_FORMAT__,elf64
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%define __x86_64__
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section .note.GNU-stack noalloc noexec nowrite progbits
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section .text
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%endif
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%ifidn __OUTPUT_FORMAT__,win64
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%define __x86_64__
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%endif
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%ifidn __OUTPUT_FORMAT__,macho64
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%define __x86_64__
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%endif
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%ifdef __x86_64__
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%define endbranch db 0xf3, 0x0f, 0x1e, 0xfa
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%else
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%define endbranch db 0xf3, 0x0f, 0x1e, 0xfb
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%endif
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%ifdef REL_TEXT
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%define WRT_OPT
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%elifidn __OUTPUT_FORMAT__, elf64
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%define WRT_OPT wrt ..plt
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%else
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%define WRT_OPT
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%endif
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%macro mk_global 1-3
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%ifdef __NASM_VER__
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%ifidn __OUTPUT_FORMAT__, macho64
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global %1
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%elifidn __OUTPUT_FORMAT__, win64
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global %1
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%else
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global %1:%2 %3
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%endif
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%else
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global %1:%2 %3
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%endif
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%endmacro
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; Fixes for nasm lack of MS proc helpers
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%ifdef __NASM_VER__
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%ifidn __OUTPUT_FORMAT__, win64
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%macro alloc_stack 1
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sub rsp, %1
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%endmacro
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%macro proc_frame 1
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%1:
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%endmacro
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%macro save_xmm128 2
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movdqa [rsp + %2], %1
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%endmacro
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%macro save_reg 2
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mov [rsp + %2], %1
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%endmacro
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%macro rex_push_reg 1
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push %1
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%endmacro
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%macro push_reg 1
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push %1
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%endmacro
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%define end_prolog
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%endif
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%define endproc_frame
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%endif
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%ifidn __OUTPUT_FORMAT__, macho64
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%define elf64 macho64
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mac_equ equ 1
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%endif
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%endif ; ifndef _REG_SIZES_ASM_
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