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Initial commit isa-l v2.14.1 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-10-22 23:54:34 +02:00
########################################################################
ec: add AVX512 ec functions with 5 and 6 outputs Added AVX512 optimized functions to calculate the GF(2^8) vector dot product with 5 and 6 outputs at a time. Also added GF(2^8) vector multiply AVX512 optimized functions with 5 and 6 accumulate. Change-Id: I6d2c080f4f4f8e4823ad9a9be2c65c3b5b3bb1f8 Signed-off-by: John Kariuki <John.K.Kariuki@intel.com>
2019-06-13 01:09:52 +02:00
# Copyright(c) 2011-2019 Intel Corporation All rights reserved.
Initial commit isa-l v2.14.1 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-10-22 23:54:34 +02:00
#
# Redistribution and use in source and binary forms, with or without
Format only patch from iindent and remove_whitespace Change-Id: I114bfcfa8750c7ba3a50ad2be9dd9e87cb7a1042 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-05-31 03:28:57 +02:00
# modification, are permitted provided that the following conditions
Initial commit isa-l v2.14.1 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-10-22 23:54:34 +02:00
# are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# * Neither the name of Intel Corporation nor the names of its
# contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
########################################################################
Implement aarch64 neon for erasure code. 1.Replace below erasure code interfaces to arm neon interface by mbin_interface function. ec_encode_data gf_vect_mul gf_vect_dot_prod gf_vect_mad ec_encode_data_update 2.Utilise arm neon instrution to accelerate GF(2^8) set compute by 128bit registor. Change-Id: Ib0ecbfbd1837d2b1f823d26815c896724d2d22e4 Signed-off-by: Zhou Xiong <zhouxiong13@huawei.com>
2019-10-25 03:18:08 +02:00
include erasure_code/aarch64/Makefile.am
enable VSX SIMD in ISA-L for ppc64le 1) Implement the ErasureCode function in Altivec Intrinsics 2) Coding style update Change-Id: I2c81d035f4083e9b011dbf3b741f628813b68606 Thanks-to: Daniel Axtens <dja@axtens.net> Signed-off-by: Hong Bo Peng <penghb@cn.ibm.com>
2020-02-20 04:47:53 +01:00
include erasure_code/ppc64le/Makefile.am
ec: Fixes for 32-bit build Change-Id: Iac362f0d7282716a8502afcec939b0d1877a943f Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-21 21:46:30 +01:00
lsrc += erasure_code/ec_base.c
ec: Group src by arch Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-07 00:09:44 +01:00
ec: Add base function aliases Change-Id: I36f1a7948e0009ca5f4f67437f4aa704e737a05a Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-20 23:35:42 +01:00
lsrc_base_aliases += erasure_code/ec_base_aliases.c
ec: Group src by arch Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-07 00:09:44 +01:00
lsrc_x86_64 += \
ec: Fixes for 32-bit build Change-Id: Iac362f0d7282716a8502afcec939b0d1877a943f Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-21 21:46:30 +01:00
erasure_code/ec_highlevel_func.c \
Initial commit isa-l v2.14.1 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-10-22 23:54:34 +02:00
erasure_code/gf_vect_mul_sse.asm \
erasure_code/gf_vect_mul_avx.asm \
erasure_code/gf_vect_dot_prod_sse.asm \
erasure_code/gf_vect_dot_prod_avx.asm \
erasure_code/gf_vect_dot_prod_avx2.asm \
erasure_code/gf_2vect_dot_prod_sse.asm \
erasure_code/gf_3vect_dot_prod_sse.asm \
erasure_code/gf_4vect_dot_prod_sse.asm \
erasure_code/gf_5vect_dot_prod_sse.asm \
erasure_code/gf_6vect_dot_prod_sse.asm \
erasure_code/gf_2vect_dot_prod_avx.asm \
erasure_code/gf_3vect_dot_prod_avx.asm \
erasure_code/gf_4vect_dot_prod_avx.asm \
erasure_code/gf_5vect_dot_prod_avx.asm \
erasure_code/gf_6vect_dot_prod_avx.asm \
erasure_code/gf_2vect_dot_prod_avx2.asm \
erasure_code/gf_3vect_dot_prod_avx2.asm \
erasure_code/gf_4vect_dot_prod_avx2.asm \
erasure_code/gf_5vect_dot_prod_avx2.asm \
erasure_code/gf_6vect_dot_prod_avx2.asm \
erasure_code/gf_vect_mad_sse.asm \
erasure_code/gf_2vect_mad_sse.asm \
erasure_code/gf_3vect_mad_sse.asm \
erasure_code/gf_4vect_mad_sse.asm \
erasure_code/gf_5vect_mad_sse.asm \
erasure_code/gf_6vect_mad_sse.asm \
erasure_code/gf_vect_mad_avx.asm \
erasure_code/gf_2vect_mad_avx.asm \
erasure_code/gf_3vect_mad_avx.asm \
erasure_code/gf_4vect_mad_avx.asm \
erasure_code/gf_5vect_mad_avx.asm \
erasure_code/gf_6vect_mad_avx.asm \
erasure_code/gf_vect_mad_avx2.asm \
erasure_code/gf_2vect_mad_avx2.asm \
erasure_code/gf_3vect_mad_avx2.asm \
erasure_code/gf_4vect_mad_avx2.asm \
erasure_code/gf_5vect_mad_avx2.asm \
erasure_code/gf_6vect_mad_avx2.asm \
erasure_code/ec_multibinary.asm
Add avx512 versions of ec_encode_data - Includes gf_nvect_dot_prod, gf_nvect_mad functions - Change ec multibinary to use common macros - Autoconf checks for nasm or yasm support and picks if available - Leave out compile of any avx512 code if assembler not available Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-11-18 23:40:52 +01:00
#if HAVE_AVX512
ec: Group src by arch Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-07 00:09:44 +01:00
lsrc_x86_64 += \
erasure_code: add AVX2 2vect mad with GFNI implementation Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-12-08 13:08:34 +01:00
erasure_code/gf_vect_mad_avx2_gfni.asm \
erasure_code/gf_2vect_mad_avx2_gfni.asm \
erasure_code: add AVX2 3vect mad with GFNI implementation Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-12-13 14:09:00 +01:00
erasure_code/gf_3vect_mad_avx2_gfni.asm \
erasure_code: add AVX2 4vect mad with GFNI implementation Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-12-13 15:27:35 +01:00
erasure_code/gf_4vect_mad_avx2_gfni.asm \
erasure_code: add AVX2 5vect mad with GFNI implementation Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-12-13 15:51:10 +01:00
erasure_code/gf_5vect_mad_avx2_gfni.asm \
ec: Group src by arch Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-07 00:09:44 +01:00
erasure_code/gf_vect_dot_prod_avx512.asm \
Add avx512 versions of ec_encode_data - Includes gf_nvect_dot_prod, gf_nvect_mad functions - Change ec multibinary to use common macros - Autoconf checks for nasm or yasm support and picks if available - Leave out compile of any avx512 code if assembler not available Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-11-18 23:40:52 +01:00
erasure_code/gf_2vect_dot_prod_avx512.asm \
erasure_code/gf_3vect_dot_prod_avx512.asm \
erasure_code/gf_4vect_dot_prod_avx512.asm \
ec: add AVX512 ec functions with 5 and 6 outputs Added AVX512 optimized functions to calculate the GF(2^8) vector dot product with 5 and 6 outputs at a time. Also added GF(2^8) vector multiply AVX512 optimized functions with 5 and 6 accumulate. Change-Id: I6d2c080f4f4f8e4823ad9a9be2c65c3b5b3bb1f8 Signed-off-by: John Kariuki <John.K.Kariuki@intel.com>
2019-06-13 01:09:52 +02:00
erasure_code/gf_5vect_dot_prod_avx512.asm \
erasure_code/gf_6vect_dot_prod_avx512.asm \
erasure_code: implement EC with AVX512 + GFNI Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-13 13:07:41 +01:00
erasure_code/gf_vect_dot_prod_avx512_gfni.asm \
erasure_code: add initial AVX2 dot product with GFNI implementation Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-11-28 19:20:16 +01:00
erasure_code/gf_vect_dot_prod_avx2_gfni.asm \
erasure_code: add 2 vector AVX2 dot product with GFNI implementation Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-12-06 23:21:33 +01:00
erasure_code/gf_2vect_dot_prod_avx2_gfni.asm \
erasure_code: add 3 vector AVX2 dot product with GFNI implementation Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
2023-12-05 20:39:13 +01:00
erasure_code/gf_3vect_dot_prod_avx2_gfni.asm \
erasure_code: implement EC with AVX512 + GFNI Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-13 13:07:41 +01:00
erasure_code/gf_2vect_dot_prod_avx512_gfni.asm \
erasure_code/gf_3vect_dot_prod_avx512_gfni.asm \
erasure_code/gf_4vect_dot_prod_avx512_gfni.asm \
erasure_code/gf_5vect_dot_prod_avx512_gfni.asm \
erasure_code/gf_6vect_dot_prod_avx512_gfni.asm \
Add avx512 versions of ec_encode_data - Includes gf_nvect_dot_prod, gf_nvect_mad functions - Change ec multibinary to use common macros - Autoconf checks for nasm or yasm support and picks if available - Leave out compile of any avx512 code if assembler not available Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-11-18 23:40:52 +01:00
erasure_code/gf_vect_mad_avx512.asm \
erasure_code/gf_2vect_mad_avx512.asm \
erasure_code/gf_3vect_mad_avx512.asm \
ec: add AVX512 ec functions with 5 and 6 outputs Added AVX512 optimized functions to calculate the GF(2^8) vector dot product with 5 and 6 outputs at a time. Also added GF(2^8) vector multiply AVX512 optimized functions with 5 and 6 accumulate. Change-Id: I6d2c080f4f4f8e4823ad9a9be2c65c3b5b3bb1f8 Signed-off-by: John Kariuki <John.K.Kariuki@intel.com>
2019-06-13 01:09:52 +02:00
erasure_code/gf_4vect_mad_avx512.asm \
erasure_code/gf_5vect_mad_avx512.asm \
erasure_code: implement EC update with AVX512 + GFNI Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-14 15:43:16 +01:00
erasure_code/gf_6vect_mad_avx512.asm \
erasure_code/gf_vect_mad_avx512_gfni.asm \
erasure_code/gf_2vect_mad_avx512_gfni.asm \
erasure_code/gf_3vect_mad_avx512_gfni.asm \
erasure_code/gf_4vect_mad_avx512_gfni.asm \
erasure_code/gf_5vect_mad_avx512_gfni.asm \
erasure_code/gf_6vect_mad_avx512_gfni.asm
Add avx512 versions of ec_encode_data - Includes gf_nvect_dot_prod, gf_nvect_mad functions - Change ec multibinary to use common macros - Autoconf checks for nasm or yasm support and picks if available - Leave out compile of any avx512 code if assembler not available Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-11-18 23:40:52 +01:00
ec: Group src by arch Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-07 00:09:44 +01:00
lsrc_x86_32 += \
ec: Fixes for 32-bit build Change-Id: Iac362f0d7282716a8502afcec939b0d1877a943f Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-03-21 21:46:30 +01:00
erasure_code/ec_highlevel_func.c \
Initial commit isa-l v2.14.1 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-10-22 23:54:34 +02:00
erasure_code/ec_multibinary.asm \
erasure_code/gf_vect_dot_prod_avx.asm \
erasure_code/gf_2vect_dot_prod_avx.asm \
erasure_code/gf_3vect_dot_prod_avx.asm \
erasure_code/gf_4vect_dot_prod_avx.asm \
erasure_code/gf_vect_dot_prod_sse.asm \
erasure_code/gf_2vect_dot_prod_sse.asm \
erasure_code/gf_3vect_dot_prod_sse.asm \
erasure_code/gf_4vect_dot_prod_sse.asm \
erasure_code/gf_vect_dot_prod_avx2.asm \
erasure_code/gf_2vect_dot_prod_avx2.asm \
erasure_code/gf_3vect_dot_prod_avx2.asm \
erasure_code/gf_4vect_dot_prod_avx2.asm
Add avx512 versions of ec_encode_data - Includes gf_nvect_dot_prod, gf_nvect_mad functions - Change ec multibinary to use common macros - Autoconf checks for nasm or yasm support and picks if available - Leave out compile of any avx512 code if assembler not available Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-11-18 23:40:52 +01:00
unit_tests32 += erasure_code/erasure_code_base_test \
Initial commit isa-l v2.14.1 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-10-22 23:54:34 +02:00
erasure_code/erasure_code_test \
erasure_code/gf_vect_mul_test \
erasure_code/gf_vect_mul_base_test \
erasure_code/gf_vect_dot_prod_base_test \
test: Remove redundant arch-specific tests Change-Id: Ifdbac9d8a99888bfd7a12da5d47dd07b8f85481d Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-11-22 00:54:53 +01:00
erasure_code/gf_vect_dot_prod_test
Initial commit isa-l v2.14.1 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-10-22 23:54:34 +02:00
perf_tests32 += erasure_code/gf_vect_mul_perf \
erasure_code/gf_vect_dot_prod_perf \
erasure_code/erasure_code_perf \
erasure_code/erasure_code_base_perf \
test: Remove redundant arch-specific tests Change-Id: Ifdbac9d8a99888bfd7a12da5d47dd07b8f85481d Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-11-22 00:54:53 +01:00
erasure_code/gf_vect_dot_prod_1tbl
Initial commit isa-l v2.14.1 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-10-22 23:54:34 +02:00
build: Fix an include path to be srcdir relative Allows configure to again build in an external directory. When building ISAL in an external path, assembler or compiler needs relative include paths. Signed-off-by: Xiaodong Liu <xiaodong.liu@intel.com> Reviewed-by: Greg Tucker <greg.b.tucker@intel.com>
2016-07-11 10:25:18 +02:00
src_include += -I $(srcdir)/erasure_code
Initial commit isa-l v2.14.1 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-10-22 23:54:34 +02:00
extern_hdrs += include/erasure_code.h \
include/gf_vect_mul.h
other_src += erasure_code/ec_base.h \
Add avx512 versions of ec_encode_data - Includes gf_nvect_dot_prod, gf_nvect_mad functions - Change ec multibinary to use common macros - Autoconf checks for nasm or yasm support and picks if available - Leave out compile of any avx512 code if assembler not available Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-11-18 23:40:52 +01:00
include/multibinary.asm \
Initial commit isa-l v2.14.1 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-10-22 23:54:34 +02:00
include/reg_sizes.asm
check_tests += erasure_code/gf_vect_mul_test \
erasure_code/erasure_code_test \
erasure_code/gf_inverse_test \
erasure_code/erasure_code_update_test
test: Remove redundant arch-specific tests Change-Id: Ifdbac9d8a99888bfd7a12da5d47dd07b8f85481d Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-11-22 00:54:53 +01:00
unit_tests += \
Initial commit isa-l v2.14.1 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-10-22 23:54:34 +02:00
erasure_code/gf_vect_mul_base_test \
erasure_code/gf_vect_dot_prod_base_test \
erasure_code/gf_vect_dot_prod_test \
erasure_code/gf_vect_mad_test \
test: Remove redundant arch-specific tests Change-Id: Ifdbac9d8a99888bfd7a12da5d47dd07b8f85481d Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2017-11-22 00:54:53 +01:00
erasure_code/erasure_code_base_test
Initial commit isa-l v2.14.1 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2015-10-22 23:54:34 +02:00
perf_tests += erasure_code/gf_vect_mul_perf \
erasure_code/gf_vect_dot_prod_perf \
erasure_code/gf_vect_dot_prod_1tbl \
erasure_code/erasure_code_perf \
erasure_code/erasure_code_base_perf \
erasure_code/erasure_code_update_perf
aarch64: Cleanup build issues This patch addresses one build failure and fixes several build warnings for Arm (some for x86 too). - Fix dynamic relocation link failure of ld.bfd 2.30 on Arm [log] relocation R_AARCH64_ADR_PREL_PG_HI21 against symbol `xor_gen_neon' which may bind externally can not be used when making a shared object - Add arch dependent "other_tests" to exclude x86 specific tests on Arm [log] isa-l/erasure_code/gf_2vect_dot_prod_sse_test.c:181: undefined reference to `gf_2vect_dot_prod_sse' - Check "fread" return value to fix gcc warnings on Arm and x86 [log] warning: ignoring return value of ‘fread’, declared with attribute warn_unused_result [-Wunused-result] fread(in_buf, 1, in_size, in_file); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - Fix issue of comparing "char" with "int" on Arm. "char" is unsigned on Arm by default, an unsigned char will never equal to EOF(-1). [Log] programs/igzip_cli.c:318:31: warning: comparison is always true due to limited range of data type [-Wtype-limits] while (tmp != '\n' && tmp != EOF) ^~ - Include <stdlib.h> to several files to fix build warnings on Arm [log] igzip/igzip_inflate_perf.c:339:5: warning: incompatible implicit declaration of built-in function ‘exit’ exit(0); ^~~~ Change-Id: I82c1b63316b634b3d398ffba2ff815679d9051a8 Signed-off-by: Yibo Cai <yibo.cai@arm.com>
2019-03-13 03:43:23 +01:00
other_tests += erasure_code/gen_rs_matrix_limits
build: Remove unneeded file types.h The file types.h has long been misnamed and overlaps with functionality in the test helper routines. Change-Id: I774047d3a0074198b67a6b4e909f1e2ce1938195 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2021-06-10 01:25:30 +02:00
other_src += include/test.h
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