1. no longer use the register names directly and optimized code format
2. to be compatible with O32, specify type of address variable with mips_reg and handle the address variable with PTR_ operator
3. ff_pred16x16_plane_ functions only support N64 ABI now
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
1.the codes are compatible with O32 ABI
2.use uld and mtc1 to workaround cpu 3A2000 gslwlc1 bug (gslwlc1 instruction extension bug in O32 ABI)
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
1. no longer use the register names directly and optimized code format
2. to be compatible with O32, specify type of address variable with mips_reg and handle the address variable with PTR_ operator
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
1. no longer use the register names directly and optimized code format
2. to be compatible with O32, specify type of address variable with mips_reg and handle the address variable with PTR_ operator
3. use uld and mtc1 to workaround cpu 3A2000 gslwlc1 bug (gslwlc1 instruction extension bug in O32 ABI)
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
Values for unsupported frequencies > 48000 Hz are still included (parser
will make use of them).
Also convert sampling frequencies array to unsigned.
Signed-off-by: James Almer <jamrial@gmail.com>
Move this from separate structure field to a packet flag.
Behavior should be equivalent, except that residual flag is now properly
cleared when packet has no core frame at all.
Also print a message when forcing recovery mode due to invalid residual
to make debugging easier.
Signed-off-by: James Almer <jamrial@gmail.com>
Parse core frame size directly when searching for frame end instead of
using value extracted from previous frame.
Account for unused bits when calculating sync word distance for 14-bit
streams to avoid alias sync detection.
Parse EXSS frame size and skip over EXSS frame to avoid alias sync
detection.
Signed-off-by: James Almer <jamrial@gmail.com>
For reasons we are not privy to, nvidia decided that the nvenc encoder
should apply aspect ratio compensation to 'DVD like' content, assuming that
the content is not BT.601 compliant, but needs to be BT.601 compliant. In
this context, that means that they make the following, questionable,
assumptions:
1) If the input dimensions are 720x480 or 720x576, assume the content has
an active area of 704x480 or 704x576.
2) Assume that whatever the input sample aspect ratio is, it does not account
for the difference between 'physical' and 'active' dimensions.
From these assumptions, they then conclude that they can 'help', by adjusting
the sample aspect ratio by a factor of 45/44. And indeed, if you wanted to
display only the 704 wide active area with the same aspect ratio as the full
720 wide image - this would be the correct adjustment factor, but what if you
don't? And more importantly, what if you're used to lavc not making this kind
of adjustment at encode time - because none of the other encoders do this!
And, what if you had already accounted for BT.601 and your input had the
correct attributes? Well, it's going to apply the compensation anyway!
So, if you take some content, and feed it through nvenc repeatedly, it
will keep scaling the aspect ratio every time, stretching your video out
more and more and more.
So, clearly, regardless of whether you want to apply bt.601 aspect ratio
adjustments or not, this is not the way to do it. With any other lavc
encoder, you would do it as part of defining your input parameters or do
the adjustment at playback time, and there's no reason by nvenc should
be any different.
This change adds some logic to undo the compensation that nvenc would
otherwise do.
nvidia engineers have told us that they will work to make this
compensation mechanism optional in a future release of the nvenc
SDK. At that point, we can adapt accordingly.
Signed-off-by: Philip Langdale <philipl@overt.org>
Reviewed-by: Timo Rothenpieler <timo@rothenpieler.org>
Signed-off-by: Anton Khirnov <anton@khirnov.net>
The code needs only a few definitions from cuda.h, so define them
directly when CUDA is not enabled. CUDA is still required for accepting
HW frames as input.
Based on the code by Timo Rothenpieler <timo@rothenpieler.org>.
For some unknown reason enabling these causes proper CBR padding,
so as there are no known downsides just always enable them in CBR mode.
Signed-off-by: Anton Khirnov <anton@khirnov.net>
There is no real advantage to listing some codecs or subsystems
separately simply because they are somehow "hw-accelerated", on the
contrary it makes them harder to find than in a plain alphabetically
ordered list.
* commit '71d3305c2711d4f6ec8b92db09ff64cf4e19a58e':
h264_parse: make sure the ref count is zeroed on all failure paths
Merged-by: Derek Buitenhuis <derek.buitenhuis@gmail.com>
* commit 'a6e27f7add2698fdd89911632b570c3d0c3f2aaa':
h264: factor out parsing the reference count into a separate file
Merged-by: Derek Buitenhuis <derek.buitenhuis@gmail.com>
* commit '8d0cc8ca97678f4ca87948ebabcbaab5a4f4c1f6':
h264_parser: switch to h2645_parse for NAL unescaping
Merged-by: Hendrik Leppkes <h.leppkes@gmail.com>
Some streams contain an additional AnnexB NAL inside the mp4/nalff NALU.
This commonly occurs in interlaced streams where both fields are packed
into the same MP4 NAL with an AnnexB startcode in between.
Port handling of this format from the previous h264 nal handling.
Fixes trac #5529
Use the newly created vlc.h directly instead of including get_bits when needed.
The VLC and RL_VLC_ELEM structures are independent from the bitreader.
Signed-off-by: Luca Barbato <lu_zero@gentoo.org>
1. no longer use the register names directly and optimized code format
2. to be compatible with O32, specify type of address variable with mips_reg and handle the address variable with PTR_ operator
3. optimize some unaligned loads and stores
4. use uld and mtc1 to workaround cpu 3A2000 gslwlc1 bug (gslwlc1 instruction extension bug in O32 ABI)
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
