mathops: mips: Correctly enable loongson-specific assembly
The code wrongly assumed that the instructions used are supported on mips64, while it is supported only on loongson cpus.
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@ -28,28 +28,7 @@
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#if HAVE_INLINE_ASM
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#if HAVE_LOONGSON
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static inline av_const int64_t MAC64(int64_t d, int a, int b)
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{
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int64_t m;
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__asm__ ("dmult.g %1, %2, %3 \n\t"
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"daddu %0, %0, %1 \n\t"
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: "+r"(d), "=&r"(m) : "r"(a), "r"(b));
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return d;
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}
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#define MAC64(d, a, b) ((d) = MAC64(d, a, b))
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static inline av_const int64_t MLS64(int64_t d, int a, int b)
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{
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int64_t m;
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__asm__ ("dmult.g %1, %2, %3 \n\t"
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"dsubu %0, %0, %1 \n\t"
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: "+r"(d), "=&r"(m) : "r"(a), "r"(b));
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return d;
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}
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#define MLS64(d, a, b) ((d) = MLS64(d, a, b))
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#elif ARCH_MIPS64
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#if ARCH_MIPS64
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static inline av_const int64_t MAC64(int64_t d, int a, int b)
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{
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@ -75,8 +54,32 @@ static inline av_const int64_t MLS64(int64_t d, int a, int b)
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}
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#define MLS64(d, a, b) ((d) = MLS64(d, a, b))
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#else
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static inline av_const int64_t MAC64(int64_t d, int a, int b)
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{
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int64_t m;
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__asm__ ("dmult.g %1, %2, %3 \n\t"
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"daddu %0, %0, %1 \n\t"
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: "+r"(d), "=&r"(m) : "r"(a), "r"(b));
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return d;
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}
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#define MAC64(d, a, b) ((d) = MAC64(d, a, b))
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static inline av_const int64_t MLS64(int64_t d, int a, int b)
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{
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int64_t m;
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__asm__ ("dmult.g %1, %2, %3 \n\t"
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"dsubu %0, %0, %1 \n\t"
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: "+r"(d), "=&r"(m) : "r"(a), "r"(b));
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return d;
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}
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#define MLS64(d, a, b) ((d) = MLS64(d, a, b))
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#endif
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#endif /* HAVE_LOONGSON */
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#endif /* HAVE_INLINE_ASM */
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#endif /* AVCODEC_MIPS_MATHOPS_H */
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