Merge commit '637606de2d2e0af0a9fa2f23f943765d7d7c5cd5'
* commit '637606de2d2e0af0a9fa2f23f943765d7d7c5cd5': configure: arm: make _inline arch ext symbols depend on inline_asm arm: use HAVE*_INLINE/EXTERNAL macros for conditional compilation Conflicts: configure libavcodec/arm/dca.h Merged-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
commit
89c8eaa321
2
configure
vendored
2
configure
vendored
@ -1555,6 +1555,8 @@ armvfp_deps="arm"
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neon_deps="arm"
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vfpv3_deps="armvfp"
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map 'eval ${v}_inline_deps=inline_asm' $ARCH_EXT_LIST_ARM
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mipsfpu_deps="mips"
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mips32r2_deps="mips"
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mipsdspr1_deps="mips"
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@ -23,7 +23,7 @@
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#include "config.h"
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#if HAVE_NEON && HAVE_INLINE_ASM
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#if HAVE_NEON_INLINE
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#define VMUL2 VMUL2
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static inline float *VMUL2(float *dst, const float *v, unsigned idx,
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@ -138,6 +138,6 @@ static inline float *VMUL4S(float *dst, const float *v, unsigned idx,
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return dst;
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}
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#endif /* HAVE_NEON && HAVE_INLINE_ASM */
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#endif /* HAVE_NEON_INLINE */
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#endif /* AVCODEC_ARM_AAC_H */
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@ -25,7 +25,7 @@
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#include "config.h"
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#include "libavutil/intmath.h"
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#if HAVE_ARMV6 && HAVE_INLINE_ASM && AV_GCC_VERSION_AT_LEAST(4,4) && !CONFIG_THUMB
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#if HAVE_ARMV6_INLINE && AV_GCC_VERSION_AT_LEAST(4,4) && !CONFIG_THUMB
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#define decode_blockcodes decode_blockcodes
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static inline int decode_blockcodes(int code1, int code2, int levels,
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@ -79,7 +79,7 @@ static inline int decode_blockcodes(int code1, int code2, int levels,
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#endif
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#if HAVE_NEON && HAVE_INLINE_ASM && HAVE_ASM_MOD_Y
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#if HAVE_NEON_INLINE && HAVE_ASM_MOD_Y
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#define int8x8_fmul_int32 int8x8_fmul_int32
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static inline void int8x8_fmul_int32(float *dst, const int8_t *src, int scale)
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@ -22,7 +22,7 @@
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#include "config.h"
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#include "libavutil/arm/asm.S"
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#if HAVE_ARMV5TE
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#if HAVE_ARMV5TE_EXTERNAL
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function ff_prefetch_arm, export=1
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subs r2, r2, #1
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pld [r0]
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@ -28,7 +28,7 @@
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#if HAVE_INLINE_ASM
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#if HAVE_ARMV6
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#if HAVE_ARMV6_INLINE
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#define MULH MULH
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static inline av_const int MULH(int a, int b)
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{
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@ -50,7 +50,7 @@ static av_always_inline av_const int FASTDIV(int a, int b)
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return r;
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}
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#else /* HAVE_ARMV6 */
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#else /* HAVE_ARMV6_INLINE */
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#define FASTDIV FASTDIV
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static av_always_inline av_const int FASTDIV(int a, int b)
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@ -64,7 +64,7 @@ static av_always_inline av_const int FASTDIV(int a, int b)
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#define MLS64(d, a, b) MAC64(d, -(a), b)
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#if HAVE_ARMV5TE
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#if HAVE_ARMV5TE_INLINE
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/* signed 16x16 -> 32 multiply add accumulate */
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# define MAC16(rt, ra, rb) \
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@ -37,7 +37,7 @@
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# define U(x)
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#endif
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#if HAVE_ARMV6 && HAVE_INLINE_ASM
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#if HAVE_ARMV6_INLINE
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#define vp56_rac_get_prob vp56_rac_get_prob_armv6
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static inline int vp56_rac_get_prob_armv6(VP56RangeCoder *c, int pr)
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@ -21,7 +21,7 @@
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#include "config.h"
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#if HAVE_ARMV6
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#if HAVE_ARMV6_EXTERNAL
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#define decode_block_coeffs_internal ff_decode_block_coeffs_armv6
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int ff_decode_block_coeffs_armv6(VP56RangeCoder *rc, DCTELEM block[16],
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uint8_t probs[8][3][NUM_DCT_TOKENS-1],
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@ -118,7 +118,7 @@ function ff_vp8_luma_dc_wht_armv6, export=1
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usub16 r4, r4, r6 @ block[0,1][3]
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usub16 r5, r5, r12 @ block[2,3][3]
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#if HAVE_ARMV6T2
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#if HAVE_ARMV6T2_EXTERNAL
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sbfx r6, r8, #3, #13
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sbfx r12, r7, #3, #13
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sbfx r1, r9, #3, #13
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@ -151,7 +151,7 @@ function ff_vp8_luma_dc_wht_armv6, export=1
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strh r4, [r0], #32
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asr r10, r5, #19 @ block[3][3]
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#if HAVE_ARMV6T2
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#if HAVE_ARMV6T2_EXTERNAL
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sbfx r2, r2, #3, #13
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sbfx lr, lr, #3, #13
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sbfx r3, r3, #3, #13
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@ -284,7 +284,7 @@ function ff_vp8_idct_add_armv6, export=1
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sxth r12, r12
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ldr r9, [r0, r2]
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sxth r1, r1
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#if HAVE_ARMV6T2
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#if HAVE_ARMV6T2_EXTERNAL
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sbfx r7, r7, #3, #13
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sbfx r10, r10, #3, #13
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#else
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@ -89,7 +89,7 @@ ELF .size \name, . - \name
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\name:
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.endm
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#if !HAVE_ARMV6T2
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#if !HAVE_ARMV6T2_EXTERNAL
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.macro movw rd, val
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mov \rd, \val & 255
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orr \rd, \val & ~255
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@ -97,7 +97,7 @@ ELF .size \name, . - \name
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#endif
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.macro mov32 rd, val
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#if HAVE_ARMV6T2
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#if HAVE_ARMV6T2_EXTERNAL
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movw \rd, #(\val) & 0xffff
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.if (\val) >> 16
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movt \rd, #(\val) >> 16
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@ -146,7 +146,7 @@ T ldr \rd, [\rd]
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.macro movrel rd, val
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#if CONFIG_PIC
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ldpic \rd, \val
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#elif HAVE_ARMV6T2 && !defined(__APPLE__)
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#elif HAVE_ARMV6T2_EXTERNAL && !defined(__APPLE__)
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movw \rd, #:lower16:\val
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movt \rd, #:upper16:\val
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#else
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@ -35,7 +35,7 @@ static av_always_inline av_const uint32_t av_bswap32(uint32_t x)
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#elif HAVE_INLINE_ASM
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#if HAVE_ARMV6
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#if HAVE_ARMV6_INLINE
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#define av_bswap16 av_bswap16
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static av_always_inline av_const unsigned av_bswap16(unsigned x)
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{
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@ -48,7 +48,7 @@ static av_always_inline av_const unsigned av_bswap16(unsigned x)
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#define av_bswap32 av_bswap32
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static av_always_inline av_const uint32_t av_bswap32(uint32_t x)
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{
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#if HAVE_ARMV6
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#if HAVE_ARMV6_INLINE
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__asm__("rev %0, %0" : "+r"(x));
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#else
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uint32_t t;
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@ -57,7 +57,7 @@ static av_always_inline av_const uint32_t av_bswap32(uint32_t x)
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"mov %0, %0, ror #8 \n\t"
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"eor %0, %0, %1, lsr #8 \n\t"
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: "+r"(x), "=&r"(t));
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#endif /* HAVE_ARMV6 */
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#endif /* HAVE_ARMV6_INLINE */
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return x;
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}
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#endif /* !AV_GCC_VERSION_AT_LEAST(4,5) */
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#if HAVE_INLINE_ASM
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#if HAVE_ARMV6
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#if HAVE_ARMV6_INLINE
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#define av_clip_uint8 av_clip_uint8_arm
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static av_always_inline av_const unsigned av_clip_uint8_arm(int a)
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@ -86,7 +86,7 @@ static av_always_inline int av_sat_dadd32_arm(int a, int b)
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return r;
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}
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#endif /* HAVE_ARMV6 */
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#endif /* HAVE_ARMV6_INLINE */
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#if HAVE_ASM_MOD_Q
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