c86950cb3f
Save and restore floating point registers via 64-bit load/stores when possible. Use assembler's builtin macro ops to generate pairs of 32-bit load/stores on Mips I cpus. Some cpus or FR modes have only 16 even-numbered dp fp regs. This is exposed by _MIPS_FPSET, defined by existing compilers. (cherry picked from commit dd37251c473e1483faba0fd5aaf30e7a55582e8a) Change-Id: Ibd43653701a363a77af85121d3cbd229d132a06a