Currently the dlmalloc allocates the memory with 8-byte alignment.
According to the com.aurorasoftworks.quadrant.ui.professional benchmark data:
We can get much better memory performance if we change it to be 16-byte aligned.
For example, On Nexus-S:
8-byte aligned :
1378 1070 1142 1665 1765 1163 1179 1263 1404 avg: 1336.555555556
16-byte aligned:
1691 1731 1780 1691 1671 1678 1802 1758 1780 avg: 1731.333333333
gain: 29.53%
That patch provides flexibity to customize the MALLOC_ALIGNMENT from the
board config.The macro MALLOC_ALIGNMENT defaults to 8.
To change it, please define BOARD_MALLOC_ALIGNMENT in the BoardConfig.mk:
BOARD_MALLOC_ALIGNMENT := <whatever>
Change-Id: I8da0376944a0bbcef1d0fc026bfb6d9125db9739
Signed-off-by: Jin Wei <wei.a.jin@intel.com>
Signed-off-by: Jack Ren <jack.ren@intel.com>
Signed-off-by: Beare, Bruce J <bruce.j.beare@intel.com>
So that we can always get the full stack trace regardless of gcc's handling
of the "noreturn" attribute associated with abort().
(Cherry pick of Id264a5167e7cabbf11515fbc48f5469c527e34d4.)
Bug: 6455193
Conflicts:
libc/Android.mk
Change-Id: I568fc5303fd1d747075ca933355f914122f94dac
ARM Cortex A8 use 64 bytes and ARM Cortex A9 use 32 bytes cache line
size.
The following patch:
Adds code to adjust memcpy cache line size to match A9 cache line
size.
Adds a flag to select between 32 bytes and 64 bytes cache line
size.
Copyright (C) ST-Ericsson SA 2010
Modified neon implementation to fit Cortex A9 cache line size
Author: Henrik Smiding henrik.smiding@stericsson.com for
ST-Ericsson.
Change-Id: I8a55946bfb074e6ec0a14805ed65f73fcd0984a3
Signed-off-by: Christian Bejram <christian.bejram@stericsson.com>
We don't have a toolchain anymore, we don't have working original
kernel headers, and nobody is maintaining this so there is really
no point in keeping this here. Details of the patch:
- removed code paths from Android.mk files related to the SuperH
architecture ("sh")
- removed libc/arch-sh, linker/arch-sh, libc/kernel/arch-sh
- simplified libc/SYSCALLS.TXT
- simplified the scripts in libc/tools/ and libc/kernel/tools
Change-Id: I26b0e1422bdc347489e4573e2fbec0e402f75560
Signed-off-by: David 'Digit' Turner <digit@android.com>
* commit '6b6ebeca985fb3843b56b507ac4ac1be44080a9c':
enable support for large files (> 2G)
Enable functional DSO object destruction
x86: Enable -fstack-protector
Update X86 Bionic CRT files for unwind/exceptions
bionic, libthread_db x86 fixes
Updated gcc 4.4.3 IA toolchain doesn't require the .ctors list
Remove an extra register move.
Replace __atomic_XXX with GCC __sync_XXX intrinsics.
move some typedefs to procfs.h required by gdbserver build
use consistent guards for off_t and size_t defines for IA
Simplify variable typing for IA builds
sigsetmask.c was not processing the "mask" argument.
Add defines for CAIF support
Remove extra/unneeded copy of fenv.h
Use proper variable typing
Update ATOM string routines to latest
Fix undefined reference to dl_iterate_phdr for x86
Fix missing NL
ptrace.c Fix source file format to unix from dos
* commit '3a13102637c8be53edf28f96598ac11aaa3e14df':
enable support for large files (> 2G)
Enable functional DSO object destruction
x86: Enable -fstack-protector
Update X86 Bionic CRT files for unwind/exceptions
bionic, libthread_db x86 fixes
Updated gcc 4.4.3 IA toolchain doesn't require the .ctors list
Remove an extra register move.
Replace __atomic_XXX with GCC __sync_XXX intrinsics.
move some typedefs to procfs.h required by gdbserver build
use consistent guards for off_t and size_t defines for IA
Simplify variable typing for IA builds
sigsetmask.c was not processing the "mask" argument.
Add defines for CAIF support
Remove extra/unneeded copy of fenv.h
Use proper variable typing
Update ATOM string routines to latest
Fix undefined reference to dl_iterate_phdr for x86
Fix missing NL
ptrace.c Fix source file format to unix from dos
Unfortunately, legacy .so files for ARM don't have a correct crtbegin file.
Consequently, we have to grandfather the old __dso_handle behaviour.
Add some ifdefs for ARM to allow it to use the old code until we can work
out a transition.
Change-Id: I6a28f368267d792c94e1d985d8344023bc632f6f
Author: H.J. Lu <hongjiu.lu@intel.com>
Signed-off-by: Bruce Beare <bruce.j.beare@intel.com>
libcutils/mspace.c includes libc/bionic/dlmalloc.c, we need to
take care of the fact that any internal C library function cannot
be used from it.
Change-Id: I0bc81ae090b7ac2d464f26b97fc6b94a08cdad9c
The latest merge conflict resolution worked only for ARM, but not for x86
Both ARM and x86 builds have been tested with this fix.
Change-Id: I4ec1f1b0ea32fa86e7e2515b221133473d6550a3
NOTE: Care has been taken to not change the compiler flags for ARM builds.
In particular, when building crtbegin_so.so, the -fPIC flag is only
used for x86 (previous reports indicate that it breaks the ARM
build at runtime for obscure reasons).
Unfortunately, legacy .so files for ARM don't have a correct crtbegin file.
Consequently, we have to grandfather the old __dso_handle behaviour.
Add some ifdefs for ARM to allow it to use the old code until we can work
out a transition.
Change-Id: I6a28f368267d792c94e1d985d8344023bc632f6f
Author: H.J. Lu <hongjiu.lu@intel.com>
Signed-off-by: Bruce Beare <bruce.j.beare@intel.com>
Reference results of the experiments on TI OMAP3430 at 600 MHz
$ bench_strcmp -N "strcmp_1k" -s 1k -I 200
[original C code]
prc thr usecs/call samples errors cnt/samp size
strcmp_1k 1 1 10.38000 102 0 15000 1024
[ARM optimized code]
prc thr usecs/call samples errors cnt/samp size
strcmp_1k 1 1 3.08840 88 0 15000 1024
The work was derived from ARM Ltd, contributed to newlib, and reworked
for Android by Linaro.
Change-Id: Ib0d5755e1eb9adb07d80ef0252f57a5c4c57a425
Signed-off-by: Jim Huang <jserv@0xlab.org>
Added a memmove() variant for Dalvik's System.arraycopy()
implementation. It guarantees 16-bit or 32-bit atomicity depending
on the alignment of the arguments.
Bug 3398352
Change-Id: Ie7bd246305ef0ff8290513663327c5b81680368d
It adds two functions sigsetjmp and siglongjmp
that fix compiling errors in bluetooth and mksh.
Copy directly from sigsetjmp.S of OpenBSD.
Change-Id: I4696f82ee6f85d1c93cbdd3c9e40f4917d50f3a6
This patch improves the handling of 64-bit parameters in syscalls on ARM.
The ARM EABI mandates that 64-bit quantities be passed in even/odd register
pairs, which requires special treatment.
This allows us to simplify our implementations of pread() and pwrite()
and remove the C stubs for pread64() and pwrite64().
Also add ftruncate64() to <unistd.h>
Change-Id: I407e2fd223ba0093dd2d0b04c6152fadfc9ce3ef
Bug 3107933
This adds the cpu_set_t type definition and related functions
and macros used to handle CPU thread affinity.
sched_getcpu()
sched_setaffinity()
sched_getaffinity()
Change-Id: If382ecafde8926341a88478062b275553645065b
64-bit pread() and pwrite() is needed for ZipFileRO to be able to read
ludicrously large ZIP files just in case someone is crazy enough to do
it.
Also fix a license header that was apparently mangled.
Change-Id: I6819ef8b36e46b63b40749c95717b1ecf9307033
Originally, there are _rand48 (in libc/bionic/_rand48.c) and __rand48
(in libc/stdlib/_rand48.c) implemented in bionic. Besides the naming,
the functionality is identical. This patch removes the duplicated
_rand48. Also, drand48 and erand48 are modified accordingly.
Change-Id: Ie5761a0a97f45df8538222a77edacb7c3e0125d7
Merge commit '6bf08d131f4109088b7fa1e53196513636c49e9b'
* commit '6bf08d131f4109088b7fa1e53196513636c49e9b':
Move the atom optimization flags into TARGET_linux-x86.mk.
Merge commit '3558834c565bbfe96dfcf233373c3814b4655347' into gingerbread-plus-aosp
* commit '3558834c565bbfe96dfcf233373c3814b4655347':
Move the atom optimization flags into TARGET_linux-x86.mk.
