Merge "Remove __ARM_HAVE_VFP."
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commit
a18af83bc1
@ -59,14 +59,12 @@ ENTRY(_setjmp)
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add r1, r0, #(_JB_CORE_BASE * 4)
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stmia r1, {r4-r14}
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#ifdef __ARM_HAVE_VFP
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/* Store floating-point registers */
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add r1, r0, #(_JB_FLOAT_BASE * 4)
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vstmia r1, {d8-d15}
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/* Store floating-point state */
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fmrx r1, fpscr
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str r1, [r0, #(_JB_FLOAT_STATE * 4)]
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#endif /* __ARM_HAVE_VFP */
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mov r0, #0x00000000
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bx lr
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@ -81,14 +79,12 @@ ENTRY(_longjmp)
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teq r2, r3
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bne botch
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#ifdef __ARM_HAVE_VFP
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/* Restore floating-point registers */
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add r2, r0, #(_JB_FLOAT_BASE * 4)
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vldmia r2, {d8-d15}
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/* Restore floating-point state */
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ldr r2, [r0, #(_JB_FLOAT_STATE * 4)]
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fmxr fpscr, r2
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#endif /* __ARM_HAVE_VFP */
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/* Restore core registers */
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add r2, r0, #(_JB_CORE_BASE * 4)
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@ -72,14 +72,12 @@ ENTRY(setjmp)
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add r1, r0, #(_JB_CORE_BASE * 4)
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stmia r1, {r4-r14}
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#ifdef __ARM_HAVE_VFP
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/* Store floating-point registers */
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add r1, r0, #(_JB_FLOAT_BASE * 4)
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vstmia r1, {d8-d15}
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/* Store floating-point state */
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fmrx r1, fpscr
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str r1, [r0, #(_JB_FLOAT_STATE * 4)]
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#endif /* __ARM_HAVE_VFP */
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mov r0, #0x00000000
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bx lr
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@ -115,14 +113,12 @@ ENTRY(longjmp)
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ldmfd sp!, {r0, r1, r14}
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.cfi_def_cfa_offset 0
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#ifdef __ARM_HAVE_VFP
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/* Restore floating-point registers */
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add r2, r0, #(_JB_FLOAT_BASE * 4)
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vldmia r2, {d8-d15}
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/* Restore floating-point state */
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ldr r2, [r0, #(_JB_FLOAT_STATE * 4)]
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fmxr fpscr, r2
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#endif /* __ARM_HAVE_VFP */
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/* Restore core registers */
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add r2, r0, #(_JB_CORE_BASE * 4)
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@ -139,11 +135,7 @@ ENTRY(longjmp)
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teq r0, #0x00000000
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moveq r0, #0x00000001
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bx lr
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#ifdef __ARM_26__
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mov r15, r14
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#else
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mov r15, r14
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#endif
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/* validation failed, die die die. */
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botch:
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@ -53,12 +53,6 @@
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# endif
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#endif
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/* define _ARM_HAVE_VFP if we have VFPv3
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*/
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#if __ARM_ARCH__ >= 7 && defined __VFP_FP__
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# define __ARM_HAVE_VFP
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#endif
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/* define _ARM_HAVE_NEON for ARMv7 architecture if we support the
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* Neon SIMD instruction set extensions. This also implies
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* that VFPv3-D32 is supported.
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