Merge "Clean up the ARM fenv.h, moving implementation details into fenv.c."
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8c054c51c3
@ -28,10 +28,11 @@
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#include <fenv.h>
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/*
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* Hopefully the system ID byte is immutable, so it's valid to use
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* this as a default environment.
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*/
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#define FPSCR_ENABLE_SHIFT 8
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#define FPSCR_ENABLE_MASK (FE_ALL_EXCEPT << FPSCR_ENABLE_SHIFT)
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#define FPSCR_RMODE_SHIFT 22
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const fenv_t __fe_dfl_env = 0;
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int fegetenv(fenv_t* __envp) {
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@ -86,14 +87,14 @@ int fetestexcept(int __excepts) {
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int fegetround(void) {
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fenv_t _fpscr;
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fegetenv(&_fpscr);
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return ((_fpscr >> _FPSCR_RMODE_SHIFT) & 0x3);
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return ((_fpscr >> FPSCR_RMODE_SHIFT) & 0x3);
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}
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int fesetround(int __round) {
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fenv_t _fpscr;
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fegetenv(&_fpscr);
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_fpscr &= ~(0x3 << _FPSCR_RMODE_SHIFT);
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_fpscr |= (__round << _FPSCR_RMODE_SHIFT);
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_fpscr &= ~(0x3 << FPSCR_RMODE_SHIFT);
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_fpscr |= (__round << FPSCR_RMODE_SHIFT);
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fesetenv(&_fpscr);
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return 0;
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}
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@ -102,7 +103,7 @@ int feholdexcept(fenv_t* __envp) {
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fenv_t __env;
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fegetenv(&__env);
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*__envp = __env;
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__env &= ~(FE_ALL_EXCEPT | _FPSCR_ENABLE_MASK);
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__env &= ~(FE_ALL_EXCEPT | FPSCR_ENABLE_MASK);
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fesetenv(&__env);
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return 0;
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}
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@ -118,21 +119,21 @@ int feupdateenv(const fenv_t* __envp) {
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int feenableexcept(int __mask) {
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fenv_t __old_fpscr, __new_fpscr;
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fegetenv(&__old_fpscr);
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__new_fpscr = __old_fpscr | (__mask & FE_ALL_EXCEPT) << _FPSCR_ENABLE_SHIFT;
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__new_fpscr = __old_fpscr | (__mask & FE_ALL_EXCEPT) << FPSCR_ENABLE_SHIFT;
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fesetenv(&__new_fpscr);
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return ((__old_fpscr >> _FPSCR_ENABLE_SHIFT) & FE_ALL_EXCEPT);
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return ((__old_fpscr >> FPSCR_ENABLE_SHIFT) & FE_ALL_EXCEPT);
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}
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int fedisableexcept(int __mask) {
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fenv_t __old_fpscr, __new_fpscr;
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fegetenv(&__old_fpscr);
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__new_fpscr = __old_fpscr & ~((__mask & FE_ALL_EXCEPT) << _FPSCR_ENABLE_SHIFT);
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__new_fpscr = __old_fpscr & ~((__mask & FE_ALL_EXCEPT) << FPSCR_ENABLE_SHIFT);
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fesetenv(&__new_fpscr);
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return ((__old_fpscr >> _FPSCR_ENABLE_SHIFT) & FE_ALL_EXCEPT);
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return ((__old_fpscr >> FPSCR_ENABLE_SHIFT) & FE_ALL_EXCEPT);
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}
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int fegetexcept(void) {
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fenv_t __fpscr;
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fegetenv(&__fpscr);
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return ((__fpscr & _FPSCR_ENABLE_MASK) >> _FPSCR_ENABLE_SHIFT);
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return ((__fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT);
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}
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@ -52,17 +52,12 @@ typedef __uint32_t fexcept_t;
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#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
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FE_OVERFLOW | FE_UNDERFLOW)
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#define _FPSCR_ENABLE_SHIFT 8
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#define _FPSCR_ENABLE_MASK (FE_ALL_EXCEPT << _FPSCR_ENABLE_SHIFT)
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/* Rounding modes. */
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#define FE_TONEAREST 0x0
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#define FE_UPWARD 0x1
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#define FE_DOWNWARD 0x2
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#define FE_TOWARDZERO 0x3
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#define _FPSCR_RMODE_SHIFT 22
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__END_DECLS
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#endif /* !_ARM_FENV_H_ */
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