ARM: Change dmb domain for bionic_atomic_barrier()

This patch changes the domain that the memory barrier operates on. Assumes
that the scope of bionic_atomic_barrier() does not include device memory,
memory shared with the GPU or any other memory external to the processor
cluster.

Change-Id: I291e741c98a64c86f3a3cf99811bbf1e714ac9aa
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
This commit is contained in:
Serban Constantinescu 2013-12-19 11:57:10 +00:00 committed by Elliott Hughes
parent 1afb375d30
commit 845c778fa6
4 changed files with 5 additions and 5 deletions

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@ -17,7 +17,7 @@
#define BIONIC_ATOMIC_AARCH64_H
/* For ARMv8, we can use the 'dmb' instruction directly */
__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
__ATOMIC_INLINE__ void __bionic_memory_barrier() {
__asm__ __volatile__ ( "dmb ish" : : : "memory" );
}

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@ -16,9 +16,9 @@
#ifndef BIONIC_ATOMIC_ARM_H
#define BIONIC_ATOMIC_ARM_H
__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
__ATOMIC_INLINE__ void __bionic_memory_barrier() {
#if defined(ANDROID_SMP) && ANDROID_SMP == 1
__asm__ __volatile__ ( "dmb" : : : "memory" );
__asm__ __volatile__ ( "dmb ish" : : : "memory" );
#else
/* A simple compiler barrier. */
__asm__ __volatile__ ( "" : : : "memory" );

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@ -25,7 +25,7 @@
* the architecture-specific assembler versions.
*/
__ATOMIC_INLINE__ void __bionic_memory_barrier(void) {
__ATOMIC_INLINE__ void __bionic_memory_barrier() {
__sync_synchronize();
}

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@ -25,7 +25,7 @@
*
* Macros defined in this header:
*
* void ANDROID_MEMBAR_FULL(void)
* void ANDROID_MEMBAR_FULL()
* Full memory barrier. Provides a compiler reordering barrier, and
* on SMP systems emits an appropriate instruction.
*/