d99fa58ced
Review URL: http://webrtc-codereview.appspot.com/42001 git-svn-id: http://webrtc.googlecode.com/svn/trunk@95 4adac7df-926f-26a2-2b94-8c16560cd09d
94 lines
2.3 KiB
ArmAsm
94 lines
2.3 KiB
ArmAsm
@
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@ Copyright (c) 2011 The WebRTC project authors. All Rights Reserved.
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@
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@ Use of this source code is governed by a BSD-style license
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@ that can be found in the LICENSE file in the root of the source
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@ tree. An additional intellectual property rights grant can be found
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@ in the file PATENTS. All contributing project authors may
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@ be found in the AUTHORS file in the root of the source tree.
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@ sqrt() routine. 3 cycles/bit, total 51 cycles.
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@ IN : r0 32 bit unsigned integer
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@ OUT: r0 = INT (SQRT (r0)), precision is 16 bits
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@ TMP: r1, r2
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.global WebRtcSpl_Sqrt
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.align 2
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.section .text.WebRtcSpl_Sqrt:
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WebRtcSpl_Sqrt:
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.fnstart
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MOV r1, #3 << 30
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MOV r2, #1 << 30
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@ unroll for i = 0 .. 15
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CMP r0, r2, ROR #2 * 0
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SUBHS r0, r0, r2, ROR #2 * 0
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 1
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SUBHS r0, r0, r2, ROR #2 * 1
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 2
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SUBHS r0, r0, r2, ROR #2 * 2
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 3
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SUBHS r0, r0, r2, ROR #2 * 3
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 4
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SUBHS r0, r0, r2, ROR #2 * 4
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 5
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SUBHS r0, r0, r2, ROR #2 * 5
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 6
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SUBHS r0, r0, r2, ROR #2 * 6
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 7
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SUBHS r0, r0, r2, ROR #2 * 7
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 8
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SUBHS r0, r0, r2, ROR #2 * 8
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 9
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SUBHS r0, r0, r2, ROR #2 * 9
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 10
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SUBHS r0, r0, r2, ROR #2 * 10
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 11
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SUBHS r0, r0, r2, ROR #2 * 11
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 12
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SUBHS r0, r0, r2, ROR #2 * 12
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 13
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SUBHS r0, r0, r2, ROR #2 * 13
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 14
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SUBHS r0, r0, r2, ROR #2 * 14
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ADC r2, r1, r2, LSL #1
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CMP r0, r2, ROR #2 * 15
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SUBHS r0, r0, r2, ROR #2 * 15
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ADC r2, r1, r2, LSL #1
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BIC r0, r2, #3 << 30 @ for rounding add: CMP r0, r2 ADC r2, #1
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.fnend
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