MIPS optimizations for ISAC (patch #3)
Implemented functions: - WebRtcIsacfix_MatrixProduct1 - WebRtcIsacfix_MatrixProduct2 The optimizations are bit-exact to the C code. R=andrew@webrtc.org, tina.legrand@webrtc.org Review URL: https://webrtc-codereview.appspot.com/18019004 Patch from Ljubomir Papuga <lpapuga@mips.com>. git-svn-id: http://webrtc.googlecode.com/svn/trunk@6919 4adac7df-926f-26a2-2b94-8c16560cd09d
This commit is contained in:
andrew@webrtc.org
@@ -166,4 +166,24 @@ void WebRtcIsacfix_MatrixProduct2Neon(const int16_t matrix0[],
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const int matrix0_index_step);
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#endif
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#if defined(MIPS32_LE)
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void WebRtcIsacfix_MatrixProduct1MIPS(const int16_t matrix0[],
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const int32_t matrix1[],
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int32_t matrix_product[],
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const int matrix1_index_factor1,
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const int matrix0_index_factor1,
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const int matrix1_index_init_case,
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const int matrix1_index_step,
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const int matrix0_index_step,
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const int inner_loop_count,
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const int mid_loop_count,
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const int shift);
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void WebRtcIsacfix_MatrixProduct2MIPS(const int16_t matrix0[],
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const int32_t matrix1[],
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int32_t matrix_product[],
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const int matrix0_index_factor,
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const int matrix0_index_step);
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#endif
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#endif // WEBRTC_MODULES_AUDIO_CODING_CODECS_ISAC_FIX_SOURCE_ENTROPY_CODING_H_
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@@ -0,0 +1,249 @@
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/*
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* Copyright (c) 2014 The WebRTC project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "modules/audio_coding/codecs/isac/fix/source/entropy_coding.h"
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#include "modules/audio_coding/codecs/isac/fix/source/settings.h"
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// MIPS optimization of the function WebRtcIsacfix_MatrixProduct1.
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// Bit-exact with the function WebRtcIsacfix_MatrixProduct1C from
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// entropy_coding.c file.
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void WebRtcIsacfix_MatrixProduct1MIPS(const int16_t matrix0[],
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const int32_t matrix1[],
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int32_t matrix_product[],
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const int matrix1_index_factor1,
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const int matrix0_index_factor1,
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const int matrix1_index_init_case,
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const int matrix1_index_step,
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const int matrix0_index_step,
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const int inner_loop_count,
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const int mid_loop_count,
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const int shift) {
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if (matrix1_index_init_case != 0) {
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int j = SUBFRAMES, k = 0, n = 0;
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int32_t r0, r1, r2, sum32;
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int32_t* product_start = matrix_product;
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int32_t* product_ptr;
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const uint32_t product_step = 4 * mid_loop_count;
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const uint32_t matrix0_step = 2 * matrix0_index_step;
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const uint32_t matrix1_step = 4 * matrix1_index_step;
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const uint32_t matrix0_step2 = 2 * matrix0_index_factor1;
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const uint32_t matrix1_step2 = 4 * matrix1_index_factor1;
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const int16_t* matrix0_start = matrix0;
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const int32_t* matrix1_start = matrix1;
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int16_t* matrix0_ptr;
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int32_t* matrix1_ptr;
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__asm __volatile (
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".set push \n\t"
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".set noreorder \n\t"
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"1: \n\t"
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"addu %[product_ptr], %[product_start], $0 \n\t"
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"addu %[k], %[product_step], $0 \n\t"
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"addiu %[j], %[j], -1 \n\t"
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"addu %[matrix1_start], %[matrix1], $0 \n\t"
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"2: \n\t"
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"addu %[matrix1_ptr], %[matrix1_start], $0 \n\t"
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"addu %[matrix0_ptr], %[matrix0_start], $0 \n\t"
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"addu %[n], %[inner_loop_count], $0 \n\t"
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"mul %[sum32], $0, $0 \n\t"
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"3: \n\t"
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"lw %[r0], 0(%[matrix1_ptr]) \n\t"
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"lh %[r1], 0(%[matrix0_ptr]) \n\t"
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"addu %[matrix1_ptr], %[matrix1_ptr], %[matrix1_step] \n\t"
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"sllv %[r0], %[r0], %[shift] \n\t"
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"andi %[r2], %[r0], 0xffff \n\t"
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"sra %[r2], %[r2], 1 \n\t"
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"mul %[r2], %[r2], %[r1] \n\t"
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"sra %[r0], %[r0], 16 \n\t"
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"mul %[r0], %[r0], %[r1] \n\t"
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"addu %[matrix0_ptr], %[matrix0_ptr], %[matrix0_step] \n\t"
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"addiu %[n], %[n], -1 \n\t"
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#if defined(MIPS_DSP_R1_LE)
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"shra_r.w %[r2], %[r2], 15 \n\t"
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#else
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"addiu %[r2], %[r2], 0x4000 \n\t"
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"sra %[r2], %[r2], 15 \n\t"
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#endif
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"addu %[sum32], %[sum32], %[r2] \n\t"
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"bgtz %[n], 3b \n\t"
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" addu %[sum32], %[sum32], %[r0] \n\t"
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"addiu %[k], %[k], -4 \n\t"
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"addu %[matrix1_start], %[matrix1_start], %[matrix1_step2] \n\t"
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"sw %[sum32], 0(%[product_ptr]) \n\t"
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"bgtz %[k], 2b \n\t"
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" addiu %[product_ptr], %[product_ptr], 4 \n\t"
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"addu %[matrix0_start], %[matrix0_start], %[matrix0_step2] \n\t"
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"bgtz %[j], 1b \n\t"
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" addu %[product_start], %[product_start], %[product_step] \n\t"
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".set pop \n\t"
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: [product_ptr] "=&r" (product_ptr), [product_start] "+r" (product_start),
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[k] "=&r" (k), [j] "+r" (j), [matrix1_start] "=&r"(matrix1_start),
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[matrix1_ptr] "=&r" (matrix1_ptr), [matrix0_ptr] "=&r" (matrix0_ptr),
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[matrix0_start] "+r" (matrix0_start), [n] "=&r" (n), [r0] "=&r" (r0),
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[sum32] "=&r" (sum32), [r1] "=&r" (r1),[r2] "=&r" (r2)
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: [product_step] "r" (product_step), [matrix1] "r" (matrix1),
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[inner_loop_count] "r" (inner_loop_count),
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[matrix1_step] "r" (matrix1_step), [shift] "r" (shift),
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[matrix0_step] "r" (matrix0_step), [matrix1_step2] "r" (matrix1_step2),
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[matrix0_step2] "r" (matrix0_step2)
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: "hi", "lo", "memory"
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);
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} else {
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int j = SUBFRAMES, k = 0, n = 0;
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int32_t r0, r1, r2, sum32;
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int32_t* product_start = matrix_product;
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int32_t* product_ptr;
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const uint32_t product_step = 4 * mid_loop_count;
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const uint32_t matrix0_step = 2 * matrix0_index_step;
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const uint32_t matrix1_step = 4 * matrix1_index_step;
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const uint32_t matrix0_step2 = 2 * matrix0_index_factor1;
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const uint32_t matrix1_step2 = 4 * matrix1_index_factor1;
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const int16_t* matrix0_start = matrix0;
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const int32_t* matrix1_start = matrix1;
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int16_t* matrix0_ptr;
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int32_t* matrix1_ptr;
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__asm __volatile (
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".set push \n\t"
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".set noreorder \n\t"
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"1: \n\t"
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"addu %[product_ptr], %[product_start], $0 \n\t"
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"addu %[k], %[product_step], $0 \n\t"
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"addiu %[j], %[j], -1 \n\t"
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"addu %[matrix0_start], %[matrix0], $0 \n\t"
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"2: \n\t"
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"addu %[matrix1_ptr], %[matrix1_start], $0 \n\t"
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"addu %[matrix0_ptr], %[matrix0_start], $0 \n\t"
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"addu %[n], %[inner_loop_count], $0 \n\t"
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"mul %[sum32], $0, $0 \n\t"
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"3: \n\t"
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"lw %[r0], 0(%[matrix1_ptr]) \n\t"
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"lh %[r1], 0(%[matrix0_ptr]) \n\t"
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"addu %[matrix1_ptr], %[matrix1_ptr], %[matrix1_step] \n\t"
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"sllv %[r0], %[r0], %[shift] \n\t"
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"andi %[r2], %[r0], 0xffff \n\t"
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"sra %[r2], %[r2], 1 \n\t"
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"mul %[r2], %[r2], %[r1] \n\t"
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"sra %[r0], %[r0], 16 \n\t"
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"mul %[r0], %[r0], %[r1] \n\t"
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"addu %[matrix0_ptr], %[matrix0_ptr], %[matrix0_step] \n\t"
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"addiu %[n], %[n], -1 \n\t"
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#if defined(MIPS_DSP_R1_LE)
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"shra_r.w %[r2], %[r2], 15 \n\t"
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#else
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"addiu %[r2], %[r2], 0x4000 \n\t"
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"sra %[r2], %[r2], 15 \n\t"
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#endif
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"addu %[sum32], %[sum32], %[r2] \n\t"
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"bgtz %[n], 3b \n\t"
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" addu %[sum32], %[sum32], %[r0] \n\t"
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"addiu %[k], %[k], -4 \n\t"
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"addu %[matrix0_start], %[matrix0_start], %[matrix0_step2] \n\t"
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"sw %[sum32], 0(%[product_ptr]) \n\t"
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"bgtz %[k], 2b \n\t"
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" addiu %[product_ptr], %[product_ptr], 4 \n\t"
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"addu %[matrix1_start], %[matrix1_start], %[matrix1_step2] \n\t"
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"bgtz %[j], 1b \n\t"
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" addu %[product_start], %[product_start], %[product_step] \n\t"
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".set pop \n\t"
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: [product_ptr] "=&r" (product_ptr), [product_start] "+r" (product_start),
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[k] "=&r" (k), [j] "+r" (j), [matrix1_start] "+r"(matrix1_start),
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[matrix1_ptr] "=&r" (matrix1_ptr), [matrix0_ptr] "=&r" (matrix0_ptr),
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[matrix0_start] "=&r" (matrix0_start), [n] "=&r" (n), [r0] "=&r" (r0),
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[sum32] "=&r" (sum32), [r1] "=&r" (r1),[r2] "=&r" (r2)
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: [product_step] "r" (product_step), [matrix0] "r" (matrix0),
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[inner_loop_count] "r" (inner_loop_count),
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[matrix1_step] "r" (matrix1_step), [shift] "r" (shift),
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[matrix0_step] "r" (matrix0_step), [matrix1_step2] "r" (matrix1_step2),
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[matrix0_step2] "r" (matrix0_step2)
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: "hi", "lo", "memory"
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);
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}
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}
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// MIPS optimization of the function WebRtcIsacfix_MatrixProduct2.
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// Bit-exact with the function WebRtcIsacfix_MatrixProduct2C from
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// entropy_coding.c file.
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void WebRtcIsacfix_MatrixProduct2MIPS(const int16_t matrix0[],
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const int32_t matrix1[],
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int32_t matrix_product[],
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const int matrix0_index_factor,
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const int matrix0_index_step) {
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int j = 0, n = 0;
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int loop_count = SUBFRAMES;
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const int16_t* matrix0_ptr;
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const int32_t* matrix1_ptr;
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const int16_t* matrix0_start = matrix0;
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const int matrix0_step = 2 * matrix0_index_step;
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const int matrix0_step2 = 2 * matrix0_index_factor;
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int32_t r0, r1, r2, r3, r4, sum32, sum32_2;
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__asm __volatile (
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".set push \n\t"
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".set noreorder \n\t"
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"addu %[j], %[loop_count], $0 \n\t"
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"addu %[matrix0_start], %[matrix0], $0 \n\t"
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"1: \n\t"
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"addu %[matrix1_ptr], %[matrix1], $0 \n\t"
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"addu %[matrix0_ptr], %[matrix0_start], $0 \n\t"
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"addu %[n], %[loop_count], $0 \n\t"
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"mul %[sum32], $0, $0 \n\t"
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"mul %[sum32_2], $0, $0 \n\t"
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"2: \n\t"
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"lw %[r0], 0(%[matrix1_ptr]) \n\t"
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"lw %[r1], 4(%[matrix1_ptr]) \n\t"
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"lh %[r2], 0(%[matrix0_ptr]) \n\t"
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"andi %[r3], %[r0], 0xffff \n\t"
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"sra %[r3], %[r3], 1 \n\t"
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"mul %[r3], %[r3], %[r2] \n\t"
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"andi %[r4], %[r1], 0xffff \n\t"
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"sra %[r4], %[r4], 1 \n\t"
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"mul %[r4], %[r4], %[r2] \n\t"
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"sra %[r0], %[r0], 16 \n\t"
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"mul %[r0], %[r0], %[r2] \n\t"
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"sra %[r1], %[r1], 16 \n\t"
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"mul %[r1], %[r1], %[r2] \n\t"
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#if defined(MIPS_DSP_R1_LE)
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"shra_r.w %[r3], %[r3], 15 \n\t"
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"shra_r.w %[r4], %[r4], 15 \n\t"
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#else
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"addiu %[r3], %[r3], 0x4000 \n\t"
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"sra %[r3], %[r3], 15 \n\t"
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"addiu %[r4], %[r4], 0x4000 \n\t"
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"sra %[r4], %[r4], 15 \n\t"
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#endif
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"addiu %[matrix1_ptr], %[matrix1_ptr], 8 \n\t"
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"addu %[matrix0_ptr], %[matrix0_ptr], %[matrix0_step] \n\t"
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"addiu %[n], %[n], -1 \n\t"
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"addu %[sum32], %[sum32], %[r3] \n\t"
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"addu %[sum32_2], %[sum32_2], %[r4] \n\t"
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"addu %[sum32], %[sum32], %[r0] \n\t"
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"bgtz %[n], 2b \n\t"
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" addu %[sum32_2], %[sum32_2], %[r1] \n\t"
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"sra %[sum32], %[sum32], 3 \n\t"
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"sra %[sum32_2], %[sum32_2], 3 \n\t"
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"addiu %[j], %[j], -1 \n\t"
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"addu %[matrix0_start], %[matrix0_start], %[matrix0_step2] \n\t"
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"sw %[sum32], 0(%[matrix_product]) \n\t"
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"sw %[sum32_2], 4(%[matrix_product]) \n\t"
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"bgtz %[j], 1b \n\t"
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" addiu %[matrix_product], %[matrix_product], 8 \n\t"
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".set pop \n\t"
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: [j] "=&r" (j), [matrix0_start] "=&r" (matrix0_start),
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[matrix1_ptr] "=&r" (matrix1_ptr), [matrix0_ptr] "=&r" (matrix0_ptr),
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[n] "=&r" (n), [sum32] "=&r" (sum32), [sum32_2] "=&r" (sum32_2),
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[r0] "=&r" (r0), [r1] "=&r" (r1), [r2] "=&r" (r2), [r3] "=&r" (r3),
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[r4] "=&r" (r4), [matrix_product] "+r" (matrix_product)
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: [loop_count] "r" (loop_count), [matrix0] "r" (matrix0),
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[matrix1] "r" (matrix1), [matrix0_step] "r" (matrix0_step),
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[matrix0_step2] "r" (matrix0_step2)
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: "hi", "lo", "memory"
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);
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}
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@@ -211,6 +211,8 @@ static void WebRtcIsacfix_InitMIPS(void) {
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WebRtcIsacfix_FilterMaLoopFix = WebRtcIsacfix_FilterMaLoopMIPS;
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WebRtcIsacfix_Spec2Time = WebRtcIsacfix_Spec2TimeMIPS;
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WebRtcIsacfix_Time2Spec = WebRtcIsacfix_Time2SpecMIPS;
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WebRtcIsacfix_MatrixProduct1 = WebRtcIsacfix_MatrixProduct1MIPS;
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WebRtcIsacfix_MatrixProduct2 = WebRtcIsacfix_MatrixProduct2MIPS;
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#if defined(MIPS_DSP_R1_LE)
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WebRtcIsacfix_AllpassFilter2FixDec16 =
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WebRtcIsacfix_AllpassFilter2FixDec16MIPS;
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@@ -89,6 +89,7 @@
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}],
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['target_arch=="mipsel"', {
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'sources': [
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'entropy_coding_mips.c',
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'filters_mips.c',
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'lattice_mips.c',
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'pitch_estimator_mips.c',
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